Verilog HDL. Lecture #6. Madhu Mutyam Dept. of Computer Science and Engineering Indian Institute of Technology, Madras

Transcription

1 Verilog HDL Lecture #6 Madhu Mutyam Dept. of Computer Science and Engineering Indian Institute of Technology, Madras

2 2 Verilog RTL Structural Level Verilog allows a designer to develop a complex hardware system by defining it at various levels of abstraction Behavioral level C-like procedures that express functionality Dataflow level specifying how data is processed and moved between registers Gate level interconnection of logic gates Switch level interconnection of transistors Verilog allows the designer to simulate and verify the design at each level

3 3 Verilog Resources Verilog HDL, by S. Palnitkar (department library) ALDEC's Verilog Tutorial: Gerard Blair's Verilog Tutorial: DOULOS's Verilog Tutorial: Course website

4 4 Design Methodology q0 q1 q2 q3 T_FF T_FF T_FF T_FF clock q q q q tff0 tff1 tff2 tff3 clock reset Ripple Carry Counter T_FF Ripple Carry Counter q d q D_FF reset module rcc(q, clk, reset); output [3:0] q; input clk, reset; T_FF tff0(q[0], clk, reset); T_FF tff1(q[1], q[0], reset); T_FF tff2(q[2], q[1], reset); T_FF tff3(q[3], q[2], reset); module module T_FF(q, clk, reset); output q; input clk, reset; wire d; D_FF dff0(q, d, clk, reset); not n1(d, q); module D_FF T_FF (tff0) Inverter gate D_FF T_FF (tff1) Inverter gate D_FF T_FF (tff2) Inverter gate D_FF T_FF (tff3) Inverter gate module D_FF(q, d, clk, reset); output q; input d, clk, reset; reg q; reset or negedge clk) if(reset) q = 1 b0; else q = d; module

5 5 helloworld.v Modules are the basic building-blocks Verilog uses to describe an entire hardware system. Modules are of four types: behavioral, dataflow, gate-level and switch-level. module helloworld; $display( Hello World!!! ); $finish; module System calls This is a behavioral module. Behavioral modules contain code in procedural blocks. This is a procedural block. There are two types of procedural blocks: and always. More than one statement must be put in a - group.

6 6 blockstime1.v module blockstime1; integer i, j; i = 0; j = 3; module $display( i = %d, j = %d, i, j); $finish; Integer data type: other types are time and real.

7 7 blockstime2.v module blockstime2; integer i, j; #2 i = 0; #5 j = i; Time delay models signal propagation delay in a circuit. $display( time = %d, i = %d, j = %d, $time, i, j); #3 i = 2; #10 $finish; module Multiple blocks. Delays add within each block, but different blocks all start at time $time = 0 and run in parallel (i.e., concurrently).

8 8 blockstime3.v module blockstime3; integer i, j; #2 i = 0; #5 j = i; $display( time = %d, i = %d, j = %d, $time, i, j); Important Verilog is a discrete event simulator: events are executed in a time-ordered queue. #3 i = 2; #2 j = i; $display( time = %d, i = %d, j = %d, $time, i, j); #10 $finish; module Multiple blocks. Predict output before you run!

9 9 blockstime4.v module blockstime4; integer i, j; i = 0; j = 3; #10 $finish; always #1 i = i + 1; j = j + 1; module always $display(i = %d, j = %d, i, j); always block is an infinite loop. Following are the same: Comment out this delay. Run. Explain the problem! while (1) forever

10 10 clockgenerator.v Port list. Ports can be of three types: input, output, inout. Each must be declared. module clockgenerator(clk); output clk; reg clk; clk = 0; always #5 clk = ~clk; module Internal register. Register reg data type can have one of four values: 0, 1, x, z. Registers store a value till the next assignment. Registers are assigned values in procedural blocks. If this module is run stand-alone make sure to add a $finish statement here or simulation will never complete! The delay is half the clock period.

11 11 useclock.v module useclock(clk); input clk; clockgenerator cg(clk); #50 $finish; clk) Compile with the clockgenerator.v module. Event trigger $display( Time = %d Clock up, $time); clk) $display( Time = %d Clock down, $time); module

12 12 systemcalls.v module systemclock(clk); input clk; clockgenerator cg(clk); #25 $stop; #50 $finish; module Compile with the clockgenerator.v module. Susps simulation enters interactive mode. Terminates simulation. $write( $write does not ); $write( add a new line\n ); $display( $display does ); $display( add anew line ); $monitor( Clock = %d, clk); Similar output calls except $display adds a new line. $monitor produces output each time a variable changes value.

13 13 blockstime5.v #0 delay causes the statement to execute after other processes scheduled at that time instant have completed. $time does not advance till after the statement completes. module blocktime5; integer i, j; #0 $display( time = %d, i = %d, j = %d, $time, i, j); i = 0; j = 5; #10 $finish; module Comment out the delay. Run. Explain what happens!

14 14 blockstime6.v module blocktime6; integer i, j; #2 i = 0; j = #5 i; $display( time = %d, i = %d, j = %d, $time, i, j); #3 i = 2; #10 $finish; module Intra-assignment delay: RHS is computed and stored in a temporary (transparent to user) and LHS is assigned the temporary after the delay. Compare output with blockstime2.v.

15 15 numbers.v module numbers; integer i, j; reg[3:0] x, y; module vector <base>: base can be d, b, o, h Default base: d Typical format: <size> <base><number> size is a decimal value that specifies the size of the number in bits. i = b1101; j = -1;x = 4 b1011; y = 4 d7; $display( decimal i = %d, binary i = %b, i, i); $display( octal i = %o, hex i = %h, i, i) $display( decimal j = %d, binary j = %b, j, j); $display( octal j = %o, hex j = %h, j, j) $display( decimal x = %d, binary x = %b, x, x); $display( octal x = %o, hex x = %h, x, x) $display( decimal y = %d, binary y = %b, y, y); $display( octal y = %o, hex y = %h, y, y) $finish; Array of register arrays simulate memory. Example memory declaration with 1K 32-bit words: reg[31:0] smallmem[0:1023];