Digital Design using HDLs EE 4755 Final Examination
|
|
|
- Noel Reeves
- 6 years ago
- Views:
Transcription
1 Name Digital Design using HDLs EE 4755 Final Examination Monday, 8 December :00-12:00 CST Alias Problem 1 Problem 2 Problem 3 Problem 4 Problem 5 Exam Total (20 pts) (20 pts) (20 pts) (20 pts) (20 pts) (100 pts) Good Luck!
2 Problem 1: [20 pts] The encode module below, based on Homework 4, is used to convert a decimal value to binary one ASCII digit at a time. Input val_prev is the binary value so far, and output val_next is the binary value after using ASCII character ascii_char. If ascii_char isn t a numeric digit non_digit is set to 1 and val_next is set to zero. There is also an overflow output. module encode #( int width = 32 ) (output logic [width-1:0] val_next, output logic overflow, input [7:0] ascii_char, output non_digit, input [width-1:0] val_prev); logic [width+3:0] val_curr; logic [3:0] high_bits, bin_char; assign non_digit = ascii_char < Char_0 ascii_char > Char_9; begin bin_char = ascii_char - Char_0; val_curr = 10 * val_prev + bin_char; high_bits = val_curr >> width; if ( non_digit ) begin overflow = 0; val_next = 0; else begin overflow = high_bits!= 0; val_next = val_curr; module (a) Show the hardware that will be synthesized for this module. Take into account optimizations (see the next subproblem). Synthesized hardware. (b) Indicate how many units such as adders, multipliers, shifters, and multiplexors will actually be present in the optimized hardware. The count should be based on the units that are present after optimization, not on the hardware first inferred from the Verilog. Number of adders. Number of multipliers. Number of shifters. Number of multiplexors. 2
3 Problem 2: [20 pts] Appearing below is another encode module, this one has a new input radix, which indicates the radix (base) of the number to be converted. When completed the module should function like the module from the previous problem, except that the digits form a radix-radix number. For example, if radix were 10 it would operate like the previous module. If radix were 8 the digits would be octal, etc. (a) Modify the module so that it takes into account the radix. Assume that radix can be any value from 2 to 16. Note that for a radix of 16 the valid digits are 0-9 and A-F (only consider upper case). Modify the module to generate the correct non_digit output. Modify the module to update val_next correctly given the radix. typedef enum {Char_0 = 48, Char_9 = 57, Char_A = 65, Char_F = 70} Chars; module encode_radix #( int width = 32 ) (output logic [width-1:0] val_next, output logic overflow, output non_digit, input [7:0] ascii_char, input [width-1:0] val_prev, input [4:0] radix); logic [width+3:0] val_curr; logic [3:0] high_bits, bin_char; begin val_curr = high_bits = val_curr >> width; if ( non_digit ) begin overflow = 0; val_next = 0; else begin overflow = high_bits!= 0; val_next = val_curr; module 3
4 Problem 2, continued: (b) Suppose that module encode_radix (from the previous part) were to be used in a larger design in which the values of radix could only be 2, 8, 10, and 16. Also suppose that the synthesis program can t figure out that radix is limited to these values. Why would the cost be higher than necessary, and how could encode_radix be modified to get the lower cost hardware? Explain why the cost will be higher than is necessary. Show the changes to encode_radix so that the synthesis program will generate the lower cost design. The port definitions cannot be changed. 4
5 Problem 3: [20 pts] Appearing to the right is hardware and a corresponding Verilog module. The module is incomplete, finish it. Hint: The hardware includes an -around shift, that s the part with the msb/lsb labels. Add sizes and other information to port declarations. start 32 in_pat 30:0 31:31 msb lsb find_period en en pat sh_pat = done Finish the Verilog code. 1 + en per 32 = clk module find_period (output per, output done, per input in_pat, input start, input clk); module 5
6 Problem 4: [20 pts] The Verilog below is the key lookup part of the simple CAM module used in class. logic [dwid:1] storage_data [ssize]; logic [ssize-1:0] storage_full; logic [kwid:1] storage_key [ssize]; always_comb begin mmatch = 0; midx = 0; for ( int i=0; i<ssize; i++ ) if ( storage_full[i] && storage_key[i] == key ) begin mmatch = 1; midx = i; assign out_data = storage_data[midx]; (a) Starting with the registers and key shown below, sketch the hardware synthesized for this code without optimization. The hardware should produce values for mmatch and midx (but not out_data). Do so for ssize=3. In class we often showed part of this as a box labeled priority encoder (or pri for short), in this problem actually show the hardware. Synthesized hardware for ssize = 3 to generate mmatch and midx. key storage_key[0] storage_full[0] storage_key[1] storage_full[1] storage_key[2] storage_full[2] (b) Assume that the cost of an a-bit comparison unit is a, and its delay is also a. Assume that the cost of an a-input, b-bit multiplexor is ab and the delay is 1. Compute the cost and delay of the logic used to compute midx in terms of ssize (use s in your formulas) and kwid (use k in your formulas). As with the previous part, do this for the unoptimized hardware. Remember to solve this for an arbitrary value of ssize (s), not for s = 3. Cost in terms of s and k: Delay in terms of s and k: 6
7 Problem 4, continued: Appearing below is a variation on the key lookup from the CAM module. Instead of finding a matching key it finds the largest stored key that is to the lookup key. Note that this version doesn t include storage_full. logic [dwid:1] storage_data [ssize]; logic [kwid:1] storage_key [ssize]; always_comb begin midx = 0; bkey = 0; for ( int i=0; i<ssize; i++ ) if ( storage_key[i] >= bkey && storage_key[i] <= key ) // READ THIS LINE CAREFULLY begin midx = i; bkey = storage_key[i]; assign out_data = storage_data[midx]; (c) Sketch the hardware for ssize=3. Sketch the synthesized hardware needed to generate bkey. key storage_key[0] storage_key[1] storage_key[2] (d) Compute the cost and performance in terms of ssize (use s) and the key size (use k). As before a k-bit comparison unit (equality or magnitude) costs k and has a delay of k and an a-input, b-bit mux costs ab and has a delay of 1. Hint: There s a big difference. Cost in terms of s and k: Delay in terms of s and k: 7
8 Problem 5: [20 pts] Answer each question below. (a) The module below is supposed to count from 0 to max (inclusive), then return to zero. Strictly speaking it does, but there are problems, including the fact that it s not synthesizable. Fix the problems. module counter #(int max = 3)(output logic [7:0] count, input clk); posedge clk ) begin count <= count + 1; begin module if ( count == max ) count <= 0; Why isn t the module synthesizable? Fix the problem. 8
9 (b) There is a problem with the module below due to the way that a is declared. module sa1(output a, input c, d); wire a; begin module a = c & d; Fix the problem by changing the declaration of a. Fix the problem without changing the declaration of a. (c) Describe a situation in which using always_comb has a benefit over using Situation where always_comb helps. 9
10 (d) The module below is supposed to be computing x 2 + y 2. module sa2(output logic [63:0] sos, input [63:0] x, y); logic [63:0] a1, b1, a2, b2; wire [63:0] p, s; fpmul f1(p,a1,b1); fpadd f2(s,a2,b2); begin module // Compute x^2. a1 = x; b1 = x; #1; sos = p; // Compute y^2. a1 = y; b1 = y; #1; // Compute x^2 + y^2. a2 = p; b2 = sos; #1; sos = s; Explain why the module is not synthesizable. Fix the problem. 10
Digital Design using HDLs EE 4755 Final Examination
Name Solution Digital Design using HDLs EE 4755 Final Examination Monday, 8 December 214 1:-12: CST Alias Not Synthesizable Problem 1 Problem 2 Problem 3 Problem 4 Problem 5 Exam Total (2 pts) (2 pts)
Computer Organization EE 3755 Midterm Examination
Name Computer Organization EE 3755 Midterm Examination Wednesday, 30 October 2013, 8:30 9:20 CDT Alias Problem 1 Problem 2 Problem 3 Problem 4 Problem 5 Problem 6 Problem 7 Exam Total (21 pts) (15 pts)
Digital Design using HDLs EE 4755 Midterm Examination
Name Digital Design using HDLs EE 4755 Midterm Examination Monday, 16 October 217 9:3 1:2 CDT Alias Problem 1 Problem 2 Problem 3 Problem 4 Problem 5 Problem 6 Exam Total (2 pts) (2 pts) (2 pts) (15 pts)
Digital Design using HDLs EE 4755 Midterm Examination
Name Digital Design using HDLs EE 4755 Midterm Examination Friday, 21 October 2016 12:30 13:20 CDT Alias Problem 1 Problem 2 Problem 3 Problem 4 Problem 5 Problem 6 Exam Total (20 pts) (20 pts) (20 pts)
Digital Design using HDLs EE 4755 Midterm Examination
Name Digital Design using HDLs EE 4755 Midterm Examination Monday, 1 November 214 11:3 12:2 CST Alias Problem 1 Problem 2 Problem 3 Problem 4 Problem 5 Problem 6 Exam Total (2 pts) (2 pts) (1 pts) (15
Computer Organization EE 3755 Midterm Examination
Name Computer Organization EE 3755 Midterm Examination Wednesday, 24 October 2012, 9:30 10:20 CDT Alias Problem 1 Problem 2 Problem 3 Problem 4 Problem 5 Problem 6 Problem 7 Exam Total (15 pts) (14 pts)
EE 4755 Digital Design Using Hardware Description Languages
EE 4755 Digital Design Using Hardware Description Languages Midterm Exam Review When / Where Monday, 16 October 2017, 9:30-10:20 CDT 225 Tureaud Hall (Here) Conditions Closed Book, Closed Notes Bring one
Digital Design using HDLs EE 4755 Midterm Examination
Name Digital Design using HDLs EE 4755 Midterm Examination Wednesday, 28 October 2015 11:30 12:20 CDT Alias Problem 1 Problem 2 Problem 3 Problem 4 Problem 5 Exam Total (100 pts) Good Luck! Problem 1:
Digital Design using HDLs EE 4755 Final Examination
Name Digital Design using HDLs EE 4755 Final Examination Thursday, 8 December 26 2:3-4:3 CST Alias Problem Problem 2 Problem 3 Problem 4 Problem 5 Problem 6 Exam Total (3 pts) (2 pts) (5 pts) (5 pts) (
Computer Organization EE 3755 Midterm Examination
Name Solution Computer Organization EE 3755 Midterm Examination Wednesday, 24 October 2012, 9:30 10:20 CDT Alias A Century of Turing Problem 1 Problem 2 Problem 3 Problem 4 Problem 5 Problem 6 Problem
Digital Design Using Verilog EE Final Examination
Name Digital Design Using Verilog EE 4702-1 Final Examination 8 May 2000, 7:30 9:30 CDT Alias Problem 1 Problem 2 Problem 3 Problem 4 Problem 5 Exam Total (100 pts) Good Luck! Problem 1: The modules below
FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1
FPGA Design Challenge :Techkriti 14 Digital Design using Verilog Part 1 Anurag Dwivedi Digital Design : Bottom Up Approach Basic Block - Gates Digital Design : Bottom Up Approach Gates -> Flip Flops Digital
ECE 2030D Computer Engineering Spring problems, 5 pages Exam Two 8 March 2012
Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate
Digital Design with FPGAs. By Neeraj Kulkarni
Digital Design with FPGAs By Neeraj Kulkarni Some Basic Electronics Basic Elements: Gates: And, Or, Nor, Nand, Xor.. Memory elements: Flip Flops, Registers.. Techniques to design a circuit using basic
Lecture 32: SystemVerilog
Lecture 32: SystemVerilog Outline SystemVerilog module adder(input logic [31:0] a, input logic [31:0] b, output logic [31:0] y); assign y = a + b; Note that the inputs and outputs are 32-bit busses. 17:
Introduction to Verilog/System Verilog
NTUEE DCLAB Feb. 27, 2018 Introduction to Verilog/System Verilog Presenter: Yao-Pin Wang 王耀斌 Advisor: Prof. Chia-Hsiang Yang 楊家驤 Dept. of Electrical Engineering, NTU National Taiwan University What is
In this lecture, we will go beyond the basic Verilog syntax and examine how flipflops and other clocked circuits are specified.
1 In this lecture, we will go beyond the basic Verilog syntax and examine how flipflops and other clocked circuits are specified. I will also introduce the idea of a testbench as part of a design specification.
Digital Design with SystemVerilog
Digital Design with SystemVerilog Prof. Stephen A. Edwards Columbia University Spring 25 Synchronous Digital Design Combinational Logic Sequential Logic Summary of Modeling Styles Testbenches Why HDLs?
World Inside a Computer is Binary
C Programming 1 Representation of int data World Inside a Computer is Binary C Programming 2 Decimal Number System Basic symbols: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 Radix-10 positional number system. The radix
EECS150 - Digital Design Lecture 5 - Verilog Logic Synthesis
EECS150 - Digital Design Lecture 5 - Verilog Logic Synthesis Jan 31, 2012 John Wawrzynek Spring 2012 EECS150 - Lec05-verilog_synth Page 1 Outline Quick review of essentials of state elements Finite State
LSU EE 4755 Homework 1 Solution Due: 9 September 2015
LSU EE 4755 Homework 1 Solution Due: 9 September 2015 The questions below can be answered without using EDA software, paper and pencil will suffice. Please turn in the solution on paper. Homework 2 will
ECE 2020B Fundamentals of Digital Design Spring problems, 6 pages Exam Two 26 February 2014
Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate
ECE 2300 Digital Logic & Computer Organization. More Sequential Logic Verilog
ECE 2300 Digital Logic & Computer Organization Spring 2018 More Sequential Logic Verilog Lecture 7: 1 Announcements HW3 will be posted tonight Prelim 1 Thursday March 1, in class Coverage: Lectures 1~7
Digital Integrated Circuits
Digital Integrated Circuits Lecture 4 Jaeyong Chung System-on-Chips (SoC) Laboratory Incheon National University BCD TO EXCESS-3 CODE CONVERTER 0100 0101 +0011 +0011 0111 1000 LSB received first Chung
A Verilog Primer. An Overview of Verilog for Digital Design and Simulation
A Verilog Primer An Overview of Verilog for Digital Design and Simulation John Wright Vighnesh Iyer Department of Electrical Engineering and Computer Sciences College of Engineering, University of California,
Synthesis of Language Constructs. 5/10/04 & 5/13/04 Hardware Description Languages and Synthesis
Synthesis of Language Constructs 1 Nets Nets declared to be input or output ports are retained Internal nets may be eliminated due to logic optimization User may force a net to exist trireg, tri0, tri1
HDLs and SystemVerilog. Digital Computer Design
HDLs and SystemVerilog Digital Computer Design Logic Arrays Gates can be organized into regular arrays. If the connections are made programmable, these logic arrays can be configured to perform any function
Verilog for Synthesis Ing. Pullini Antonio
Verilog for Synthesis Ing. Pullini Antonio antonio.pullini@epfl.ch Outline Introduction to Verilog HDL Describing combinational logic Inference of basic combinational blocks Describing sequential circuits
Introduction To Verilog Design. Chun-Hung Chou
Introduction To Verilog Design Chun-Hung Chou 1 Outline Typical Design Flow Design Method Lexical Convention Data Type Data Assignment Event Control Conditional Description Register Description Synthesizable
a, b sum module add32 sum vector bus sum[31:0] sum[0] sum[31]. sum[7:0] sum sum overflow module add32_carry assign
![a, b sum module add32 sum vector bus sum[31:0] sum[0] sum[31]. sum[7:0] sum sum overflow module add32_carry assign](/thumbs/91/106466219.jpg "a, b sum module add32 sum vector bus sum[31:0] sum[0] sum[31]. sum[7:0] sum sum overflow module add32_carry assign")
I hope you have completed Part 1 of the Experiment. This lecture leads you to Part 2 of the experiment and hopefully helps you with your progress to Part 2. It covers a number of topics: 1. How do we specify
Verilog Module 1 Introduction and Combinational Logic
Verilog Module 1 Introduction and Combinational Logic Jim Duckworth ECE Department, WPI 1 Module 1 Verilog background 1983: Gateway Design Automation released Verilog HDL Verilog and simulator 1985: Verilog
EE 101 Homework 4 Redekopp Name: Due: See Blackboard
EE 101 Homework 4 Redekopp Name: Due: See Blackboard Score: In this homework we will use Xilinx to complete the indicated designs. Using Xilinx to perform this homework. Please download the Xilinx EE 101
Veriolog Overview. CS/EE 3710 Fall 2010
Veriolog Overview CS/EE 3710 Fall 2010 Hardware Description Languages HDL Designed to be an alternative to schematics for describing hardware systems Two main survivors VHDL Commissioned by DOD Based on
Homework deadline extended to next friday
Norm Midterm Grading Finished Stats on course homepage Pickup after this lab lec. Regrade requests within 1wk of posted solution Homework deadline extended to next friday Description Design Conception
Digital Circuit Design and Language. Datapath Design. Chang, Ik Joon Kyunghee University
Digital Circuit Design and Language Datapath Design Chang, Ik Joon Kyunghee University Typical Synchronous Design + Control Section : Finite State Machine + Data Section: Adder, Multiplier, Shift Register
MASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences
MASSACHUSETTS INSTITUTE OF TECHNOLOGY Department of Electrical Engineering and Computer Sciences Introductory Digital Systems Lab (6.111) uiz - Spring 2004 Prof. Anantha Chandrakasan Student Name: Problem
ECE Digital Engineering Laboratory. Designing for Synthesis
ECE 554 - Digital Engineering Laboratory Designing for Synthesis Below is a list of coding styles that might cause synthesis problems and/or inefficient design implementation. This is not an exhaustive
Lecture #2: Verilog HDL
Lecture #2: Verilog HDL Paul Hartke Phartke@stanford.edu Stanford EE183 April 8, 2002 EE183 Design Process Understand problem and generate block diagram of solution Code block diagram in verilog HDL Synthesize
COMP2611: Computer Organization. Data Representation
COMP2611: Computer Organization Comp2611 Fall 2015 2 1. Binary numbers and 2 s Complement Numbers 3 Bits: are the basis for binary number representation in digital computers What you will learn here: How
Verilog for High Performance
Verilog for High Performance Course Description This course provides all necessary theoretical and practical know-how to write synthesizable HDL code through Verilog standard language. The course goes
Combinational Circuit Design
Modeling Combinational Circuits with Verilog Prof. Chien-Nan Liu TEL: 3-42275 ext:34534 Email: jimmy@ee.ncu.edu.tw 3- Combinational Circuit Design Outputs are functions of inputs inputs Combinational Circuit
Digital Design (VIMIAA01) Introduction to the Verilog HDL
BUDAPEST UNIVERSITY OF TECHNOLOGY AND ECONOMICS FACULTY OF ELECTRICAL ENGINEERING AND INFORMATICS DEPARTMENT OF MEASUREMENT AND INFORMATION SYSTEMS Digital Design (VIMIAA01) Introduction to the Verilog
Chapter 4. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 4 <1>
Chapter 4 Digital Design and Computer Architecture, 2 nd Edition David Money Harris and Sarah L. Harris Chapter 4 Chapter 4 :: Topics Introduction Combinational Logic Structural Modeling Sequential
Chapter 4. Digital Design and Computer Architecture, 2 nd Edition. David Money Harris and Sarah L. Harris. Chapter 4 <1>
Chapter 4 Digital Design and Computer Architecture, 2 nd Edition David Money Harris and Sarah L. Harris Chapter 4 Chapter 4 :: Topics Introduction Combinational Logic Structural Modeling Sequential
ECE 4514 Digital Design II. Spring Lecture 3: Verilog Bread and Butter
ECE 4514 Digital Design II Spring 2007 Verilog Difference between synthesis and simulation Modules, module declarations and instantiation Constants Numbers Data types Value Levels Regs Vectors Arrays Synthesis
EECS150 - Digital Design Lecture 4 - Verilog Introduction. Outline
EECS150 - Digital Design Lecture 4 - Verilog Introduction Feb 3, 2009 John Wawrzynek Spring 2009 EECS150 - Lec05-Verilog Page 1 Outline Background and History of Hardware Description Brief Introduction
VHDL for Synthesis. Course Description. Course Duration. Goals
VHDL for Synthesis Course Description This course provides all necessary theoretical and practical know how to write an efficient synthesizable HDL code through VHDL standard language. The course goes
Slide Set 1. for ENEL 339 Fall 2014 Lecture Section 02. Steve Norman, PhD, PEng
Slide Set 1 for ENEL 339 Fall 2014 Lecture Section 02 Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary Fall Term, 2014 ENEL 353 F14 Section
TSEA44 - Design for FPGAs
2015-11-24 Now for something else... Adapting designs to FPGAs Why? Clock frequency Area Power Target FPGA architecture: Xilinx FPGAs with 4 input LUTs (such as Virtex-II) Determining the maximum frequency
Spiral 1 / Unit 4 Verilog HDL. Digital Circuit Design Steps. Digital Circuit Design OVERVIEW. Mark Redekopp. Description. Verification.
1-4.1 1-4.2 Spiral 1 / Unit 4 Verilog HDL Mark Redekopp OVERVIEW 1-4.3 1-4.4 Digital Circuit Design Steps Digital Circuit Design Description Design and computer-entry of circuit Verification Input Stimulus
BINARY SYSTEM. Binary system is used in digital systems because it is:
CHAPTER 2 CHAPTER CONTENTS 2.1 Binary System 2.2 Binary Arithmetic Operation 2.3 Signed & Unsigned Numbers 2.4 Arithmetic Operations of Signed Numbers 2.5 Hexadecimal Number System 2.6 Octal Number System
Verilog. Reminder: Lab #1 due tonight! Fall 2008 Lecture 3
Verilog Hardware Description Languages Verilog -- structural: modules, instances -- dataflow: continuous assignment -- sequential behavior: always blocks -- pitfalls -- other useful features Reminder:
Chapter 2 Using Hardware Description Language Verilog. Overview
Chapter 2 Using Hardware Description Language Verilog CSE4210 Winter 2012 Mokhtar Aboelaze based on slides by Dr. Shoab A. Khan Overview Algorithm development isa usually done in MATLAB, C, or C++ Code
Outline. Combinational Circuit Design: Practice. Sharing. 2. Operator sharing. An example 0.55 um standard-cell CMOS implementation
Outline Combinational Circuit Design: Practice 1. Derivation of efficient HDL description 2. Operator sharing 3. Functionality sharing 4. Layout-related circuits 5. General circuits Chapter 7 1 Chapter
Combinational Circuit Design: Practice
Combinational Circuit Design: Practice Chapter 7 1 Outline 1. Derivation of efficient HDL description 2. Operator sharing 3. Functionality sharing 4. Layout-related circuits 5. General circuits Chapter
Computer Arithmetic andveriloghdl Fundamentals
Computer Arithmetic andveriloghdl Fundamentals Joseph Cavanagh Santa Clara University California, USA ( r ec) CRC Press vf J TayiorS«. Francis Group ^"*" "^ Boca Raton London New York CRC Press is an imprint
EE 109L Review. Name: Solutions
EE 9L Review Name: Solutions Closed Book / Score:. Short Answer (6 pts.) a. Storing temporary values in (memory / registers) is preferred due to the (increased / decreased) access time. b. True / False:
UNIT II - COMBINATIONAL LOGIC Part A 2 Marks. 1. Define Combinational circuit A combinational circuit consist of logic gates whose outputs at anytime are determined directly from the present combination
ECE 353 Lab 4. Verilog Review. Professor Daniel Holcomb UMass Amherst Fall 2017
ECE 353 Lab 4 Verilog Review Professor Daniel Holcomb UMass Amherst Fall 2017 What You Will Do In Lab 4 Design and implement a serial MIDI receiver Hardware in an Altera Complex Programmable Logic Device
Writing Circuit Descriptions 8
8 Writing Circuit Descriptions 8 You can write many logically equivalent descriptions in Verilog to describe a circuit design. However, some descriptions are more efficient than others in terms of the
Figure 1: Verilog used to generate divider
Abstract Compared to other arithmetic operations, division is not simple or quick in hardware. Division typically requires significantly more hardware to implement when compared to other arithmetic operations.
Computer Organization EE 3755 Final Examination
Name Computer Organization EE 3755 Final Examination Monday, 9 December 2013, 10:00 12:00 CST Alias Problem 1 Problem 2 Problem 3 Problem 4 Problem 5 Problem 6 Exam Total (16 pts) (16 pts) (16 pts) (16
Binary Arithmetic. Daniel Sanchez Computer Science & Artificial Intelligence Lab M.I.T.
Binary Arithmetic Daniel Sanchez Computer Science & Artificial Intelligence Lab M.I.T. MIT 6.004 Fall 2018 Reminder: Encoding Positive Integers Bit i in a binary representation (in right-to-left order)
Why Should I Learn This Language? VLSI HDL. Verilog-2
Verilog Why Should I Learn This Language? VLSI HDL Verilog-2 Different Levels of Abstraction Algorithmic the function of the system RTL the data flow the control signals the storage element and clock Gate
ECE2049: Embedded Computing in Engineering Design C Term Spring Lecture #3: Of Integers and Endians (pt. 2)
ECE2049: Embedded Computing in Engineering Design C Term Spring 2018 Lecture #3: Of Integers and Endians (pt. 2) Reading for Today: Davies Ch 2, MSP430 User's Guide Ch 6.1, 6.3 Reading for Next Class:
Verilog 1 - Fundamentals
Verilog 1 - Fundamentals FA FA FA FA module adder( input [3:0] A, B, output cout, output [3:0] S ); wire c0, c1, c2; FA fa0( A[0], B[0], 1 b0, c0, S[0] ); FA fa1( A[1], B[1], c0, c1, S[1] ); FA fa2( A[2],
Introduction to synthesis. Logic Synthesis
Introduction to synthesis Lecture 5 Logic Synthesis Logic synthesis operates on boolean equations and produce optimized combinational logic Logic Minimization Two-level logic minimization Two-level logic
ECE 4514 Digital Design II. Spring Lecture 13: Logic Synthesis
ECE 4514 Digital Design II A Tools/Methods Lecture Second half of Digital Design II 9 10-Mar-08 L13 (T) Logic Synthesis PJ2 13-Mar-08 L14 (D) FPGA Technology 10 18-Mar-08 No Class (Instructor on Conference)
ECE 2020B Fundamentals of Digital Design Spring problems, 6 pages Exam Two Solutions 26 February 2014
Problem 1 (4 parts, 21 points) Encoders and Pass Gates Part A (8 points) Suppose the circuit below has the following input priority: I 1 > I 3 > I 0 > I 2. Complete the truth table by filling in the input
Verilog Hardware Description Language ROOM: B405
Verilog Hardware Description Language HONG@IS.NAIST.JP ROOM: B405 Content Lecture 1: Computer organization and performance evaluation metrics Lecture 2: Processor architecture and memory system Lecture
COMP Overview of Tutorial #2
COMP 1402 Winter 2008 Tutorial #2 Overview of Tutorial #2 Number representation basics Binary conversions Octal conversions Hexadecimal conversions Signed numbers (signed magnitude, one s and two s complement,
Introduction to Verilog HDL
Introduction to Verilog HDL Ben Abdallah Abderazek National University of Electro-communications, Tokyo, Graduate School of information Systems May 2004 04/09/08 1 What you will understand after having
University of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering
University of Toronto Faculty of Applied Science and Engineering Edward S. Rogers Sr. Department of Electrical and Computer Engineering Final Examination ECE 241F - Digital Systems Examiners: S. Brown,
EE 109L Final Review
EE 09L Final Review Name: Closed Book / Score:. Short Answer (6 pts.) a. Storing temporary values in (memory / registers) is preferred due to the (increased / decreased) access time. b. True / False: A
CS16 Exam #1 7/17/ Minutes 100 Points total
CS16 Exam #1 7/17/2012 75 Minutes 100 Points total Name: 1. (10 pts) Write the definition of a C function that takes two integers `a` and `b` as input parameters. The function returns an integer holding
Verilog Fundamentals. Shubham Singh. Junior Undergrad. Electrical Engineering
Verilog Fundamentals Shubham Singh Junior Undergrad. Electrical Engineering VERILOG FUNDAMENTALS HDLs HISTORY HOW FPGA & VERILOG ARE RELATED CODING IN VERILOG HDLs HISTORY HDL HARDWARE DESCRIPTION LANGUAGE
(System)Verilog Tutorial Aleksandar Milenković
(System)Verilog Tutorial Aleksandar Milenković The LaCASA Laboratory Electrical and Computer Engineering Department The University of Alabama in Huntsville Email: milenka@ece.uah.edu Web: http://www.ece.uah.edu/~milenka
ECE 353 Lab 4. Verilog Review. Professor Daniel Holcomb With material by Professor Moritz and Kundu UMass Amherst Fall 2016
ECE 353 Lab 4 Verilog Review Professor Daniel Holcomb With material by Professor Moritz and Kundu UMass Amherst Fall 2016 Recall What You Will Do Design and implement a serial MIDI receiver Hardware in
Introduction to Verilog
Introduction to Verilog Synthesis and HDLs Verilog: The Module Continuous (Dataflow) Assignment Gate Level Description Procedural Assignment with always Verilog Registers Mix-and-Match Assignments The
ECE 2030B 1:00pm Computer Engineering Spring problems, 5 pages Exam Two 10 March 2010
Instructions: This is a closed book, closed note exam. Calculators are not permitted. If you have a question, raise your hand and I will come to you. Please work the exam in pencil and do not separate
Number Systems and Conversions UNIT 1 NUMBER SYSTEMS & CONVERSIONS. Number Systems (2/2) Number Systems (1/2) Iris Hui-Ru Jiang Spring 2010
Contents Number systems and conversion Binary arithmetic Representation of negative numbers Addition of two s complement numbers Addition of one s complement numbers Binary s Readings Unit.~. UNIT NUMBER
COMP 303 Computer Architecture Lecture 6
COMP 303 Computer Architecture Lecture 6 MULTIPLY (unsigned) Paper and pencil example (unsigned): Multiplicand 1000 = 8 Multiplier x 1001 = 9 1000 0000 0000 1000 Product 01001000 = 72 n bits x n bits =
EECS 470 Lab 6. SystemVerilog. Department of Electrical Engineering and Computer Science College of Engineering. (University of Michigan)
EECS 470 Lab 6 SystemVerilog Department of Electrical Engineering and Computer Science College of Engineering University of Michigan Thursday, October. 18 th, 2018 Thursday, October. 18 th, 2018 1 / Overview
Midterm Exam 2B Answer key
Midterm Exam 2B Answer key 15110 Principles of Computing Fall 2015 April 6, 2015 Name: Andrew ID: Lab section: Instructions Answer each question neatly in the space provided. There are 6 questions totaling
Register Transfer Level Design. Topics. Register Transfer Level Notation. Chapter 8 Steve Oldridge Dr. Sidney Fels. A Circuit is described as:
Register Transfer Level Design Chapter 8 Steve Oldridge Dr. Sidney Fels Topics RTL Notation RTL in HDL Algorithmic State Machines Sequential Binary Multiplier Control Logic HDL Design with Multiplexors
Slide Set 1. for ENEL 353 Fall Steve Norman, PhD, PEng. Electrical & Computer Engineering Schulich School of Engineering University of Calgary
Slide Set 1 for ENEL 353 Fall 2017 Steve Norman, PhD, PEng Electrical & Computer Engineering Schulich School of Engineering University of Calgary Fall Term, 2017 SN s ENEL 353 Fall 2017 Slide Set 1 slide
Lab 7 (All Sections) Prelab: Introduction to Verilog
Lab 7 (All Sections) Prelab: Introduction to Verilog Name: Sign the following statement: On my honor, as an Aggie, I have neither given nor received unauthorized aid on this academic work 1 Objective The
Computer Organization EE 3755 Final Examination
Name Computer Organization EE 3755 Final Examination Tuesday, 4 December 2012, 7:30 9:30 CST Alias Problem 1 Problem 2 Problem 3 Problem 4 Problem 5 Problem 6 Problem 7 Exam Total (15 pts) (15 pts) (20
Digital Fundamentals
Digital Fundamentals Tenth Edition Floyd Chapter 1 Modified by Yuttapong Jiraraksopakun Floyd, Digital Fundamentals, 10 th 2008 Pearson Education ENE, KMUTT ed 2009 Analog Quantities Most natural quantities
EECS 470 Lab 3. SystemVerilog Style Guide. Department of Electrical Engineering and Computer Science College of Engineering University of Michigan
EECS 470 Lab 3 SystemVerilog Style Guide Department of Electrical Engineering and Computer Science College of Engineering University of Michigan Thursday, 18 th January 2018 (University of Michigan) Lab
Verilog Execution Semantics
System Verilog (SV) is a parallel, hardware description language. SV differs from procedural languages such as C in that it models concurrency in digital logic. Logic gates operate in parallel, but software
problem maximum score 1 10pts 2 8pts 3 10pts 4 12pts 5 7pts 6 7pts 7 7pts 8 17pts 9 22pts total 100pts
University of California at Berkeley College of Engineering epartment of Electrical Engineering and Computer Sciences EECS150 J. Wawrzynek Spring 2003 2/21/03 Exam I Solutions Name: I number: This is a
2IN35 VLSI Programming Lab Work Assignment 1: Hardware design using Verilog
2IN35 VLSI Programming Lab Work Assignment 1: Hardware design using Verilog Hrishikesh Salunkhe, h.l.salunkhe@tue.nl, Alok Lele, a.lele@tue.nl April 28, 2015 1 Contents 1 Introduction 3 2 Hardware design
Speaker: Kayting Adviser: Prof. An-Yeu Wu Date: 2009/11/23
98-1 Under-Graduate Project Synthesis of Combinational Logic Speaker: Kayting Adviser: Prof. An-Yeu Wu Date: 2009/11/23 What is synthesis? Outline Behavior Description for Synthesis Write Efficient HDL
Digital Design Using Verilog EE Midterm Examination
Name Solution Digital Design Using Verilog EE 4702-1 Midterm Examination 5 April 2000 8:40-9:30 CDT Alias always @( posedge ) Problem 1 Problem 2 Exam Total (40 pts) (60 pts) (100 pts) Good Luck! Problem
Microcomputers. Outline. Number Systems and Digital Logic Review
Microcomputers Number Systems and Digital Logic Review Lecture 1-1 Outline Number systems and formats Common number systems Base Conversion Integer representation Signed integer representation Binary coded
Lab 7 (Sections 300, 301 and 302) Prelab: Introduction to Verilog
Lab 7 (Sections 300, 301 and 302) Prelab: Introduction to Verilog Name: Sign the following statement: On my honor, as an Aggie, I have neither given nor received unauthorized aid on this academic work
Digital Design. Verilo. and. Fundamentals. fit HDL. Joseph Cavanagh. CRC Press Taylor & Francis Group Boca Raton London New York
Digital Design and Verilo fit HDL Fundamentals Joseph Cavanagh Santa Clara University California, USA CRC Press Taylor & Francis Group Boca Raton London New York CRC Press is an imprint of the Taylor &
Programming with HDLs
Programming with HDLs Paul Chow February 11, 2008 1 Introduction The purpose of this document is to encourage the proper approach or mindset for programming in a hardware description language (HDL), particularly
ECE 353 Lab 3 (Verilog Design Approach)
ECE 353 Lab 3 (Verilog Design Approach) Prof Daniel Holcomb Recall What You Will Do Design and implement a serial MIDI receiver Hardware in an Altera Complex Programmable Logic Device (CPLD) MAX 7000S