Design Problem 6 Solution

Transcription

1 CSE 260 Digital Computers: Organization and Logical Design Design Problem 6 Solution Jon Turner The modifications to the VHDL for the console appear below entity console end console; architecture a1 of console is -- registers for counting memory operations by processor signal readcount, writecount: std_logic_vector(19 downto 0); begin -- process for counting memory operations process(clk) begin if rising_edge(clk) then if reset = '1' then readcount <= (others => '0'); writecount <= (others => '0'); elsif memenin = '1' then if memrwin = '1' then readcount <= readcount + 1; writecount <= writecount + 1; end process; -- process for updating display selekt <= dispcntr(4 downto 0); process(clk) begin if rising_edge(clk) then if reset = '1' then dispcntr <= (others => '0'); regselect <= (others => '0'); dispcntr <= dispcntr + 1; - 1 -

2 update <= '0'; if dispcntr(15 downto 5) = x"00" & "000" then update <= '1'; nuchar <= x"20"; case dispcntr(4 downto 0) is when "00000" => regselect <= "00"; when "01011" => if swt(0) = '0' then nuchar <= hex2ascii(int(snoopadr(15 downto 12))); nuchar <= hex2ascii(int(readcount(19 downto 16))); when "01100" => if swt(0) = '0' then nuchar <= hex2ascii(int(snoopadr(11 downto 8))); nuchar <= hex2ascii(int(readcount(15 downto 12))); when "01101" => if swt(0) = '0' then nuchar <= hex2ascii(int(snoopadr(7 downto 4))); nuchar <= hex2ascii(int(readcount(11 downto 8))); when "01110" => if swt(0) = '0' then nuchar <= hex2ascii(int(snoopadr(3 downto 0))); nuchar <= hex2ascii(int(readcount(7 downto 4))); when "01111" => if swt(0) = '0' then nuchar <= x"20"; nuchar <= hex2ascii(int(readcount(3 downto 0))); when "11011" => if swt(0) = '0' then nuchar <= hex2ascii(int(snoopdata(15 downto 12))); nuchar <= hex2ascii(int(writecount(19 downto 16))); when "11100" => if swt(0) = '0' then nuchar <= hex2ascii(int(snoopdata(11 downto 8))); nuchar <= hex2ascii(int(writecount(15 downto 12))); when "11101" => - 2 -

3 if swt(0) = '0' then nuchar <= hex2ascii(int(snoopdata(7 downto 4))); nuchar <= hex2ascii(int(writecount(11 downto 8))); when "11110" => if swt(0) = '0' then nuchar <= hex2ascii(int(snoopdata(3 downto 0))); nuchar <= hex2ascii(int(writecount(7 downto 4))); when "11111" => if swt(0) = '0' then nuchar <= x"20"; nuchar <= hex2ascii(int(writecount(3 downto 0))); when others => end case; end process; end a1;% - 3 -

4 The simulation output for part 1 is shown below. We note that the program finishes writing the maze at ms and that the final value of the read and write counts is 415,836 and 71,478. The simulation also shows the last few squares being written, providing some basic confirmation that the program is working correctly. As we make changes to the processor, we expect to see the same set of values being written to the display buffer

5 The simulation results for the second part are shown below. We note that the data written for the last few squares are consistent with the baseline simulation from part 1, that the time to write the maze is 17.1 ms and that the number of memory reads has dropped to 226,

6 The modified VHDL appears below. entity cpucache end cpucache; architecture a1 of cpucache is -- instruction cache words long -- to get synthesizer to use RAM rather than flops, -- it's necessary to define cache as array of std_logic_vectors -- rather than an array of records subtype icacherawword is std_logic_vector(24 downto 0); type icachetype is array(0 to 255) of icacherawword; signal icache: icachetype; type icacheword is record valid: std_logic; tag: std_logic_vector(15 downto 8); value: word; end record; signal icacheadr: std_logic_vector(7 downto 0); signal icachetag: std_logic_vector(15 downto 8); signal icacherawout: icacherawword; signal icacheout: icacheword; signal icachein: word; signal icachematch: std_logic; signal cachecount: std_logic_vector(7 downto 0); signal initcache: std_logic; begin icacheadr <= cachecount when initcache = '1' pc(7 downto 0) when state = fetch ireg(7 downto 0) when state = dstore iar(7 downto 0) when state = istore (others => '0'); icachetag <= pc(15 downto 8) when state = fetch pctop & ireg(11 downto 8) when state = dstore iar(15 downto 8) when state = istore (others => '0'); icacherawout <= icache(int(icacheadr)); icacheout <= (icacherawout(24), icacherawout(23 downto 16), icacherawout(15 downto 0)); icachematch <= '1' when icacheout.valid = '1' and icacheout.tag = icachetag '0' - 6 -

7 -- instruction cache process process (clk) begin if rising_edge(clk) then if reset = '1' then initcache <= '1'; cachecount <= (others => '0'); elsif initcache = '1' then cachecount <= cachecount + 1; icache(int(icacheadr)) <= (others => '0'); if cachecount = x"ff" then initcache <= '0'; elsif state = fetch and tick = x"1" then icache(int(icacheadr)) <= ('1' & icachetag & dbus); elsif icacheout.tag = icachetag then if state = dstore or (state = istore and tick = x"2") then icache(int(icacheadr)) <= ('1' & icachetag & acc); end process; process (clk) function decode(instr: word) return state_type is begin end function decode; procedure wrapup is begin end procedure wrapup; begin if rising_edge(clk) then if reset = '1' or initcache = '1' then tick <= tick + 1; -- advance time by default if state = resetstate then state <= fetch; tick <= x"0"; elsif state = pausestate then elsif state = fetch then end process; end a1; - 7 -

8 The simulation output for part 3 is shown below. Observe that the writing of the last few squares remains consistent with the earlier runs. Also note that the time to complete the maze has dropped to ms and the number of reads has dropped to 210,

9 The modifications to the CPU for part 4 are shown below. entity cpucache end cpucache; architecture a1 of cpucache is -- target address for branch instructions signal branchtarget: word; -- cache rows, two words per row subtype cacherawword is std_logic_vector(25 downto 0); type cachetype is array(0 to 127) of cacherawword; signal lcache, rcache: cachetype; type cacheword is record valid: std_logic; tag: std_logic_vector(15 downto 7); value: word; end record; signal lru: std_logic_vector(0 to 127); signal cacheadr: std_logic_vector(6 downto 0); signal cachetag: std_logic_vector(15 downto 7); signal leftcacherawout, rightcacherawout: cacherawword; signal leftcacheout, rightcacheout: cacheword; signal cachematch, leftmatch, rightmatch: std_logic; signal cachecount: std_logic_vector(6 downto 0); signal initcache: std_logic; begin branchtarget <= dpc + iregsx8; cacheadr <= cachecount when initcache = '1' pc(6 downto 0) when state = fetch ireg(6 downto 0) when state = dstore iar(6 downto 0) when state = istore (others => '0'); cachetag <= pc(15 downto 7) when state = fetch pctop & ireg(11 downto 7) when state = dstore iar(15 downto 7) when state = istore (others => '0'); leftcacherawout <= lcache(int(cacheadr)); leftcacheout <= ( leftcacherawout(25), leftcacherawout(24 downto 16), leftcacherawout(15 downto 0)); rightcacherawout <= rcache(int(cacheadr)); rightcacheout <= (rightcacherawout(25), rightcacherawout(24 downto 16), rightcacherawout(15 downto 0)); leftmatch <= '1' when leftcacheout.valid = '1' and - 9 -

10 leftcacheout.tag = cachetag '0'; rightmatch <= '1' when rightcacheout.valid = '1' and rightcacheout.tag = cachetag '0'; cachematch <= leftmatch or rightmatch; -- update cache and lru bits process (clk) begin if rising_edge(clk) then if reset = '1' then initcache <= '1'; cachecount <= (others => '0'); elsif initcache = '1' then cachecount <= cachecount + 1; lcache(int(cacheadr)) <= (others => '0'); rcache(int(cacheadr)) <= (others => '0'); lru(int(cacheadr)) <= '0'; if cachecount = x"7f" then initcache <= '0'; elsif state = fetch and tick = x"1" then if lru(int(cacheadr)) = '0' then lcache(int(cacheadr)) <= ('1' & cachetag & dbus); rcache(int(cacheadr)) <= ('1' & cachetag & dbus); lru(int(cacheadr)) <= not lru(int(cacheadr)); elsif cachematch = '1' then if state = dstore or (state = istore and tick = x"2") then if leftmatch = '1' then lcache(int(cacheadr)) <= ('1' & cachetag & acc); rcache(int(cacheadr)) <= ('1' & cachetag & acc); lru(int(cacheadr)) <= not lru(int(cacheadr)); end process; alu <= (not acc) + 1 when state = negate not acc when state = nott acc + dbus when state = add acc and dbus when state = andd acc or dbus when state = orr leftshift(acc, dbus(3 downto 0)) when state = lshift and dbus(15 downto 4) = x"000" rightshift(acc, dbus(3 downto 0)) when state = rshift and dbus(15 downto 4) = x"000" x 0000 ; process (clk)

11 function decode end function decode; procedure wrapup end procedure wrapup; begin if rising_edge(clk) then if reset = '1' or initcache = '1' then tick <= tick + 1; -- advance time by default if state = resetstate then elsif state = pausestate then elsif state = fetch then if tick = x"0" then -- check cache for data if leftmatch = '1' then state <= decode(leftcacheout.value); ireg <= leftcacheout.value; dpc <= pc; pc <= pc+1; tick <= x"0"; elsif rightmatch = '1' then state <= decode(rightcacheout.value); ireg <= rightcacheout.value; dpc <= pc; pc <= pc+1; tick <= x"0"; elsif tick = x"1" then ireg <= dbus; elsif tick = x"2" then state <= decode(ireg); dpc <= pc; pc <= pc + 1; tick <= x"0"; case state is end case; end process; process (ireg,pc,iar,acc,dpc,pctop,state,tick,cachematch,iregsx8) begin end process; end a1;

12 The simulation output for part 4 is shown below. Again, note that the writing of the last few squares remains consistent with the earlier runs. Also note that the time to complete the maze has dropped to ms and the number of reads has dropped to 190,

13 The CPU modifications for the extra credit part appear below. entity cpucache end cpucache; architecture a1 of cpucache is signal aluin: word; -- secondary alu data output -- target address for branch instructions signal branchtarget: word; -- cache rows, two words per row subtype cacherawword is std_logic_vector(25 downto 0); type cachetype is array(0 to 127) of cacherawword; signal lcache, rcache: cachetype; type cacheword is record valid: std_logic; tag: std_logic_vector(15 downto 7); value: word; end record; signal lru: std_logic_vector(0 to 127); signal cacheadr: std_logic_vector(6 downto 0); signal cachetag: std_logic_vector(15 downto 7); signal leftcacherawout, rightcacherawout: cacherawword; signal leftcacheout, rightcacheout: cacheword; signal cachematch, leftmatch, rightmatch: std_logic; signal cachecount: std_logic_vector(6 downto 0); signal initcache: std_logic; begin branchtarget <= dpc + iregsx8; cacheadr <= cachecount when initcache = '1' pc(6 downto 0) when state = fetch iar(6 downto 0) when (state = iload or state = istore) and tick >= x"2" branchtarget(6 downto 0) when state = brind ireg(6 downto 0); cachetag <= pc(15 downto 7) when state = fetch iar(15 downto 7) when (state=iload or state=istore) and tick >= x"2" branchtarget(15 downto 7) when state = brind pctop & ireg(11 downto 7); leftcacherawout <= lcache(int(cacheadr)); leftcacheout <= ( leftcacherawout(25), leftcacherawout(24 downto 16), leftcacherawout(15 downto 0)); rightcacherawout <= rcache(int(cacheadr));

14 rightcacheout <= (rightcacherawout(25), rightcacherawout(24 downto 16), rightcacherawout(15 downto 0)); leftmatch <= '1' when leftcacheout.valid = '1' and leftcacheout.tag = cachetag '0'; rightmatch <= '1' when rightcacheout.valid = '1' and rightcacheout.tag = cachetag '0'; cachematch <= leftmatch or rightmatch; -- update cache and lru bits process (clk) begin if rising_edge(clk) then if reset = '1' then initcache <= '1'; cachecount <= (others => '0'); elsif initcache = '1' then cachecount <= cachecount + 1; lcache(int(cacheadr)) <= (others => '0'); rcache(int(cacheadr)) <= (others => '0'); lru(int(cacheadr)) <= '0'; if cachecount = x"7f" then initcache <= '0'; elsif ((state = fetch or state = dload or state= add or state = andd or state = orr or state = lshift or state = rshift or state = brind or state = iload or state = istore) and tick = x"1") or (state = iload and tick = x"3") then if lru(int(cacheadr)) = '0' then lcache(int(cacheadr)) <= ('1' & cachetag & dbus); rcache(int(cacheadr)) <= ('1' & cachetag & dbus); lru(int(cacheadr)) <= not lru(int(cacheadr)); elsif cachematch = '1' then if state = dstore or (state = istore and tick = x"2") then if leftmatch = '1' then lcache(int(cacheadr)) <= ('1' & cachetag & acc); rcache(int(cacheadr)) <= ('1' & cachetag & acc); lru(int(cacheadr)) <= not lru(int(cacheadr)); elsif ((state = dload or state= add or state = andd or state = orr or state = lshift or state = rshift or state = brind or state = iload or state = istore) and tick = x"0") or (state = iload and tick = x"2") then lru(int(cacheadr)) <= leftmatch; end process;

15 aluin <= leftcacheout.value when leftmatch = '1' rightcacheout.value when rightmatch = '1' dbus; alu <= (not acc) + x"0001" when state = negate not acc when state = nott acc + aluin when state = add acc and aluin when state = andd acc or aluin when state = orr leftshift(acc, aluin(3 downto 0)) when state = lshift and aluin(15 downto 4) = x"000" rightshift(acc, aluin(3 downto 0)) when state = rshift and aluin(15 downto 4) = x"000" aluin; process (clk) function decode end function decode; procedure wrapup end procedure wrapup; begin if rising_edge(clk) then if reset = '1' or initcache = '1' then tick <= tick + 1; -- advance time by default if state = resetstate then elsif state = pausestate then elsif state = fetch then if tick = x"0" then -- check cache for data if leftmatch = '1' then state <= decode(leftcacheout.value); ireg <= leftcacheout.value; dpc <= pc; pc <= pc+1; tick <= x"0"; elsif rightmatch = '1' then state <= decode(rightcacheout.value); ireg <= rightcacheout.value; dpc <= pc; pc <= pc+1; tick <= x"0"; elsif tick = x"1" then ireg <= dbus; elsif tick = x"2" then state <= decode(ireg); dpc <= pc; pc <= pc + 1; tick <= x"0";

16 case state is when negate nott => acc <= alu; wrapup; -- branch instructions when branch => pc <= dpc + iregsx8; wrapup; when brzero => if acc = x"0000" then pc <= dpc + iregsx8; wrapup; when brpos => if acc(15) = '0' and acc /= x"0000" then pc <= dpc + iregsx8; wrapup; when brneg => if acc(15) = '1' then pc <= dpc + iregsx8; wrapup; when brind => if tick = x"0" then if cachematch = '1' then pc <= alu; wrapup; elsif tick = x"1" then pc <= dbus; wrapup; -- load instructions when mload => acc <= iregsx4; wrapup; when dload => if tick = x"0" then if cachematch = '1' then acc <= alu; wrapup; elsif tick = x"1" then acc <= dbus; wrapup; when iload => if tick = x"0" then if cachematch = '1' then iar <= alu; tick <= x"2"; elsif tick = x"1" then iar <= dbus; elsif tick = x"2" then if cachematch = '1' then acc <= alu; wrapup;

17 elsif tick = x"3" then acc <= dbus; wrapup; -- store instructions when dstore => wrapup; when istore => if tick = x"0" then if cachematch = '1' then iar <= alu; tick <= x"2"; elsif tick = x"1" then iar <= dbus; elsif tick = x"2" then wrapup; -- arithmetic and logic instructions when add andd orr lshift rshift => if tick = x"0" then if cachematch = '1' then acc <= alu; wrapup; elsif tick = x"1" then acc <= alu; wrapup; when others => state <= halt; end case; end process; process (ireg,pc,iar,acc,dpc,pctop,state,tick,cachematch,iregsx8) begin -- Memory control section (combinational) -- default values for memory control signals en <= '0'; rw <= '1'; abus <= (others => 'Z'); dbus <= (others => 'Z'); case state is when fetch => if tick = x"0" and cachematch = '0' then en <= '1'; abus <= pc; when brind => if tick = x"0" and cachematch = '0' then en <= '1'; abus <= dpc + iregsx8; when dload add andd orr lshift rshift => if tick = x"0" and cachematch = '0' then en <= '1'; abus <= pctop & ireg(11 downto 0);

18 when iload => if tick = x"0" and cachematch = '0' then en <= '1'; abus <= pctop & ireg(11 downto 0); elsif tick = x"2" and cachematch = '0' then en <= '1'; abus <= iar; when dstore => en <= '1'; rw <= '0'; abus <= pctop & ireg(11 downto 0); dbus <= acc; when istore => if tick = x"0" and cachematch = '0' then en <= '1'; abus <= pctop & ireg(11 downto 0); elsif tick = x"2" then en <= '1'; rw <= '0'; abus <= iar; dbus <= acc; when others => end case; end process; end a1;

19 The simulation output for the extra credit part is shown below. Again, note that the writing of the last few squares remains consistent with the earlier runs. Also note that the time to complete the maze has dropped to 13.4 ms and the number of reads has dropped to 68,769. It s also interesting to note in the second line from the bottom that there are long stretches where the read count is not changing, indicating that all memory reads during that period are hitting the cache

20 The table with the results from all parts is shown below. The first column shows the time for the maze program to complete. We see a reduction at each step as the cache becomes larger and/or more sophisticated. The final version produces a run time that is just over half the original. The second column shows the number of reads, which also drops as we go down in the table. It s striking that the combined instruction and data cache gives a large reduction in memory reads (almost a factor of 3 difference from the previous case), but it gives only a small reduction in run-time. The reason for this is that on the Washu2, each memory read costs just two clock cycles, since it uses on-chip SRAM and the clock period is fairly long. Since the combined I-D cache saves us about 120,000 reads, this translates to 2.4 million ns or 2.4 ms, which is roughly the difference in the run times for the last to rows. The third column shows the number of memory writes, which never changes. The penultimate column shows the minimum clock period reported by the synthesizer, and the last column shows what the run time of the program would be, if the processor clock was adjusted to match the minimum clock period. We note that the fastest completion time for the program is for the first cache design. While the others reduce the number of memory accesses, they do require a larger clock period, and this leads to worse overall performance. It s also worth noting that the no-cache case is only about 20% slower than the fastest cache-based design. This illustrates that a fast simple circuit can sometimes be a better choice than a more sophisticated but slower circuit. One should not conclude from this that cache s aren t worth the trouble. For a processor in which the memory access time is much larger than the instruction execution time, caches are indispensable. However, on a processor like the WashU-2, a cache provides a relatively small improvement