Design Problem 4 Solution

Transcription

1 CSE 260 Digital Computers: Organization and Logical Design Design Problem 4 Solution Jon Turner Due 4/13/06 1. (125 points). In this problem, you will design a packet FIFO, which is a circuit that temporarily stores variable length packets of information. Your circuit will have two interfaces. The left interface includes a four bit data input called din, a single bit input, called sopin (sop stands for start-of-packet) and two single bit outputs, ack (which stands for acknowledgement) and errsig (which indicates an error has occorred). The right interface will have a four bit data output called dout, one single bit output, sopout and a single bit input called ok2send. Packets are sent to the left interface on the din input. The sopin input is high during the clock tick when the first word of a packet is input. The value of the first word specifies the total number of words in the packet; this number must be at least three and no more than six. On receiving the first word of a new packet, your circuit should make sure that there is enough space available to store the entire packet. If there is, then the ack input should be high during the clock edge when the second word of the packet is received. If the packet will not fit in the available space, your circuit should not attempt to store it in memory and should not raise the ack signal. Your circuit should enter an error state if the length specified in the first word of a packet is out of range. When it is in the error state, the errsig output should go high, and it should remain high until the circuit is reset. The interface does not need to handle back-to-back packets. There should be one idle clock tick between receiving the last word of one packet and the first word of the next. Whenever the circuit contains at least one complete packet, the right interface should send a packet out using the dout output, if the ok2send input is high. The sopout output should be asserted as the first word of the packet is sent out. Once the circuit starts to send a packet out, it should continue until all words of the packet have been sent, even if ok2send drops after the first word goes out. Your circuit should be called pfifo and should include a memory called pstore with space to store a total of 16 words. Your circuit should also include two counters nwords which gives the number of words in the memory that are currently occupied by packets, and npkts, which gives the number of packets that have been completely received and have not yet been completely sent out. Your circuit may also include other registers. In addition to the signals mentioned above, your circuit will also have a synchronous reset input. When the reset input is asserted, any stored data is discarded and the inputs are ignored until reset goes low. Your design notes should include a detailed description of the function of what the circuit does (essentially a paraphrasing of the description given above, in your own words) and two timing diagrams, one for the left interface and one for the right interface. The - 1 -

2 timing diagram for the left interface should show a typical packet arrival. The timing diagram for the right interface should show a typical packet departure. Your design notes should also include a block diagram of your circuit showing all the major components (such as the memory, the registers and the controllers for the left and right interfaces) all the input and output signals and the major signals that go between the components. Your notes should include a state transition diagram for each of the two controllers. Finally, your design notes should include a description of your testing strategy. Implement your design using VHDL and turn in a printed copy. Your VHDL should be carefully documented so that it is self-contained and easy for a reader to understand. To synthesize this circuit, you will need to turn off the default synthesis option for RAM extraction. To do this, right click on Synthesize in the Process window of Project Navigator and select Properties. In the HDL Options tab, turn off the check box for RAM Extraction. Using your block diagram and your VHDL, estimate the resources that your circuit will require (number of flip flops and LUTs). Compare your estimates to the numbers reported in the synthesis report. Look at the sections of the synthesis report labeled HDL Synthesis and Macro Statistics, to help you with this. To get a better understanding of the resource usage, try re-synthesizing your circuit, optimizing for area, instead of speed (access the synthesis options by right-clicking on synthesize in the Process window of Project Navigator). Also, try changing the word-size of your circuit from 4 bits to 8 bits or 16 bits, to see how this affects the overall LUT count. Perform a functional simulation that demonstrates that your circuit works correctly (be thorough) and turn in your printout. Your simulation should be based on the testing strategy outlined in your design notes. Format your simulation output to make it easy for another person to verify that your circuit works correctly. Format counter values and data values using hexadecimal rather than binary. Group related signals together in some logical fashion. Show values of all your internal registers and the states of your state machines. Show the values stored in pstore. Add annotations to the simulation output, pointing out the different parts of the test and be sure to verify that the circuit works correctly. Perform a timing simulation of your circuit and turn in your printout. Choose the clock period for your timing simulation based on the timing information you get from the synthesis report. Your clock period will need to be at least as large as the estimated period given in the synthesis report. It should also be at least as large as the input arrival time given in the synthesis report. To set the clock period for your simulation, right click in the Testbench Waveform tool and select Re-scale timing. Change the clock period in the dialog box that comes up. You should also change the Input Setup Time to be at least equal to the input arrival time specified by the synthesis report. Set the field called Output Valid Delay so that the sum of this and the Input Setup Time is smaller than the clock period (the tool requires this, but it has no direct impact on your simulation). In order for your timing simulation to work correctly, you will need to make the reset period at the start of your simulation last for at least 100 ns. It s a good idea to use this long reset period in your functional simulation as well. That way, you can use the same testbench waveform file for both simulations. Make sure that the timing simulation output is consistent with your functional simulation. You won t be able to see all the internal signals in your timing simulation, but you should be able to observe the register values and be able to verify that the outputs are - 2 -

3 correct. If the timing simulation does not work, try increasing the clock period until you find a clock period for which it does work correctly. Turn in a printout showing that it does work correctly and report what clock period you used. Also use the timing simulation to measure the delays from when the clock changes to when the internal registers in your circuit change. Also measure the time from when the clock changes to when the acknowledgement and dout signals change. Compare the values measured from your simulation to the corresponding values in the synthesis report. Add extra cursors to your ModelSim waveform display when making these measurements. Turn in the portion of your simulation output showing these measurements and highlight them on your printout. Send a copy of your VHDL source file to jon.turner@wustl.edu. Please name your attachment dp4-yourname.vhd where yourname is your first and last names (e.g. jonturner)

4 Packet Fifo Design Notes. Description. The packet FIFO stores variable length packets of information. It has two interfaces. The left interface includes a four bit data input called din, a single bit input, called sopin (sop stands for start-of-packet) and two single bit outputs, ack (which stands for acknowledgement) and errsig (which indicates an error has occorred). The right interface will have a four bit data output called dout, one single bit output, sopout and a single bit input called ok2send. Packets are sent to the left interface on the din input. The sopin input is high during the clock tick when the first word of a packet is received. The value of the first word specifies the total number of words in the packet; this number must be at least three and no more than six. On receiving the first word of a new packet, the circuit checks that there is enough space available to store the entire packet. If there is, then the ack input is raised high before the clock edge on which the second word of the packet is received. If the packet will not fit in the available space, the circuit does not attempt to store it in memory and does not raise the ack signal. The circuit enters an error state if the length specified in the first word of a packet is out of range. When it is in the error state, the errsig output goes high, and remains high until the circuit is reset. The interface does not handle back-to-back packets. There must be one idle clock tick between receiving the last word of one packet and the first word of the next. Whenever the circuit contains at least one complete packet, the right interface sends a packet out using the dout output, if the ok2send input is high. The sopout output should be asserted as the first word of the packet is sent out. Once the circuit starts to send a packet out, it should continue until all words of the packet have been sent, even if ok2send drops after the first word goes out

5 Timing Diagrams. The timing diagrams below show a typical packet arrival on the left interface and a departure on the right interface. left interface clk sopin din ack 00 x04 x01 x02 x03 00 right interface clk ok2send sopout din x04 x01 x02 x

6 Block Diagram. The block diagram of the circuit is shown below. The data path consists of the pstore block and the demultiplexor preceding it and multiplexor following it. The input demultiplexor must do two things. First, it must steer the arriving data bits to the correct word of pstore. Second, it must generate a Load signal for each of the 16 words. Both functions can be implemented with a decoder that decodes the value of wpntr and has an output enable. The control part of the circuit has a total of six registers. InCnt is a down counter used to keep track of how many words are left to receive in the incoming packet. It is initialized from the value of din during the clock tick when the first word of the packet arrives. OutCnt serves a similar function on the output side. The registers wpntr and rpntr are pointers to the locations in pstore where the next word is to be written or read, respectively. The registers npkts and nwords keep track of the number of complete packets in pstore and the number of words used in pstore. NPkts is incremented when the last word of a packet is received and decremented when the last word is sent out. The two state machines ctlleft and ctlright handle the input and output interfaces respectively. CtlLeft includes an error state, which it enters if a packet is received with an incorrect length. The state machines each have exclusive control over two registers and they share the control of npkts and nwords. Because npkts and nwords can be incremented by ctlleft and decremented by ctlright, they must be handled separately. The two state machines provide output signals to increment and decrement them. These are treated as inputs by the registers, which do not change values whenever both of their control inputs are asserted at the same time. din 4 pstore 16x4 4 dout incnt wpntr rpntr outcnt LD LD -1 sopin ack error ctlleft idle busy errstate +1 npkts nwords -1 ctlright idle busy sopout ok2send - 6 -

7 State Transition Diagrams. The state diagrams for the two controllers are shown below. These are high level state diagrams with conditions and actions labeling the edges, rather than explicit inputs and outputs. ctlleft idle condition: sopin=1 and (din<3 or din>6) action: none condition: condition: incnt=1 sopin=1 and 3<=dIn<=6 and action: nwords+din<=16 increment nwords action: increment wpntr load incnt=din-1 increment npkts increment nwords increment wpntr write to pstore busy condition: action: incnt>1 decrement incnt increment nwords increment wpntr write to pstore errstate ctlright condition: outcnt=1 action: decrement nwords increment rpntr decrement npkts idle condition: ok2send=1 and npkts>0 action: load outcnt=dout busy condition: action: outcnt>1 decrement outcnt decrement nwords increment rpntr - 7 -

8 Testing Strategy. Before devising a specific testing strategy, we first list the features of the three state machines that we need to check. For the left interface controller, we need to verify the following. - Interface accepts packets for which the size is in range and there is room in pstore and stores them in pstore correctly. - Acknowledgements are produced for packets that should be accepted and at the right time. - Interface does not accept a packet for which the pstore does not have room. - When pstore drains sufficiently to make room for a waiting packet, pstore accepts the packet. - Interface rejects packets for which the size is out of range and goes into the error state. - Reset forces controller into its initial state and clears registers appropriately. For the right interface controller, we need to verify the following. - Interface sends packets out correctly when there is a complete packet and the ok2send input is asserted. This includes generating the sopout signal at the appropriate time. - Interface waits to send packet if ok2send is not asserted. - Interface does not attempt to send packets when there is no valid packet present. - Reset forces controller into its initial state and clears registers appropriately. For the controller that handles the two shared registers (nwords, npkts), we need to verify that they are incremented and decremented appropriately. In particular, we should test the case when there are simultaneous increment/decrement signals to these registers, meaning that their values should remain unchanged. And we also need to verify that reset puts them back in the initial state. To test all of these features, the test starts with ok2send low, allowing pstore to fill up with packets. We then attempt to add another packet, in order to check that leftctl refuses to accept it. We then raise ok2send, allowing packets to drain out. This also allows us to check that the waiting packet enters as soon as pstore has room for it. We then start a new packet in, timing its arrival so that it finishes at the same time as an outgoing packet. This allows us to verify that npkts does not change in the case where there are simultaneous increment/decrement signals present. The last phase of the test attempts to send two packets whose sizes are out of range. This allows us to verify that we enter errstate and raise errsig, and that the reset re-initializes everything

9 VHDL. library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; -- Packet FIFO -- Jon Turner - 3/23/ The packet FIFO stores variable length "packets" of information. -- It has two interfaces. The "left" interface handles incoming packets -- The "right" interface handles outgoing packets The design uses a separate controller for each interface, and -- stores packets in a bank of registers called pstore. -- It maintains six separate counters, which are detailed below. entity pfifo is port( clk, reset: in std_logic; -- left interface din: in std_logic_vector(3 downto 0); sopin: in std_logic; ack: out std_logic; errsig: out std_logic; -- data input -- start of packet -- acknowledgement -- indicates packet length error -- right interface dout: out std_logic_vector(3 downto 0); -- data output sopout: out std_logic; -- start of packet ok2send: in std_logic -- allows sending of packets ); end pfifo; architecture arch1 of pfifo is constant wsiz : integer := 4; constant pssiz : integer := 16; constant lgpssiz : integer := 4; constant lgnpkts: integer := 3; -- word size -- # of words in packet store -- # of bits to represent pssize-1 -- # of bits to represent npkts -- number of words left to arrive/leave signal incnt: std_logic_vector(wsiz-1 downto 0); signal outcnt: std_logic_vector(wsiz-1 downto 0); -- pointer to next word to write/read signal wpntr: std_logic_vector(lgpssiz-1 downto 0); signal rpntr: std_logic_vector(lgpssiz-1 downto 0); -- number of words/packets stored signal nwords: std_logic_vector(lgpssiz-1 downto 0); signal npkts: std_logic_vector(lgnpkts-1 downto 0); -- Packet store type pstoretype is array(0 to pssiz-1) of std_logic_vector(wsiz-1 downto 0); signal pstore: pstoretype; -- state machines controlling input and output type leftctltype is (idle, busy, errstate); signal leftctl: leftctltype; type rightctltype is (idle, busy); signal rightctl: rightctltype; -- auxiliary signals signal inrange: std_logic; signal validarrival: std_logic; signal enoughroom: std_logic; -- asserted when din is a valid packet length -- asserted when packet arrival starts -- asserted enough room for arriving packet - 9 -

10 signal nwordsplus: std_logic; signal nwordsminus: std_logic; signal npktsplus: std_logic; signal npktsminus: std_logic; -- asserted when nwords should be incremented -- asserted when nwords should be decremented -- asserted when npkts should be incremented -- asserted when npkts should be decremented -- more concise type conversion function function int(d: std_logic_vector) return integer is begin return conv_integer(unsigned(d)); end function int; begin inrange <= '1' when din >= x"3" and din <= x"6" else '0'; enoughroom <= '1' when (('0' & din) + ('0' & nwords)) <= pssiz else '0'; validarrival <= '1' when leftctl = idle and sopin = '1' and inrange = '1' and enoughroom = '1' else '0'; -- process for left controller process (clk) begin if clk'event and clk = '1' then ack <= '0'; if reset = '1' then leftctl <= idle; incnt <= (incnt'range => '0'); wpntr <= (wpntr'range => '0'); else if leftctl = idle then if validarrival = '1' then pstore(int(wpntr)) <= din; incnt <= din - 1; wpntr <= wpntr + 1; ack <= '1'; leftctl <= busy; elsif sopin = '1' and inrange = '0' then leftctl <= errstate; elsif leftctl = busy then pstore(int(wpntr)) <= din; incnt <= incnt - 1; wpntr <= wpntr + 1; if incnt = 1 then leftctl <= idle; end process; -- outputs of left controller npktsplus <= '1' when leftctl = busy and incnt = 1 else '0'; nwordsplus <= '1' when leftctl = busy or validarrival = '1' else '0'; errsig <= '1' when leftctl = errstate else '0'; -- process for updating nwords and npkts process(clk) begin if clk'event and clk = '1' then if reset = '1' then nwords <= (nwords'range => '0'); npkts <= (npkts'range => '0'); else if nwordsplus > nwordsminus then nwords <= nwords + 1; elsif nwordsplus < nwordsminus then nwords <= nwords - 1; if npktsplus > npktsminus then npkts <= npkts + 1; elsif npktsplus < npktsminus then

11 npkts <= npkts - 1; end process; -- process for right controller process (clk) begin if clk'event and clk = '1' then sopout <= '0'; if reset = '1' then rightctl <= idle; outcnt <= (outcnt'range => '0'); rpntr <= (rpntr'range => '0'); else if rightctl = idle then if ok2send = '1' and npkts > 0 then outcnt <= pstore(int(rpntr)); rightctl <= busy; sopout <= '1'; elsif rightctl = busy then outcnt <= outcnt - 1; rpntr <= rpntr + 1; if outcnt = 1 then rightctl <= idle; end process; -- outputs of right controller npktsminus <= '1' when rightctl = busy and outcnt = 1 else '0'; nwordsminus <= '1' when rightctl /= idle else '0'; dout <= pstore(int(rpntr)); end arch1;

12 Implementation Complexity. The relevant section of the simulation report is shown below. Notes have been added below in bold and certain parts of the output have also been highlighted to call attention to certain points. ========================================================================= * HDL Synthesis * ========================================================================= Synthesizing Unit <pfifo>. Related source file is C:/260designs/sequential/vhdlNZ/pFIFO/pFIFO.vhd. Found finite state machine <FSM_0> for signal <leftctl> States 3 Transitions 7 Inputs 4 Outputs 3 Clock clk (rising_edge) Reset reset (positive) Reset type synchronous Reset State idle Power Up State idle Encoding automatic Implementation LUT Found 1-bit register for signal <ack>. Found 4-bit 16-to-1 multiplexer for signal <dout>. Found 1-bit register for signal <sopout>. Found 4-bit subtractor for signal <$n0028> created at line 91. Found 4-bit comparator greater for signal <$n0059> created at line 74. Found 6-bit comparator lessequal for signal <$n0081> created at line 75. Found 4-bit comparator greatequal for signal <$n0082> created at line 73. Found 4-bit comparator lessequal for signal <$n0083> created at line 73. Found 4-bit adder carry out for signal <$n0084> created at line 75. Found 4-bit down counter for signal <incnt>. Found 3-bit updown counter for signal <npkts>. Found 4-bit updown counter for signal <nwords>. Found 4-bit down counter for signal <outcnt>. Found 64-bit register for signal <pstore>. Found 1-bit register for signal <rightctl<0>>. Found 4-bit up counter for signal <rpntr>. Found 4-bit up counter for signal <wpntr>. Registers have been highlighted above. Adding up the sizes gives a total of 90 flip flops. This does not include the flip flops for the finite state machine, which will use 2 or 3. The low level report below lists 95 flip flops, so the reported number is within 2 or 3 of what we would expect from the numbers above, or from an inspection of the VHDL source code. Summary: inferred 1 Finite State Machine(s). inferred 6 Counter(s). inferred 67 D-type flip-flop(s). inferred 2 Adder/Subtracter(s). inferred 4 Comparator(s). inferred 4 Multiplexer(s). Unit <pfifo> synthesized. ========================================================================= * Advanced HDL Synthesis * ========================================================================= Advanced RAM inference... Advanced multiplier inference

13 Advanced Registered AddSub inference... Selecting encoding for FSM_0... Optimizing FSM <FSM_0> on signal <leftctl> with one-hot encoding. Dynamic shift register inference... ========================================================================= HDL Synthesis Report Macro Statistics # FSMs : 1 # Adders/Subtractors : 2 4-bit adder carry out : 1 estimate 8 LUTs 4-bit subtractor : 1 8 LUTs # Counters : 6 3-bit updown counter : 1 npkts (3 FFs + 6 LUTs) 4-bit updown counter : 1 nwords (4 FFs + 8 LUTs) 4-bit down counter : 2 incnt, outcnt (8 FFs + 8 LUTs) 4-bit up counter : 2 rpntr, wpntr (8 FFs + 8 LUTs) # Registers : 22 4-bit register : 16 pstore (64 FFs) 1-bit register : 6 state machines, sopout, ack (6 FFs) # Comparators : 4 4-bit comparator lessequal : LUTs per bit 4-bit comparator greatequal : 1 8 LUTs 6-bit comparator lessequal : 1 12 LUTs 4-bit comparator greater : 1 8 LUTs # Multiplexers : 1 4-bit 16-to-1 multiplexer : 1 for pstore output (60 LUTs) Combining the estimates above gives 93 FFs LUTs. The FF count is very close to the 95 reported below and the two replicated FFs mentioned just below account for the difference. The LUT count is less than half the total of 329, so there are clearly LUTs that aren t reported in the Macro Statistics table. We would expect each bit in pstore to require 1 LUT for feeding back the currently stored value, so this adds 64. Some additional LUTs will be used for the input section of pstore to decode the value of wpntr to create the enables for the individual registers that make up pstore. One or two LUTs per word in pstore should be enough for this, so this adds 16 LUTs to 32 LUTs. The next state logic for the state machines would add maybe 2 LUTs per FF input, so that adds 8 LUTs. The sopout and ack outputs might each require another 2 LUTs. Adding these in brings the total number of estimated LUTs to 234 to 250. This is still significantly 100 fewer than the 329 reported below. When the circuit is synthesized to optimize for area rather than speed, the number of LUTs drops to 183. Our estimate of 234 is considerably higher than this, but the fact that our estimate is bracketed by the estimates given by the synthesizer provides some confidence that the synthesizer is at least making reasonable choices in optimizing the circuit. As a further experiment, I re-synthesized the circuit using an 8 bit word and a 16 bit word, optimizing for area. This gave LUT counts of 302 and 533 respectively. Since the increase in the number of words in pstore is 64 and 128 in these two cases, it appears that the number of LUTs per bit of pstore is about 1.8, since we would expect almost all the increase in LUTs in these cases to be directly associated with the bits in pstore. ========================================================================= ========================================================================= * Low Level Synthesis * ========================================================================= Optimizing unit <pfifo>... Loading device for application Xst from file '3s200.nph' in environment C:/Xilinx

14 Mapping all equations... Building and optimizing final netlist... Found area constraint ratio of 100 (+ 5) on block pfifo, actual ratio is 4. FlipFlop leftctl_ffd3 has been replicated 1 time(s) FlipFlop leftctl_ffd2 has been replicated 1 time(s) Replicated flip flops added to improve performance (by reducing fanout of flip flop outputs). These add to total flip flop count, below. ========================================================================= * Final Report * ========================================================================= Final Results RTL Top Level Output File Name : pfifo.ngr Top Level Output File Name : pfifo Output Format : NGC Optimization Goal : Speed Keep Hierarchy : NO Design Statistics # IOs : 15 Macro Statistics : # Registers : 25 # 1-bit register : 3 # 3-bit register : 6 # 4-bit register : 16 # Multiplexers : 1 # 4-bit 16-to-1 multiplexer : 1 # Adders/Subtractors : 1 # 4-bit adder carry out : 1 # Comparators : 4 # 4-bit comparator greatequal : 1 # 4-bit comparator greater : 1 # 4-bit comparator lessequal : 1 # 6-bit comparator lessequal : 1 # Xors : 12 # 1-bit xor3 : 12 Cell Usage : # BELS : 368 # GND : 1 # LUT1 : 5 # LUT2 : 13 # LUT2_D : 1 # LUT2_L : 3 # LUT3 : 54 # LUT3_D : 1 # LUT3_L : 62 # LUT4 : 112 # LUT4_D : 6 # LUT4_L : 72 # MUXCY : 4 # MUXF5 : 18 # MUXF6 : 8 # MUXF7 : 4 # VCC : 1 # XORCY : 3 # FlipFlops/Latches : 95 # FDE : 64 # FDR : 4 # FDRE : 24 # FDRS : 1 # FDS : 2 # Clock Buffers : 1 # BUFGP : 1 # IO Buffers :

15 # IBUF : 7 # OBUF : 7 ========================================================================= Device utilization summary: Selected Device : 3s200ft256-5 Number of Slices: 176 out of % Number of Slice Flip Flops: 95 out of % Number of 4 input LUTs: 329 out of % Number of bonded IOBs: 14 out of 173 8% Number of GCLKs: 1 out of 8 12%

16 Functional Simulation. The first section of the simulation is shown below. Ok2send is held low during this part so that packets fill pstore, as can be seen at the bottom of the figure. The callouts point out the main items of significance. Arrivals with proper packet sizes. Expected state changes. incnt and wpntr working correctly nwords and npkts working correctly correct data stored in pstore

17 This next part shows that packets are not accepted until there is room for them and that npkts is not modified when an arrival and departure complete at the same time. Packet blocked at input until room, then accepted. No change to npkts on simultaneous arrival, departure Outgoing packets New data replacing old in pstore

18 The final part of the simulation shows the transitions to and from the error state. Wrong packet lengths trigger transition to errstate and raise errsig. Reset restores initial state

19 Timing Simulation. The synthesis report claims that the circuit will run with a clock period of 7 ns (see below), but it also reports that inputs can take over 8.5 ns to get from input pads to flip flops. With this in mind, I simulated the circuit with a clock period of 12 ns and allowed 9 ns for signals to propagate from input pads to the internal flip flops. The circuit worked correctly at this clock rate. The first panel below shows the start of the simulation run that was used for the functional Packets received Packets forwarded 3.2 ns clk to change in nwords, npkts 8.5 ns clk to change in ack 10.8 ns clk to change in dout

20 simulation. The second panel shows additional detail. From this detailed view, we can see that nwords and npkts change 3.2 ns after the clock. The ack output changes 8.5 ns after the clock and the dout output changes 10.8 ns after the clock. It makes sense that nwords and npkts have a very short delay, since these are internal signals. Ack and dout are both external signals. We would expect dout to have longer delay since changes to dout must ripple through an output multiplexor used to select one word of the 16 in pstore. There are fewer stages of logic needed to produce the Ack signal. The delays in the simulation differ somewhat from the delays mentioned in the synthesis report. In particular, the detailed timing section of the synthesis report shows that the delay from clock to Q for the internal flip flops is 1.4 ns, whereas the simulation shows a delay of 3.2 ns. The delay measured for dout(10.8 ns) is also somewhat larger than the number that appears in the synthesis report (8 ns). These differences result from the fact that the synthesis report is based on estimates for a circuit that has not been mapped onto the actual chip. The simulation report, on the other hand, is based on the actual mapping of the circuit onto the chip and has more accurate delay information

21 Timing section of synthesis report. Timing Summary: Speed Grade: -5 Minimum period: 6.990ns (Maximum Frequency: MHz) Minimum input arrival time before clock: 8.539ns Maximum output required time after clock: 8.045ns Maximum combinational path delay: No path found Timing Detail: All values displayed in nanoseconds (ns) Timing constraint: Default period analysis for Clock 'clk' Delay: 6.990ns (Levels of Logic = 7) Source: nwords_0 (FF) Destination: nwords_3 (FF) Source Clock: clk rising Destination Clock: clk rising Data Path: nwords_0 to nwords_3 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) FDRE:C->Q nwords_0 (nwords_0) LUT2_D:I1->LO pfifo n0149<0>lut (N6935) MUXCY:S->O pfifo n0149<0>cy (pfifo n0149<0>_cyo) MUXCY:CI->O pfifo n0149<1>cy (pfifo n0149<1>_cyo) MUXCY:CI->O pfifo n0149<2>cy (pfifo n0149<2>_cyo) XORCY:CI->O pfifo n0149<3>_xor (_n0149<3>) LUT4_D:I3->O _n (CHOICE138) LUT4:I0->O _n01231 (_n0123) FDRE:CE nwords_ Total 6.990ns (3.919ns logic, 3.071ns route) (56.1% logic, 43.9% route) Timing constraint: Default OFFSET IN BEFORE for Clock 'clk' Offset: 8.539ns (Levels of Logic = 8) Source: din<0> (PAD) Destination: nwords_3 (FF) Destination Clock: clk rising Data Path: din<0> to nwords_3 Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name) IBUF:I->O din_0_ibuf (din_0_ibuf) LUT2_D:I0->LO pfifo n0149<0>lut (N6935) MUXCY:S->O pfifo n0149<0>cy (pfifo n0149<0>_cyo) MUXCY:CI->O pfifo n0149<1>cy (pfifo n0149<1>_cyo) MUXCY:CI->O pfifo n0149<2>cy (pfifo n0149<2>_cyo) XORCY:CI->O pfifo n0149<3>_xor (_n0149<3>) LUT4_D:I3->O _n (CHOICE138) LUT4:I0->O _n01231 (_n0123) FDRE:CE nwords_ Total 8.539ns (4.972ns logic, 3.567ns route) (58.2% logic, 41.8% route) Timing constraint: Default OFFSET OUT AFTER for Clock 'clk' Offset: 8.045ns (Levels of Logic = 5) Source: rpntr_0 (FF) Destination: dout<3> (PAD) Source Clock: clk rising Data Path: rpntr_0 to dout<3> Gate Net Cell:in->out fanout Delay Delay Logical Name (Net Name)

22 FDRE:C->Q rpntr_0 (rpntr_0) LUT3:I0->O Mmux_dOut_inst_lut3_81 (Mmux_dOut net15) MUXF5:I0->O Mmux_dOut_inst_mux_f5_4 (Mmux_dOut net17) MUXF6:I0->O Mmux_dOut_inst_mux_f6_2 (Mmux_dOut net21) MUXF7:I0->O Mmux_dOut_inst_mux_f7_1 (dout_1_obuf) OBUF:I->O dout_1_obuf (dout<1>) Total 8.045ns (6.255ns logic, 1.790ns route) (77.7% logic, 22.3% route)