Mealy and Moore examples

Transcription

1 CSE 37 Spring 26 Introduction to igital esign ecture 2: uential ogic Technologies ast ecture Moore and Mealy Machines Today uential logic technologies Ving machine: Moore to synch. Mealy OPEN = creates a combinational delay after and change in Moore implementation This can be corrected by retiming, i.e., move flip-flops and logic through each other to improve delay ecognize, =, OPEN.d = ( + + N)('N + N' + N + ) Mealy or Moore? = N' + N + + 'N + N' Implementation now looks like a synchronous Mealy machine it is common for programmable devices to have FF at of logic Mealy and Moore examples clock clock

2 Mealy and Moore examples (cont d) ecognize, =, then, Mealy or Moore? clock clock Hs and uential ogic Flip-flops representation of clocks - timing of state changes asynchronous vs. synchronous FSMs structural view (FFs separate from combinational logic) behavioral view (synthesis of sequencers not in this course) ata-paths = data computation (e.g., Us, comparators) + registers use of arithmetic/logical operators control of storage elements Example: reduce--string-by- emove one from every string of s on the input Moore zero [] one [] twos [] / Mealy zero [] one [] / / / Verilog FSM - educe s example Moore machine module reduce (clk, reset, in, ); input clk, reset, in; put ; parameter zero = 2 b; parameter one = 2 b; parameter twos = 2 b; reg ; reg [2:] state; reg [2:] next_state; // state variables clk) if (reset) state = zero; else state = next_state; state assignment (easy to change, if in one place) zero [] one [] twos []

3 Moore Verilog FSM (cont d) or state) case (state) zero: // last input was a zero if (in) next_state = one; else next_state = zero; one: // we've seen one if (in) next_state = twos; else next_state = zero; twos: // we've seen at least 2 ones if (in) next_state = twos; else next_state = zero; case crucial to include all signals that are input to state determination case (state) zero: = ; one: = ; twos: = ; case module note that put deps only on state Mealy Verilog FSM module reduce (clk, reset, in, ); input clk, reset, in; put ; reg ; reg state; // state variables reg next_state; clk) if (reset) state = zero; else state = next_state; or state) case (state) zero: // last input was a zero = ; if (in) next_state = one; else next_state = zero; one: // we've seen one if (in) next_state = one; = ; else next_state = zero; = ; case module / zero [] one [] / / / Synchronous Mealy Machine module reduce (clk, reset, in, ); input clk, reset, in; put ; reg ; reg state; // state variables clk) if (reset) state = zero; else case (state) zero: // last input was a zero = ; if (in) state = one; else state = zero; one: // we've seen one if (in) state = one; = ; else state = zero; = ; case module Finite state machines summary Models for representing sequential circuits abstraction of sequential elements finite state machines and their state diagrams inputs/puts Mealy, Moore, and synchronous Mealy machines Finite state machine design procedure deriving state diagram deriving state transition table determining next state and put functions implementing combinational logic Hardware description languages

4 uential logic implementation Implementation random logic gates and FFs programmable logic devices (P with FFs) esign procedure state diagrams state transition table state assignment next state functions Median filter FSM emove single s between two s (put = NS3) I PS PS2 PS3 NS NS2 NS3 X X X X X X Median filter FSM (cont d) ealized using the standard procedure and individual FFs and gates I PS PS2 PS3 NS NS2 NS3 X X X X X X NS = (I) NS2 = ( PS + PS2 I ) NS3 = PS2 O = PS3 Median filter FSM (cont d) ut it looks like a shift register if you look at it right

5 Median filter FSM (cont d) n alternate implementation with S/ FFs In CK S S S Out = S = PS2 In NS = In NS2 = PS NS3 = PS2 O = PS3 Implementation using Ps Programmable logic building block for sequential logic macro-cell: FF + logic -FF two-level logic capability like P (e.g., 8 product terms) The set input (S) does the median filter function by making the next state whenever the input is and PS2 is ( input to state xx) OPEN Ving machine example (Moore P mapping) = reset'('n + N' + N + ) = reset'( + + N) = CK Ving machine (synch. Mealy P mapping) OPEN = reset'(n' + N + + 'N + N') CK N N Open OPEN Open Com

6 22V P Combinational logic elements (SoP) uential logic elements (-FFs) Up to puts Up to FFs Up to 22 inputs 22V P Macro Cell uential logic element + put/input selection ight Game FSM Tug of War game 7 Es, 2 push buttons (, ) ight Game FSM Verilog module ight_game (ES, P, P, CK, ESET); input P ; input P ; input CK ; input ESET; put [6:] ES ; combinational logic wire, ; assign = ~left && P; assign = ~right && P; assign ES = position; E (6) E (5) E (4) ESET E (3) E (2) E () E () reg [6:] position; reg left; reg right; sequential logic CK) left <= P; right <= P; if (ESET) position <= 7'b; else if ((position == 7'b) (position == 7'b)) ; else if () position <= position << ; else if () position <= position >> ; module

7 Example: traffic light controller busy highway is intersected by a little used farmroad etectors C sense the presence of cars waiting on the farmroad with no car on farmroad, light remain green in highway direction if vehicle on farmroad, highway lights go from Green to Yellow to ed, allowing the farmroad lights to become green these stay green only as long as a farmroad car is detected but never longer than a set interval when these are met, farm lights transition from Green to Yellow to ed, allowing highway to return to green even if farmroad vehicles are waiting, highway gets at least a set interval as green ssume you have an interval timer that generates: a short time pulse (TS) and a long time pulse (T), in response to a set (ST) signal. TS is to be used for timing yellow lights and T for green lights Example: traffic light controller (cont ) Highway/farm road intersection farm road car sensors highway Example: traffic light controller (cont ) Tabulation of inputs and puts inputs description puts description reset place FSM in initial state HG, HY, H assert green/yellow/red highway lights C detect vehicle on the farm road FG, FY, F assert green/yellow/red highway lights TS short time interval expired ST start timing a short or long interval T long time interval expired Tabulation of unique states some light configurations imply others Example: traffic light controller (cont ) State diagram TS' T C / ST HY (T C)' HG TS / ST FY TS' state HG HY FG FY description highway green (farm road red) highway yellow (farm road red) farm road green (highway red) farm road yellow (highway red) TS / ST FG T+C' / ST (T+C')'

8 Example: traffic light controller (cont ) Generate state table with symbolic states Consider state assignments put encoding similar problem to state assignment (Green =, Yellow =, ed = ) Inputs Present State Next State Outputs C T TS ST H F HG HG Green ed HG HG Green ed HG HY Green ed HY HY Yellow ed HY FG Yellow ed FG FG ed Green FG FY ed Green FG FY ed Green FY FY ed Yellow FY HG ed Yellow S: HG = HY = FG = FY = S2: HG = HY = FG = FY = S3: HG = HY = FG = FY = (one-hot) S S2 S3 ogic for different state assignments NS = C T' PS PS + TS PS' PS + TS PS PS' + C' PS PS + T PS PS NS = C T PS' PS' + C T' PS PS + PS' PS ST = C T PS' PS' + TS PS' PS + TS PS PS' + C' PS PS + T PS PS H = PS H = PS' PS F = PS' F = PS PS NS = C T PS' + TS' PS + C' PS' PS NS = TS PS PS' + PS' PS + TS' PS PS ST = C T PS' + C' PS' PS + TS PS H = PS F = PS' NS3 = C' PS2 + T PS2 + TS' PS3 NS = C T PS + TS' PS H = PS PS' F = PS PS ST = C T PS + TS PS + C' PS2 + T PS2 + TS PS3 H = PS3 + PS2 H = PS F = PS + PS F = PS3 NS2 = TS PS + C T' PS2 NS = C' PS + T' PS + TS PS3