COMARCH. COMPUTER ARCHITECTURE TERM 3 SY COMPUTER ENGINEERING DE LA SALLE UNIVERSITY Quiz 1

Transcription

1 COMARCH. COMPUTER ARCHITECTURE TERM 3 SY COMPUTER ENGINEERING DE LA SALLE UNIVERSITY Quiz 1 1. Draw the logic symbol of the component whose operations are specified by the following microoperations: ctr 0; ctr ctr+1; ctr ctr-1; ctr ibus. 2. Draw the logic symbol of an 8-bit register described by the following microoperation: ldr : R ibus. 3. Draw the logic diagram of 4 registers described in (2) connected to a common bus using octal 4 to 1 multiplexers and 2x4 decoders. Name the registers as R0, R1, R2, and R3. 4. Create a table to summarize the transfer microoperations that can be carried out between these four registers. 5. If (3) is implemented using octal bus buffers, draw the logic diagram. 6. Below is the table of the Simple As Possible (SAP) computer. Draw the logic diagram of its datapath and control unit. 0 LDA portion of the instruction 1 ADD Add with the accumulator the contents of the memory specified by the portion of the instruction 2 SUB Subtract from the accumulator the contents of the memory specified by the portion of the instruction 3 OUT Output the contents of the accumulator to the output register 7. Tabulate the micro operations that will describe the operation of SAP starting with reset, fetch, LDA, ADD, SUB and OUT. 8. If the instruction set of SAP is modified as shown in the table below, draw the resulting logic diagram of the datapath and the control unit. 0 LDA portion of the instruction 1 STA Store the contents of the ACC to the memory specified by the portion of the instruction 2 ADD Add with the accumulator the contents of the memory specified by the portion of the instruction 3 SUB Subtract from the accumulator the contents of the memory specified by the portion of the instruction 8 JMP Jump program execution to specified E OUT Output the contents of the accumulator to the output register 9. Tabulate the microoperations that will describe the operation of (8). 10. Write a program in assembly for both SAP and the modified SAP that will output a counting up sequence.

2 solution (5) Draw the logic symbol of the component whose operations are specified by the following microoperations: ctr 0; ctr ctr+1; ctr ctr-1; ctr ibus (5) Draw the logic symbol of an 8-bit register described by the following microoperations: ldr : R ibus. (10) Draw the logic diagram of 4 registers described in (2) connected to a common bus using octal 4 to 1 multiplexers and 2x4 decoders. Name the registers as R0, R1, R2, and R3.

3 (10) Create a table to summarize the transfer microoperations that can be carried out between these four registers. Transfer operation Transfer operation Transfer operation Transfer operation R0 <= R0 R1 <= R0 R2 <= R0 R3 <= R0 R0 <= R1 R1 <= R1 R2 <= R1 R3 <= R1 R0 <= R2 R1 <= R2 R2 <= R2 R3 <= R2 R0 <= R3 R1 <= R3 R2 <= R3 R3 <= R3 (10) If (3) is implemented using octal bus buffers, draw the logic diagram.

4 (20) Below is the table of the Simple As Possible (SAP) computer. Draw the logic diagram of its datapath and control unit. 0 LDA portion of the instruction 1 ADD Add with the accumulator the contents of the memory specified by the portion of the instruction 2 SUB Subtract from the accumulator the contents of the memory specified by the portion of the instruction 3 OUT Output the contents of the accumulator to the output register

5 (20) Tabulate the micro operations that will describe the operation of SAP starting with reset, fetch, LDA, ADD, SUB and OUT. Fetch Cycle MAR <= PC 0 LDA 1 ADD 2 SUB IR <= M[MAR], PC <= PC + 1 portion of the instruction ACC <= M[MAR], goto FETCH Add with the accumulator the contents of the memory specified by the portion of the instruction B <= M[MAR] ACC <= ACC + B, goto FETCH Subtract from the accumulator the contents of the memory specified by the portion of the instruction B <= M[MAR] ACC <= ACC - B, goto FETCH 3 OUT Output the contents of the accumulator to the output register OUTR <= ACC, goto FETCH (20) If the instruction set of SAP is modified as shown in the table below, draw the resulting logic diagram of the datapath and the control unit. 0 LDA portion of the instruction 1 STA Store the contents of the ACC to the memory specified by the portion of the instruction 2 ADD Add with the accumulator the contents of the memory specified by the portion of the instruction 3 SUB Subtract from the accumulator the contents of the memory specified by the portion of the instruction 8 JMP Jump program execution to specified E OUT Output the contents of the accumulator to the output register

6 Datapath

7 Control unit

8 (20) Tabulate the microoperations that will describe the operation of (8). Fetch Cycle MAR <= PC IR <= M[MAR], PC <= PC LDA 1 STA 2 ADD portion of the instruction ACC <= M[MAR], goto FETCH portion of the instruction M[MAR] <= ACC, goto FETCH Add with the accumulator the contents of the memory specified by the portion of the instruction B <= M[MAR] ACC <= ACC + B, goto FETCH 3 SUB Subtract from the accumulator the contents of the memory specified by the portion of the instruction B <= M[MAR] ACC <= ACC - B, goto FETCH 8 JMP portion of the instruction PC <= IR(3:0), goto FETCH E OUT Output the contents of the accumulator to the output register OUTR <= ACC, goto FETCH

9 (10) Write a program in assembly for both SAP and the modified SAP that will output a counting up sequence. SAP Program. Counting up sequence Address Contents Mnemonic code Address Contents Mnemonic code (HEX) (HEX) (HEX) (HEX) 0 0F LDA $ F 8 1E ADD $ E 1 30 OUT 9 30 OUT 2 1E ADD $ E A 1E ADD $ E 3 30 OUT B 30 OUT 4 1E ADD $ E C 1E ADD $ E 5 30 OUT D 30 OUT 6 1E ADD $ E E OUT F 00 MSAP Program. Counting up sequence Address (HEX) Contents (HEX) Mnemonic code Address (HEX) Contents (HEX) 0 0F LDA $ F 8 1E 1 30 OUT E ADD $ E A 1E 3 80 JMP $ 1 B C 1E 5 00 D E F 00 Mnemonic code