Cell-Based Design Flow. 林丞蔚
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1 Cell-Based Design Flow 林丞蔚 1
2 Outline Overview Design Flow 1 RTL Development Synthesis Gate Level Simulation Design Flow 2 Placement and Routing Example Design IC Contest 2006 Project Assignment 2
3 Outline Overview Design Flow 1 RTL Development Synthesis Gate Level Simulation Design Flow 2 Placement and Routing Example Design IC Contest 2006 Project Assignment 3
4 Cell-based Design Flow Overview A design flow is a set of procedures that allows designers to progress from a specification for a chip to the final chip implementation in an error-free way. 4
5 Source: CM: 5086 VLSI Design Lab Cell-based Design Flow Specification Development System Models System Architecture RTL code development Functional Verification RTL Synthesis Timing Verification Synthesis Physical Synthesis/Place and Route Physical Verification Physical Design Prototype Build and Test 5 System Integration and Software Test
6 Source: CM: 5086 VLSI Design Lab Cell-based Design Tool System Architecture/SW simulation C/C++, Matlab, System C, System Verilog RTL NC-Verilog, NC-VHDL, nlint, Debussy Synthesis RTL Compiler, Design Compiler, PrimePower Physical Design SoC Encounter, Astro, Calibre, Nanosim 6
7 Outline Overview Design Flow 1 RTL Development Synthesis Gate Level Simulation Design Flow 2 Placement and Routing Example Design IC Contest 2006 Project Assignment 7
8 RTL Development Development / simulation NC-verilog Unix:> ncverilog <your_testbench_file> +access+r 8
9 RTL Development Check the simulation output Dump waveform from testbench when simulation $fsdbdumpfile( triangle.fsdb ); nwave Unix:> nwave 9
10 RTL Development Verilog dump related command VCD file format(value Change Dump) $dumpfile() FSDB file format(from Novas) $fsdbdumpfile( output.fsdb ); Fsdb file is the input of Verdi Verdi(debussy): a powerful debugging tool provided by NOVAS Unix:> Verdi 10
11 nlint from NOVAS RTL Development Unix:> nlint gui & Run->Compile Run->Lint /cad/eda/spring/verdi/ v1/nlint/doc/pdf/rules.pdf 11
12 Outline Overview Design Flow 1 RTL Development Synthesis Gate Level Simulation Design Flow 2 Placement and Routing Example Design IC Contest 2006 Project Assignment 12
13 Source: CIC Jan.08 Design Compiler Synthesis Synthesis=translation+ optimization+ mapping Residue = 16 h0000; If(high_bits==2 b10) residue = state_table[i]; Else state_table[i] = 16 h0000; HDL Source(RTL) Translate(HDL Compiler) Optimize + Map (Design Compiler) NO Timing Info => Generic Boolean Timing Info => Target Technology 13
14 Synthesis Design Compiler It synthesizes your designs (Verilog) into optimized technology-dependent, gate-level designs. Use Design Compiler GUI Startup x-win ( or any other X terminal application) $design_vision 14
15 Synthesis Environment Setup /home directory/.cshrc : set path and license of synthesis tool /your working directory/.synopsys_dc.setup : setup technology file, designware library file etc Use DC-TCL script file(.tcl) Set design constraints Unix:> design_vision-xg -f syn.tcl 15
16 Synthesis Detail of synopsys_dc.setup ASIC Technology file For schematic For Designware 16
17 Synthesis Modify the syn.tcl Your Design Name sdc file:synopsys design constrains sdf file:standard delay format Synopsys Design Constain Your Design Name 17
18 Synthesis SDC file : synopsys design constrain Setup input/output delay and loading SDF file : standard delay format Setup the rising/holding/falling time for each cell of your design 18
19 Synthesis Put the RTL file,.synopsys_dc.setup and syn.tcl to your working directory, or assert the setup commands by hand, while synthesis. Under your working directory, make new directories, Report and Netlist, for saving synthesis reports. 19
20 Synthesis Output result Command return result(error) command command Command return result(done) 20
21 Synthesis The synthesis information is in your Report directory Timing.txt 21
22 Outline Overview Design Flow 1 RTL Development Synthesis Gate Level Simulation Design Flow 2 Placement and Routing Example Design IC Contest 2006 Project Assignment 22
23 Gate Level Simulation Verify your synthesis result Modify your testbench sdf_annotate( triangle.sdf, top) `include CHIP.v Unix:> ncverilog <YourTestBench.v> -v./tsmc13_neg.v +access+r 23
24 Outline Overview Design Flow 1 RTL Development Synthesis Gate Level Simulation Design Flow 2 Placement and Routing Example Design IC Contest 2006 Project Assignment 24
25 SOC Encounter Placing & Routing Flow Netlist(verilog) Timing Constrain(sdc) IO Constrain IO, P/G Placement Specify floorplan Timing Analysis Pre-CTS Optimize Power Planning Power Analysis Clock Tree Synthesis Timing Analysis Post-CTS Optimize Power Route SI Driven Route Timing/SI Analysis Post-Route Optimize GDS file Netlist, DEF 4 Main Step(must be in order): IO Placement, Cell Placement, CTS, SI Driven Routing 25 Source: CIC Jan. 2008, SoC Encounter
26 Basic View $encounter Floorplan view Ameoba view Physical view 26
27 Project Setup Design -> Design Import netlist Cell Library Physical Library IO Map file 27
28 IO, Power/Ground Placement Floorplan -> Connect Global Nets 28
29 Floorplan Floorplan -> Specify Floorplan 29
30 Cell Placement Place -> Standard Cell And Blocks 30
31 Power Planning Power -> Power Planning -> Add Rings 31
32 Clock Tree Synthesis Clock -> Design Clock 32
33 Rounting Route -> Special Route 33
34 Rounting Route -> NanoRoute 34
35 Result Analysis Final step DRC LVS verification Verify -> Verify Connectivity Timing analysis Timing -> Analysis Timing Post layout simulation 35
36 Outline Overview Design Flow 1 RTL Development Synthesis Gate Level Simulation Design Flow 2 Placement and Routing Example Design IC Contest 2006 Project Assignment 36
37 Example Design Triangle Rendering Engine Get 3 consecutive pairs of coordinate for a triangle from system testbench Input will meet the following relation.(this means that one side of the triangle will be vertical!) Output (xo, yo) coordinate Output po is active to indicate there is a valid coordinate output (xo, yo) 37
38 Example Design I/O Interface : 38
39 Example Design Basic Algorithm Given 2 point (x1, y1), (x2, y2). The line equation of 2 point form are : Any points in the right side of this line will satisfy the equation: Any points in the left side of this line will satisfy the equation: 39
40 Example Design Design Implementation Use 2 counters to count 0~7(3 bits), when (count_x, count_y) located in the triangle, active po as high. When count_x is betwee X 1 and X_bound, active po as high. 40
41 Design Implement Finite State Machine Extra state for 3 pairs of input case(state) 0: begin if(nt) state = 1; end 1: begin state = 2; end 2: state = 3; 3: begin if(&{cnt_x, cnt_y})begin state = 0; end end 41
42 Design Implement Input : Register shift module 3 register for x and y coord. Input data state : shift data to next register Computation state : keep data. Assign mux = (compu_state)? output : input; always@(posedge clk)begin if(rst) output <= 3 b0; else output <= mux; end Output pass to the input port of next register 42
43 X_bound calculation Design Implement Case 1: x_bound += (y1-y2/x1-x2) Case 2: x_bound -= (y0-y1/x1-x0) Case 3: x_bound -= (y1-y2/x1-x2) Case 4: x_bound += (y0-y1/x0-x1) Case 4 v1 Case 3 v0 v2 Case 2 v1 Case 1 If(cnt_y < y1 && cnt_y >= y2) if(x1 > x2) x_bound <= x_bound + dx1; else x_bound <= x_bound dx1; Else if(cnt_y >= y1) if(x1 > x2) x_bound <= x_bound dx2; else x_bound <= x_bound + dx2; 43
44 Design Implement po specification Case 4 v0 Case 2 v1 v1 Case 3 v2 Case 1 Case 1, 2 assign po = (state = computation_state) && (cnt_y >= y2 && cnt_y <= y0 && x1 > x2 && cnt_x >= x2 && cnt_x <= x_bound) && (cnt_y >= y2 && cnt_y <= y0 && x1 <= x2 && cnt_x >= x_bound && cnt_x <= x2) Case 3, 4 44
45 Design Implement System architecture 45
46 Outline Overview Design Flow 1 RTL Development Synthesis Gate Level Simulation Design Flow 2 Placement and Routing Example Design IC Contest 2006 Project Assignment 46
47 Mini Project Goal : Compile / Simulate / Synthesis an Ethernet MAC project at opencores.org Tool(platform) used: Compile : ModelSim (win) Simulate : ModelSim(win) Synthesis : Design Compiler(Unix) Gate level simulation : ModelSim(win) 47
48 Mini Project Server IP ~ port: 22 (SSH) ~ port: 22 (SSH) ~ port: 22 (SSH) ID/password will be announced 48
49 Compile / Simulate - 1 Just fallow the README instruction Open the project file Execute the scripts file 49
50 Compile / Simulate - 2 Compiling and simulation message show in the command line window, and the waveform window pop up. 50
51 Synthesis Uncompress prepared file in Unix server Modify syn.tcl set DESIGN eth_rxstatem create_clock period 40 [get_ports MRxClk] Unix:> design_vision-xg f syn.tcl Check out the Report and Netlist file 51
52 Gate-Level Simulation - 1 Get file at Netlist directory from Unix server eth_rxstatem_syn.v, eth_rxstatem_syn.sdf, tsmc13_neg.v Modify tb_eth.do in the project directory Comment line 82, type in line 83 (use gate-level v file instead of original one) 52
53 Gate-Level Simulation - 2 Modify eth_rxethmac.v Add these lines as below and copy the eth_rxstatem_syn.sdf file to where do.do is located (add the timing information for the new gate level v file) 53
54 Gate-Level Simulation - 3 Modify eth_wave.do file Add these line as below (add the Rx signal to the waveform window) Execute the simulation scripts again Modelsim > do do.do 54
55 Mini Project TODO list Take screen shot of each important step or result with text explanation Check out some signals in RX module in certain period of time, then find out the corresponding verilog code What is the main difference between two simulations (logic level v.s. gate level) in their waveform? Demo and turn-in a short report at 1:00-4:00PM 3/20(Fri.) at 715 電資大樓 55
56 Term Project Goal : Write a network hardware simulation module in verilog Quick scan of the top testbench file : tb_ethernet.v Select some properties of this project, ex : full duplex/half duplex Develop a simple test case to simulate the properties you choose, and explain the result Synthesis the corresponding module and take this gate level verilog file into term project testbench (just copy and modify from tb_ethernet.v) 56
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