Lecture 7: Structural RTL Design. Housekeeping

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1 Lecture 7: Structural RTL Design James C. Hoe Department of ECE Carnegie Mellon University F17 L07 S1, James C. Hoe, CMU/ECE/CALCM, 2017 Housekeeping Your goal today: think about what you think about when you design RTL Notices Handout #3: lab 1, due noon, 9/22 Readings HDL Compiler for Verilog Reference Manual and others at /afs/ece/support/synopsys/ /share/image/ usr/local/synopsys/ /doc/online/dc/print Vivado Design Suite User Guide: Synthesis (UG901) F17 L07 S2, James C. Hoe, CMU/ECE/CALCM, 2017

2 Math DFT n m n m n m DFT I D I DFT L n m n n m n Dataflow x x x x x x x x What do you see in your mind when you design hardware? Program/Algorithm for (m = 0; m < mmax; m += 1) { for (i = m; i < n; i += istep) { j =i + mmax; tempr = wr*data[2*j] - wi*data[2*j+1]; tempi = wr*data[2*j+1] + wi*data[2*j]; data[2*j] = data[2*i] - tempr; data[2*j+1] = data[2*i+1] - tempi; data[2*i] += tempr; data[2*i+1] += tempi; } Hardware Description Language (posedge Clk) begin if (a >= b) begin a <= a - b; b <= b; else begin a <= b; b <= a; Schematic Capture Mod Flip+ Mod ce Mod,a a Flip,b Flip,a - Mod,a Flip Flip,b b ce Flip,a < =0 Flip Mod Flip F17 L07 S3, James C. Hoe, CMU/ECE/CALCM, 2017 What is Structural Design? F17 L07 S4, James C. Hoe, CMU/ECE/CALCM, 2017

3 Hardware Design is Structural a block can implement arbitrary functional and timing relationships between inputs and outputs inputs: wires driven by other CLK outputs: wires driven by block F17 L07 S5, James C. Hoe, CMU/ECE/CALCM, 2017 Hardware Design is Hierarchical inputs: wires driven by other CLK outputs: wires driven by block F17 L07 S6, James C. Hoe, CMU/ECE/CALCM, 2017

4 It all boils down to this I Comb (nextstate) NS S CS Comb (output) O a collection of synchronous state elements (updates on clock edge) a collection of combinational logic that computes nextstate (NS) from current state (CS) and input (I) a collection of combinational logic that computes output (O) from current state (CS) and input (I) F17 L07 S7, James C. Hoe, CMU/ECE/CALCM, 2017 global clock Synchronous Timing clock period chosen to be greater than critical path sync comb comb sync sync comb comb sync registers latch new CS sync comb combinational propagation delay comb sync final value of NS ready F17 L07 S8, James C. Hoe, CMU/ECE/CALCM, 2017

5 FSM D datapath = organized combinational logic and registers to carry out computation (puppet) FSM = stylized combinational logic and registers for control and sequencing (puppeteer) inputs outputs FSM datapath clock F17 L07 S9, James C. Hoe, CMU/ECE/CALCM, F17 L07 S10, James C. Hoe, CMU/ECE/CALCM, 2017 Cooperating FSM Ds Partitioning large design into manageable chunks natural decomposition by functionalities inherent concurrency and replications Correct decomposition leads to simpler parts but coordination of the parts becomes the challenge synchronization: having two FSM Ds in the right state at the right time communication: exchange information between FSM D (requires synchronization)

6 Crux of the HW Design Difficulty We design FSM Ds separately liable to forget what one machine is doing when focusing on another No language support for coordination no explicit way to say how state transitions of two FSMs must be related Coordination hardcoded into design implicitly leave little room for automatic optimization hard to localize design changes (unless decoupled using request/reply style handshakes) F17 L07 S11, James C. Hoe, CMU/ECE/CALCM, F17 L07 S12, James C. Hoe, CMU/ECE/CALCM, 2017 RTL vs Schematics Same design abstraction synchronous state, combinational next state logic hierarchy of modules with ports So why HDL more productive textual description is easier, more compact contemporary development in logic optimization (especially combinational) procedural description of combinational logic adopted PL know hows: types, structs, operators, parameters,... behavioral testbench Better but not fundamentally different

7 Verilog an RTL language? F17 L07 S13, James C. Hoe, CMU/ECE/CALCM, 2017 Verilog in essence Verilog is not RTL a multithreaded programming language + modeled time + scheduling queue + modules and ports Verilog describes how a module behaves, not its construction no notion of combinational vs sequential logic no notion of a register or even of a clock perfectly happy describing non hardware F17 L07 S14, James C. Hoe, CMU/ECE/CALCM, 2017

8 Verilog Synthesis is Interpretation // Ex 1 always@(a or b) if (a) c = b; // Ex 2 always@(a) if (a) c = b; else c = 0; // Ex 3 always@(a or b) if (a) c = b; else c = 0; // Ex 4 always@(a or b) begin c = 0; if (a) c = b; All have well defined behaviors According to Verilog semantics, c deps combinationally on a and b in Ex 3, 4 and 5 Verilog doesn t say they are combinational or they are synthesizable // Ex 5 always@(a) if (a) c = b; else c = 0; always@(b) if (a) c = b; else c = 0; F17 L07 S15, James C. Hoe, CMU/ECE/CALCM, 2017 Synthesizable Verilog Verilog becomes an RTL language and becomes synthesizable only when used in a stylized way dictated by the synthesis tool So called synthesizable subset is really a different language Difficult even to define what is correct synthesis with respect to simulation behavior always@(a) p = a & (!a); =? a p F17 L07 S16, James C. Hoe, CMU/ECE/CALCM, 2017 Is p combinational?

9 RTL by Discipline module contrived(input i, clk, output o); reg cs; // sequential reg ns; // combinational assign o = cs; i 0 1 ns clk cs o ( i or cs) if (cs) ns = ~i; else ns = i; ( posedge clk ) begin cs <= ns; combinational synch. sequential module F17 L07 S17, James C. Hoe, CMU/ECE/CALCM, 2017 Crib sheet: Combinational always fmust be assigned in all on all RHS vars possible control paths; use begin blocking assigns fcan dep on f only if f has been assigned f =... f =... repeated assigns to f okay; f =... the last one holds f =... fcannot be assigned in any f =... other process multiple LHS vars okay; all rules above apply Use continuous assigns for simple expressions F17 L07 S18, James C. Hoe, CMU/ECE/CALCM, 2017

10 Crib sheet: Synchronous always use non blocking assigns; effect of assign not visible until after all triggered processes are done fcan dep on f; RHSf stays at starting value repeated assigns to f okay; the last one holds fcannot be assigned in any other process multiple LHS vars okay; all rules above apply F17 L07 S19, James C. Hoe, CMU/ECE/CALCM, 2017 clk) begin f <=... f<=... f<=... f<=... f<=... Procedural Block to Combinational y { } x = b; if (y) x = x + a; b x 1 a { x 1 = b; if (y) x 2 = x 1 + a; else x 2 = x 1 + } x = x 2 static elaboration to single assignment F17 L07 S20, James C. Hoe, CMU/ECE/CALCM, 2017 x 2 x Why not just: assign x=y?(b+a):b;

11 reg [5:0] Z; wire [31:0] A; integer i; begin Why Procedural Block Wins Z=0; for(i=0;i<=31;i=i+1) begin if (A[i]) begin Z=Z+1; A Z F17 L07 S21, James C. Hoe, CMU/ECE/CALCM, 2017 Try saying this in continuous assign Synthesizable Loops Loop must be statically unrolled, i.e., loop index must be integer type loop index initial value must statically resolve to a constant valid loop index operations are +, the valid loop condition test must test against a static limit using relational operators (<, <=, ==, etc) Precise limitations vary by tools and versions Through static elaboration, even bounded recursion should be okay F17 L07 S22, James C. Hoe, CMU/ECE/CALCM, 2017

12 Don t try this at home module fib( output [7:0] z, input [7:0] n ); function [7:0] recur; input [7:0] n; begin if (n==0) recur=0; else if (n==1) recur=1; else recur=recur(n-1)+recur(n); function // recur assign z = recur(n); module F17 L07 S23, James C. Hoe, CMU/ECE/CALCM, 2017 This is correct Verilog; does it synthesize? Modern Synthesis Plays Tricks Standard compiler passes constant propagation common subexpression elimination deadcode elimination strength reduction Bit wise logic also Boolean optimized Most of the time, good enough to write understandable expressions with clear intent F17 L07 S24, James C. Hoe, CMU/ECE/CALCM, 2017

13 Reserve Black Arts for Timing Closure wire a, b, c, d; wire [3:0] sel; reg z; begin z = 0; if (sel[0]) z = a; if (sel[1]) z = b; if (sel[2]) z = c; if (sel[3]) z = d; wire a, b, c, d; wire [3:0] sel; reg z; always@* begin z = 0; if (sel[3]) z = d; else if (sel[2]) z = c; else if (sel[1]) z = b; else if(sel[0]) z = a; F17 L07 S25, James C. Hoe, CMU/ECE/CALCM, 2017 Tool specific Local transformations a a F17 L07 S26, James C. Hoe, CMU/ECE/CALCM, 2017 Retiming Preserves I/O relationships Tools use retiming b b balance critical paths absorb FFs into hard macros a a b c b c I 0 I 2 I n 1 a b a b c c O 0 O 2 O m 1 always@(posedge clk) begin a1<=a; b1<=b; a2<=a1; b2<=b1; c<=a2*b2;

14 Some Best Practices #1 Read the style guides Develop a mental model of synthesis Know what optimizations tools do and don t do Know the special inference rules: FF, RAM, FSM Know pragmas to control the tool Read the synthesis reports (inference and warnings) Have a good naming convention Keep combinational and sequential distinct Use modules and hierarchies Embed assertions F17 L07 S27, James C. Hoe, CMU/ECE/CALCM, 2017 FPGA Inference Extra Gotcha s FPGA Macros (especially RAM and DSP) coarse functions and structures some powerful but arbitrarily specific features penalty is too huge to not get it right Very specific guideline for inferring hard macros hard macros only does what it does tools cannot recognize all functional equivalent descriptions F17 L07 S28, James C. Hoe, CMU/ECE/CALCM, 2017 Always check inference report to see if you got what you expected

15 Use asynch set or reset Just on Flip Flops not all FFs have async reset; prevents DSP retiming Use both set and reset no FF has this; emulated externally with LUTs Use set and reset operationally set/reset cannot use special global lines Active low set/reset and enables need LUTs to turn active high F17 L07 S29, James C. Hoe, CMU/ECE/CALCM, 2017 How could you know this? BRAM cannot be used if combinational read Shift registers can be made out of LUTs BUT! no set/reset and can t read middle bits Registers will retime into multiplier and DSP (if no asynch reset) Use initial for power on reset Timing analysis doesn t do latches Many, many more like this... Read the inference report and warnings RTMF! F17 L07 S30, James C. Hoe, CMU/ECE/CALCM, 2017

16 Why is Structural Design Hard? F17 L07 S31, James C. Hoe, CMU/ECE/CALCM, 2017 Reason #1: Low Level of Abstraction When writing a high level program, specify functionality using abstract constructs: loops, double, +,... can ignore non functional details: timing, data representation, data placement,.... even assembly programming is in a virtualized realm When designing RTL direct control of structure and operation bit level and cycle level building blocks Say anything you want and get what you want; but takes a whole lot more work F17 L07 S32, James C. Hoe, CMU/ECE/CALCM, 2017

17 Reason #2: Unrestricted Design Freedom Total freedom in how to realize a functionality for(i=0; i<10; i=i+1) sum+=i; is sum an integer or float, exactly how many bits? how to +? ripple, c select, c look ahead... do + one at a time or all at once? where to store i and sum? may be not at all Can choose anything in between as cheap as possible (area or energy?) and as fast as possible (latency or throughput?) Find the one right design in a haystack of bad ones F17 L07 S33, James C. Hoe, CMU/ECE/CALCM, 2017 Reason #3: Massive Concurrency Extremely high degree of concurrency Extremely fine granularity of concurrency Explicit everything (synchronization, communication,...); poor language abstraction Nothing is disallowed (irregular parallelism, mixing parallelism,...) Everything that makes parallel programming hard is much worse in hardware design F17 L07 S34, James C. Hoe, CMU/ECE/CALCM, 2017

18 Reason #4: Because it is hard Only design hardware as the last resort if not performance critical, just write software if not energy (or cost or weight) constrained, run on faster processors, bigger computers if embarrassingly SIMD parallel, run on GPUs Unfortunately, what makes hardware design hard (#1~#3) is what makes hardware the ultimate weapon when all else fails How to make hardware design easier without making the results less efficient? F17 L07 S35, James C. Hoe, CMU/ECE/CALCM, 2017 Parting Thoughts Know your tools and practice your craft Structural RTL design operates explicitly at the bit and cycle level high workload requires large designs to be broken hierarchically into manageable modules coordinating concurrent operations of distributed modules introduces its own high complexity Need better hardware design methodologies (without taking away hardware s advantages) F17 L07 S36, James C. Hoe, CMU/ECE/CALCM, 2017

EECS150 - Digital Design Lecture 5 - Verilog Logic Synthesis

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