HDLs and SystemVerilog. Digital Computer Design

Transcription

1 HDLs and SystemVerilog Digital Computer Design

2 Logic Arrays Gates can be organized into regular arrays. If the connections are made programmable, these logic arrays can be configured to perform any function without the user having to connect wires in specific ways. Software tools allow users to map logic designs onto these arrays. Two types of logic arrays: programmable logic arrays (PLAs) field programmable gate arrays (FPGAs) 2

3 PLAs Programmable logic arrays (PLAs) is older technology perform only combinational logic functions. FPGAs can perform both combinational and sequential logic. Implement two-level combinational logic in sum-ofproducts (SOP) form. PLAs are built from an AND array followed by an OR array. Inputs M AND ARRAY Implicants N OR ARRAY P Outputs 3

4 PLAs A B C OR ARRAY X = ABC + ABC Y = AB ABC ABC AB AND ARRAY X Y A B C OR ARRAY ABC ABC AB AND ARRAY X Y

5 FPGA: Field Programmable Gate Array They can implement both combinational and sequential logic. They can also implement multilevel logic functions, whereas PLAs can only implement two-level logic. Modern FPGAs integrate other useful features such as built-in multipliers, high-speed I/Os, data converters including analog-to-digital converters, large RAM arrays, and processors. 5

6 FPGA: Field Programmable Gate Array Composed of: LEs (Logic elements): perform logic IOEs (Input/output elements): interface with outside world Programmable interconnection: connect LEs and IOEs Some FPGAs include other building blocks such as multipliers and RAMs

7 LE: Logic Element Composed of: LUTs (lookup tables): perform combinational logic Flip-flops: perform sequential logic Multiplexers: connect LUTs and flip-flops

8 Altera Cyclone IV LE 1 four-input LUT 1 registered output 1 combinational output

9 LE Configuration Example Show how to configure a Cyclone IV LE to perform the following functions: X = ABC + ABC Y = AB (A) (B) (C) (X) data data 2 data data 4 X X X X X X X X LUT output C A B 0 data 1 data 2 data 3 data 4 LUT X LE 1 (A) (B) (Y) data data data 3 X X X X data 4 X X X X LUT output A data 1 B 0 data 2 data 3 Y 0 data 4 LUT LE 2

10 LE configuration for one function of more than four inputs X = JKLM and the LUT on the second LE to compute Y = XPQR. 10

11 LE configuration for one function of more than four inputs The FSM has two bits of state (S 1:0 ) and one output (Y). The next state depends on the two bits of current state. 11

12 FPGA Design Flow Using a CAD tool (such as Altera s Quartus II) Enter the design using schematic entry or an HDL Simulate the design Synthesize design and map it onto FPGA Download the configuration onto the FPGA Test the design

13 Hardware description language (HDL) Specifies logic function only Computer-aided design (CAD) tool produces or synthesizes the optimized gates Think of the hardware the HDL should produce! Most commercial designs built using HDLs Two leading HDLs: SystemVerilog developed in 1984 by Gateway Design Automation IEEE standard (1364) in 1995 Extended in 2005 (IEEE STD ) VHDL 2008 Developed in 1981 by the Department of Defense IEEE standard (1076) in 1987 Updated in 2008 (IEEE STD )

14 HDL to Gates Simulation Inputs applied to circuit Outputs checked for correctness Millions of dollars saved by debugging in simulation instead of hardware Synthesis Transforms HDL code into a netlist describing the hardware (i.e., a list of gates and the wires connecting them)

15 SystemVerilog Modules A block of hardware with inputs and outputs is called a module. Two types of Modules: Behavioral: describe what a module does Structural: describe how it is built from simpler modules a b c Verilog Module y 15

16 Behavioral SystemVerilog module/: required to begin/end module example: name of the module Operators: ~: NOT &: AND : OR module example(input logic a, b, c, output logic y); assign y = ~a & ~b & ~c a & ~b & ~c a & ~b & c; 16

17 HDL Simulation module example(input logic a, b, c, output logic y); assign y = ~a & ~b & ~c a & ~b & ~c a & ~b & c; Inputs applied to circuit, Outputs checked for correctness 17

18 HDL Synthesis module example(input logic a, b, c, output logic y); assign y = ~a & ~b & ~c a & ~b & ~c a & ~b & c; b c un5_y y y a un8_y Transforms HDL code into a netlist describing the hardware (i.e., a list of gates and the wires connecting them) 18

19 SystemVerilog Syntax Case sensitive Example: reset and Reset are not the same signal. No names that start with numbers Example: 2mux is an invalid name Whitespace ignored Comments: // single line comment /* multiline comment */ 19

20 Structural Modeling - Hierarchy module and3(input logic a, b, c, output logic y); assign y = a & b & c; module inv(input logic a, output logic y); assign y = ~a; module nand3(input logic a, b, c output logic y); logic n1; // internal signal and3 andgate(a, b, c, n1); // instance of and3 inv inverter(n1, y); // instance of inv 20

21 Bitwise Operators module gates(input logic [3:0] a, b, output logic [3:0] y1, y2, y3, y4, y5); /* Five different two-input logic gates acting on 4 bit busses */ assign y1 = a & b; assign y2 = a b; assign y3 = a ^ b; // AND // OR // XOR assign y4 = ~(a & b); // NAND assign y5 = ~(a b); // NOR // single line comment /* */ multiline comment 21

22 Reduction Operators module and8(input logic [7:0] a, output logic y); assign y = &a; // &a is much easier to write than // assign y = a[7] & a[6] & a[5] & a[4] & // a[3] & a[2] & a[1] & a[0]; 22

23 Conditional Assignment module mux2(input logic [3:0] d0, d1, input logic s, output logic [3:0] y); assign y = s? d1 : d0; 23

24 Internal Variables module fulladder(input logic a, b, cin, output logic s, cout); logic p, g; // internal nodes assign p = a ^ b; assign g = a & b; assign s = p ^ cin; assign cout = g (p & cin); 24

25 Precedence Highest Lowest ~ NOT *, /, % mult, div, mod +, - add,sub <<, >> shift <<<, >>> arithmetic shift <, <=, >, >= comparison ==,!= equal, not equal &, ~& AND, NAND ^, ~^ XOR, XNOR, ~ OR, NOR?: ternary operator 25

26 Numbers Format: N'Bvalue N = number of bits, B = base N'B is optional but recommended (default is decimal) Number # Bits Base Decimal Equivalent Stored 3'b101 3 binary 'b11 unsized binary 'b11 8 binary 'b1010_ binary 'd6 3 decimal 'o42 6 octal 'hAB 8 hexadecimal Unsized decimal

27 Bit Manipulations: Example 1 assign y = {a[2:1], {3{b[0]}}, a[0], 6'b100_010}; // if y is a 12-bit signal, the above statement produces: y = a[2] a[1] b[0] b[0] b[0] a[0] // underscores (_) are used for formatting only to make // it easier to read. SystemVerilog ignores them. 27

28 Bit Manipulations: Example 2 module mux2_8(input logic [7:0] d0, d1, input logic s, output logic [7:0] y); mux2 lsbmux(d0[3:0], d1[3:0], s, y[3:0]); mux2 msbmux(d0[7:4], d1[7:4], s, y[7:4]); 28

29 Z: Floating Output module tristate(input logic [3:0] a, input logic en, output tri [3:0] y); assign y = en? a : 4'bz; 29

30 Sequential Logic SystemVerilog uses idioms to describe latches, flip-flops and FSMs Other coding styles may simulate correctly but produce incorrect hardware General Structure: list) statement; Whenever the event in sensitivity list occurs, statement is executed 30

31 D Flip-Flop module flop(input logic clk, input logic [3:0] d, output logic [3:0] q); clk) q <= d; // pronounced q gets d always_ff behaves like always but is used exclusively to imply flip-flops and allows tools to produce a warning if anything else is implied. 31

32 Resettable D Flip-Flop module flopr(input logic clk, input logic reset, input logic [3:0] d, output logic [3:0] q); // synchronous reset clk) if (reset) q <= 4'b0; else q <= d; 32

33 Resettable D Flip-Flop module flopr(input logic clk, input logic reset, input logic [3:0] d, output logic [3:0] q); // asynchronous reset clk, posedge reset) if (reset) q <= 4'b0; else q <= d; 33

34 D Flip-Flop with Enable module flopren(input logic clk, input logic reset, input logic en, input logic [3:0] d, output logic [3:0] q); // enable and asynchronous reset clk, posedge reset) if (reset) q <= 4'b0; else if (en) q <= d; 34

35 Other Behavioral Statements Statements that must be inside always statements: if / else case, casez 35

36 Combinational Logic using always // combinational logic using an always statement module gates(input logic [3:0] a, b, output logic [3:0] y1, y2, y3, y4, y5); always_comb // need begin/end because there is begin // more than one statement in always y1 = a & b; // AND y2 = a b; // OR y3 = a ^ b; // XOR y4 = ~(a & b); // NAND y5 = ~(a b); // NOR end always_comb reevaluates the statements inside the always statement any time any of the signals on the right hand side of <= or = in the always statement change. 36

37 Combinational Logic using case module sevenseg(input logic [3:0] data, output logic [6:0] segments); always_comb case (data) // abc_defg 0: segments = 7'b111_1110; 1: segments = 7'b011_0000; 2: segments = 7'b110_1101; 3: segments = 7'b111_1001; 4: segments = 7'b011_0011; 5: segments = 7'b101_1011; 6: segments = 7'b101_1111; 7: segments = 7'b111_0000; 8: segments = 7'b111_1111; 9: segments = 7'b111_0011; default: segments = 7'b000_0000; // required endcase case statement implies combinational logic only if all possible input combinations described Remember to use default statement 37

38 3:8 Decoder module decoder3_8(input logic [2:0] a, output logic [7:0] y); always_comb case(a) 3'b000: y = 8'b ; 3'b001: y = 8'b ; 3'b010: y = 8'b ; 3'b011: y = 8'b ; 3'b100: y = 8'b ; 3'b101: y = 8'b ; 3'b110: y = 8'b ; 3'b111: y = 8'b ; default: y = 8'bxxxxxxxx; endcase 38

39 Priority Circuit module priorityckt(input logic [3:0] a, output logic [3:0] y); always_comb if (a[3]) y = 4'b1000; else if (a[2]) y = 4'b0100; else if (a[1]) y = 4'b0010; else if (a[0]) y = 4'b0001; else y = 4'b0000; 39

40 Don t Cares module priority_casez(input logic [3:0] a, output logic [3:0] y); always_comb casez(a) 4'b1???: y = 4'b1000; 4'b01??: y = 4'b0100; 4'b001?: y = 4'b0010; 4'b0001: y = 4'b0001; default: y = 4'b0000; endcase The casez statement acts like a case statement except that it also recognizes? as don t care. 40

41 Blocking vs. Nonblocking Assignment <= is nonblocking assignment Occurs simultaneously with others = is blocking assignment Occurs in order it appears in file // Good synchronizer using // nonblocking assignments module syncgood(input logic clk, input logic d, output logic q); logic n1; clk) begin n1 <= d; // nonblocking q <= n1; // nonblocking end // Bad synchronizer using // blocking assignments module syncbad(input logic clk, input logic d, output logic q); logic n1; clk) begin n1 = d; // blocking q = n1; // blocking end 41

42 Finite State Machines (FSMs) module divideby3fsm(input logic clk, input logic reset, output logic y); typedef enum logic [1:0] {S0, S1, S2} statetype; statetype state, nextstate; // state register clk, posedge reset) if (reset) state <= S0; else state <= nextstate; // next state logic always_comb case (state) S0: nextstate = S1; S1: nextstate = S2; S2: nextstate = S0; default: nextstate = S0; Endcase // output logic assign y = (state== S0); The typedef statement defines statetype to be a two-bit logic value with three possibilities: S0, S1, or S2. state and nextstate are statetype signals. 42

43 Testbenches A testbench is an HDL module that is used to test another module, called the device under test (DUT). The testbench contains statements to apply inputs to the DUT and, ideally, to check that the correct outputs are produced. The input and desired output patterns are called test vectors. 43

44 Testbenches module testbench1(); logic a, b, c; logic y; // instantiate device under test sillyfunction dut(a, b, c, y); // apply inputs one at a time initial begin a = 0; b = 0; c = 0; #10; c = 1; #10; b = 1; c = 0; #10; c = 1; #10; a = 1; b = 0; c = 0; #10; c = 1; #10; b = 1; c = 0; #10; c = 1; #10; end module sillyfunction(input logic a, b, c, output logic y); assign y = ~b & ~c a & ~b; 44

45 Self-checking Testbench module testbench2(); logic a, b, c, y; // instantiate device under test sillyfunction dut(a, b, c, y); // apply inputs one at a time // checking results initial begin a = 0; b = 0; c = 0; #10; assert (y === 1) else $error("000 failed."); c = 1; #10; assert (y === 0) else $error("001 failed."); b = 1; c = 0; #10; assert (y === 0) else $error("010 failed."); c = 1; #10; assert (y === 0) else $error("011 failed."); a = 1; b = 0; c = 0; #10; assert (y === 1) else $error("100 failed."); c = 1; #10; assert (y === 1) else $error("101 failed."); b = 1; c = 0; #10; assert (y === 0) else $error("110 failed."); c = 1; #10; assert (y === 0) else $error("111 failed."); end 45

46 Further Reading You can read Chapter 4 of your book. 46