Sequential Circuits. Combinational circuits

Transcription

1 ecoder emux onstructive omputer Architecture Sequential ircuits Arvind omputer Science & Artificial Intelligence Lab. Massachusetts Institute of Technology L04-1 ombinational circuits A 0 A 1 A n-1 Sel... lg(n) Mux O A Sel lg(n)... O 0 O 1 O n-1 A lg(n)... O 0 O 1 O n-1 A B OpSelect - Add, Sub,... - And, Or, Xor, Not,... - GT, LT, E, Zero,... ALU Result omp? Such circuits have no cycles (feedback) or state elements L04-2 1

2 Flip flop: The basic building block of Sequential ircuits Edge-Triggered Flip-flop Metastability ata is sampled at the rising edge of the clock L04-3 Flip-flops with Write Enables EN EN dangerous! EN EN 0 1 ata is captured only if EN is on L04-4 2

3 Registers En Register: A group of flip-flops with a common clock and enable Register file: A group of registers with a common clock, input and output port(s) L04-5 An example Modulo-4 counter Prev State NextState q1q0 inc = 0 inc = inc=0 inc= inc=1 inc=1 inc=1 inc=1 10 inc=0 inc=0 q0 t+1 = ~inc q0 t + inc ~q0 t q1 t+1 = ~inc q1 t + inc ~q1 t q0 t + inc q1 t ~q0 t L04-6 3

4 Modulo-4 counter circuit inc inc q0 q1 1 0 Modulo-4 counter Read the counter q0 t+1 = ~inc q0 t + inc ~q0 t q1 t+1 = ~inc q1 t + inc ~q1 t q0 t + inc q1 t ~q0 t Optimized logic q0 t+1 = inc q0 t q1 t+1 = (inc == 1)? q0 t q1 t : q1 t L04-7 Finite State Machines (Sequential kts) A computer (in fact all digital hardware) is an FSM Neither State tables nor diagrams are suitable for describing very large digital designs large circuits must be described in a modular fashion -- as a collection of cooperating FSMs BSV is a modern programming language to describe cooperating FSMs We will give various examples of FSMs in BSV L04-8 4

5 cnt modulo4 counter in BSV module moduloounter(ounter); Reg#(Bit#(2)) cnt <- mkreg(0); method Action inc; cnt <={~cnt[1]&cnt[0] cnt[1]&~cnt[0], ~cnt[0]}; method Bit#(2) read; return cnt; module inc.en an be replaced by cnt+1 ~cnt[1]& read L04-9 Interface Modulo counter has the following interface, i.e., type interface ounter; method Action inc; method Bit#(2) read; interface An interface can have many dierent implementations For example, the numbers may be represented as Gray code L

6 first Fifo module deq enq first Fifo module deq enq FIFO Interface interface Fifo#(numeric type size, type t); method Bool notfull; method Bool notempty; method Action enq(t x); x method Action deq; en method t first; interface en - enq should be called only if notfull returns True; - deq and first should be called only if notempty returns True notfull notempty first!emty!full L04-11 One-Element FIFO Implementation module mkffifo (Fifo#(1, t)); Reg#(t) d <- mkregu; Reg#(Bool) v <- mkreg(false); method Bool notfull; return!v; method Bool notempty; return v; method Action enq(t x); v <= True; d <= x; method Action deq; v <= False; method t first; return d; module en en x notfull notempty first!emty!full L

7 Two-Element FIFO module mkffifo (Fifo#(2, t)); Reg#(t) da <- mkregu(); Reg#(Bool) va <- mkreg(false); Reg#(t) db <- mkregu(); Reg#(Bool) vb <- mkreg(false); method Bool notfull; return!vb; method Bool notempty; return va; method Action enq(t x); if (va) begin db <= x; vb <= True; else begin da <= x; va <= True; method Action deq; if (vb) begin da <= db; vb <= False; else begin va <= False; method t first; return da; module db da Assume, if there is only one element in the FIFO it resides in da parallel composition of actions no change in fifo interface L04-13 Switch in red green if (in.first.color == Red) begin red.enq(in.first.value); in.deq; else begin green.enq(in.first.value); in.deq; let x = in.first; if (x.color == Red) red.enq(x.value); else green.enq(x.value); in.deq; parallel composition of actions. Eect of in.deq is not visible to in.first The code does not test for empty in or full red or full green conditions! L

8 Switch with empty/full tests on queues in red green if (in.notempty) begin if (in.first.color == Red) begin if (red.notfull) begin red.enq(in.first.value); in.deq; else begin if (green.notfull) begin Atomicity green.enq(in.first.value); in.deq; violation! in.deq; What s wrong if the deq is moved here? L04-15 Switch with counters in red green red green if (in.first.color == Red) begin red.enq(in.first.value); in.deq; red <= red+1; else begin green.enq(in.first.value); in.deq; green <= green+1; Ignoring full/empty conditions L

9 Shared counters if (ina.first.color == Red) begin reda.enq(ina.first.value); ina.deq; red <= red+1; else begin greena.enq(ina.first.value); ina.deq; green <= green+1; ; if (inb.first.color == Red) begin redb.enq(inb.first.value); inb.deq; red <= red+1; else begin greenb.enq(inb.first.value); inb.deq; green <= green+1; Ignoring full/empty conditions What is wrong with this code? ina reda greena red green inb redb greenb ouble write error L04-17 ouble-write problem Parallel composition is illegal if a double-write possibility exists If the BSV compiler cannot prove that the predicates for writes into a register or a method call are mutually exclusive, it rejects the program L

10 Observations These programs are not very complex and yet it would have been tedious to express these programs in a state table or as a circuit directly BSV method calls are not available in Verilog/VHL, and thus such programs sometimes require tedious programming Even the meaning of double-write errors is not standardized across tool implementations in Verilog L