Readings: Storage unit. Can hold an n-bit value Composed of a group of n flip-flops. Each flip-flop stores 1 bit of information.

Transcription

1 Registers Readings: Storage unit. Can hold an n-bit value Composed of a group of n flip-flops Each flip-flop stores 1 bit of information ff ff ff ff 178

2 Controlled Register Reset Load Action 0 0 = old 1 0 = = ff ff ff ff 179

3 Shift Register Register that shifts the binary values in one or both directions In Clock ff ff ff ff Out 180

4 Transfer of ata 2 modes of communication: Parallel vs. Serial Parallel: all bits transferred at the same time Serial: one bit transferred at a time Shift register can be used for serial transfer ff ff 181

5 Shift Register w/parallel Load Shift Load Action 0 0 = old 1 0 Shift X 1 Parallel Load ff ff ff ff 182

6 Conversion between Parallel & Serial 3 LSI 3 4-bit 2 2 Shift 1 1 Reg. 0 0 Shift Load Clk 3 LSI 3 4-bit 2 2 Shift 1 1 Reg. 0 0 Shift Load Clk Cycle Op - Sender Op - Recvr

7 Bidirectional Shift Register w/parallel Load Shift Load Action 0 0 = old 0 1 Parallel Load 1 0 Shift Up (V*2) 1 1 Shift own (V/2) ff ff ff ff 184

8 Counters A reg. that goes through a specific state sequence n-bit Binary Counter: counts from 0 to 2 N -1 in binary Up Counter: Binary value increases by 1 own Counter: Binary value decreases by 1 3-bit binary up counter state diagram: 185

9 Binary Up-Counter Imp. 186

10 Complex Binary Counter Load Count Action 0 0 = old 0 1 Up Count 1 0 Reset 1 1 Load Parallel 187

11 Arbitrary Sequence Counters esign a 3-bit count that goes through the sequence 000->010->100->101->111->110->001->011->000->

12 Counters in Verilog module upcounter #(parameter WITH=8) (out, incr, reset, ); output logic [WITH-1:0] out; input logic incr, reset, ; 189

13 Memory Need method for storing large amounts of data Computer programs, data, pictures, etc. Address ata x8 RAM RAM: Random Access Memory, Read/Write ROM: Read-only Memory A5 A4 A3 A2 A1 A0 Write

14 RAM Cell Requirements: Store one bit of data Change data based on input when row is selected Input Row Select en 191

15 Write 8x4 RAM In3 In2 In1 In0 3:8 ecoder Enable A2 A1 A0 111 S2 S1 S0 Out3 Out2 Out1 Out0 192

16 RAM example Use a memory to do a programmable 32-picture animation on a 7-segment display L 5 L 4 L0 L6 L3 L 1 L 2 193

17 Verilog Memories module memory16x6 (data_out, data_in, addr, we, ); output logic [5:0] data_out; input logic [5:0] data_in; input logic [3:0] addr; input logic we, ; logic [5:0] mem [15:0]; ) begin data_out <= mem[addr]; if (we) mem[addr] <= data_in; end 194

18 Field Programmable Gate Arrays (FPGAs) Readings: B.6-B.6.5 Logic cells imbedded in a general routing structure Logic cells usually contain: RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM RAM 6-input Boolean function calculator Flip-flop (1-bit memory) All features electronically (re)programmable 195

19 Using an FPGA // Verilog code for 2-input multiplexer // Verilog code for 2-input module multiplexer // AOI (F, Verilog A, B, C, code ); for 2-input output multiplexer F; input module A, // AOI B, C, (F, Verilog ; A, B, C, code ); for 2-input output multiplexer F; module AOI (F, A, B, C, ); assign input output F A, = B, ~((A C, ; F; & B) (C & )); input module A, AOI B, C, (F, ; A, B, C, ); assign output F = ~((A F; & B) (C & )); assign input F A, = B, ~((A C, ; & B) (C & module )); MUX2 (V, SEL, I, J); // 2:1 multiplexer assign F = ~((A & B) (C & output module V; )); MUX2 (V, SEL, I, J); // input 2:1 multiplexer module SEL, I, MUX2 J; (V, SEL, I, J); // wire output 2:1 SELB, V; multiplexer VB; input output module SEL, I, V; MUX2 J; (V, SEL, I, J); // not wire G1 input (SELB, 2:1 SELB, multiplexer VB; SEL, SEL); I, J; AOI G2 wire (VB, output SELB, I, SEL, V; not G1 VB; SELB, J); not G3 (V, input (SELB, VB); SEL, SEL); I, J; AOI G2 not wire (VB, G1 (SELB, SELB, I, SEL, SEL); VB; SELB, J); not G3 (V, VB); AOI G2 (VB, I, SEL, SELB, J); not not G3 (V, G1 (SELB, VB); SEL); AOI G2 (VB, I, SEL, SELB, J); not G3 (V, VB); Verilog FPGA CA Tools Bitstream Simulation 196

20 FPGA Programming Bitstream P P P P S1 S1 4:1 MUX 4:1 MUX S0 S0 F F P P P = 1 memory cell (stores 1 bit of info) 197

21 FPGA Combinational Logic How can we use Muxes and Programming bits to compute combinational binary function F(A,B,C)? :1 4 MUX S2 S1 S0 F Creates a LUT or lookup table. 198

22 FPGA Sequential Logic How do we put FF s onto LUT outputs only when we need them? 3-LUT flipflop Clk A B C Creates a LE or logic block 199

23 FPGA Local Routing How do we combine LE s to build larger functions? In1 LE In2 LE Out1 In3 LE Out2 In4 LE This is an Altera LAB. 200

24 FPGA Global Routing Can t do all-to-all/crossbar routing, so what? LAB LAB LAB LAB 201

25 FPGA CA CA = Computer-Aided esign // Verilog code for 2-input multiplexer // Verilog code for 2-input module multiplexer // AOI (F, Verilog A, B, C, code ); for 2-input output multiplexer F; input module A, // AOI B, C, (F, Verilog ; A, B, C, code ); for 2-input output multiplexer F; module AOI (F, A, B, C, ); assign input output F A, = B, ~((A C, ; F; & B) (C & )); module AOI (F, A, B, C, ); input A, B, C, ; assign output F = ~((A F; & B) (C & )); input A, B, C, ; assign F = ~((A & B) (C & module )); MUX2 (V, SEL, I, J); // 2:1 multiplexer assign F = ~((A & B) (C & output module V; )); MUX2 (V, SEL, I, J); // input 2:1 multiplexer module SEL, I, MUX2 J; (V, SEL, I, J); // wire output 2:1 SELB, V; multiplexer VB; inputmodule SEL, I, MUX2 J; (V, SEL, I, J); // output V; not wire G1 2:1 SELB, multiplexer VB; input (SELB, SEL, SEL); I, J; AOI G2 output V; not wire (VB, G1 SELB, I, SEL, VB; SELB, J); not G3 (V, input (SELB, VB); SEL, SEL); I, J; AOI G2 wire (VB, SELB, I, SEL, VB; SELB, J); not not G3 (V, G1 (SELB, VB); SEL); AOI G2 (VB, I, SEL, SELB, J); not G1 (SELB, SEL); not G3 (V, VB); AOI G2 (VB, I, SEL, SELB, J); not G3 (V, VB); Verilog FPGA CA Tools Bitstream Tech Mapping: Convert Verilog to LUTs Placement: Assign LUTs to specific locations Routing: Wire inputs to outputs Bitstream Generation: Convert mapping to bits 202

26 Modern FPGA: Stratix V Logic Blocks Multipliers & SP Embedded Memories Clocking Logic I/O Protocols 203

27 E1-SoC FPGA: Cyclone V 5CSEMA5F31C6N ALMs (2x6-LUT): 32k FFs: 128k RAMs (10Kb): 3.9k 18x18 Hard Multipliers: 174 Clock generators (PLLs): 6 General-purpose I/Os: 288 ARM Cortex A9 cores: 2 204