CHAPTER 12 REGISTERS AND COUNTERS

Size: px

Start display at page:

Download "CHAPTER 12 REGISTERS AND COUNTERS"

Annabel Bailey
5 years ago
Views:

1 HPTER 2 REGISTERS N OUNTERS

2 ontents 2. Registers and Register Transfers 2.2 Shift Registers 2.3 esign of inary ounters 2.4 ounters for Other Sequences 2.5 ounter esign Using SR and JK FlipFlops 2.6 erivation of FlipFlop Input EquationsSummary

3 Objectives. Explain the operation of registers. Understand how to transfer data between registers using tristate bus 2. Explain the shift register operation, how to build them and analyze operation. onstruct a timing diagram for a shift register 3. Explain the operation of binary counters, how to build them using F/F and gates and analyze operation. 4. Given the present state and desired next state of F/F, determine the required F/F/ inputs 5. Given the desired counting sequence for a counter, derive F/F input equations. 6. Explain the procedures used for deriving F/F input equation. 7.onstruct a timing diagram for a counter by tracing signals through the circuit.

4 2. Registers and Register Transfers Figure 2. 4it FlipFlop Registers with ata, Load, lear, and lock inputs Grouped together F/F Using gated clock(a) F/F with clock enable Figure 2(b) Symbol for the 4bit register using bus notation Figure 2(c )

5 2. Registers and Register Transfers ata Transfer etween Registers

6 2. Registers and Register Transfers Logic iagram for 8it Register with TriState Output

7 2. Registers and Register Transfers ata Transfer Using a TriState us

8 2. Registers and Register Transfers How data can be transferred? The operation can be summarized as follows: If EF, is stored in G(or H ). If EF, is stored in G(or H ). If EF, is stored in G(or H ). If EF, is stored in G(or H ).

9 2. Registers and Register Transfers Parallel dder with ccumulator Nit Parallel dder with ccumulator

10 2. Registers and Register Transfers dder ell with Multiplexer (Figure 26)

11 22 Shift Registers RightShift Register

12 22 Shift Registers 8it Serialin, Serialout Shift Register

13 Typical Timing iagram for Shift Register 22 Shift Registers

14 22 Shift Registers Parallelin, ParallelOut Right Shift Register

15 22 Shift Registers Shift Register Operation (Table 2) Inputs Sh(Shift) L(Load) SI Next State ction no change load right shift

16 Timing iagram for Shift Register 22 Shift Registers

17 22 Shift Registers The Nextstate equations for the F/F are SI Sh L Sh L Sh Sh L Sh L Sh Sh L Sh L Sh Sh L Sh L Sh

18 22 Shift Registers Shift Register with Inverted Feedback (Figure 22) Johnson ounter 3bit shift register 22(a) Successive states 22(b)

19 2.3 esign of inary ounters binary counter using three T F/F to count clock pulses Synchronous inary ounter (Figure 23) ounting sequence :

20 2.3 esign of inary ounters State Table for inary ounter (Table 22) Flip Flop Inputs Next State Present State T T T

21 2.3 esign of inary ounters Karnaugh Map for inary ounter (Figure 24) Ta, Tb, Tc

22 2.3 esign of inary ounters inary ounter with FlipFlops (Figure 25)

23 2.3 esign of inary ounters The input equations derived from the maps are ( ) Karnaugh Maps for FlipFlops (Figure 26)

24 2.3 esign of inary ounters State Graph and Table for Upown counter (Figure 27) When U, Up counting When, own counting U

25 2.3 esign of inary ounters The updown counter can be implemented using F/F and gate inary Upown ounter (Figure 28)

26 2.3 esign of inary ounters The corresponding logic equations are ) ( ) ( ) ( U U U When U and, these equations reduce to ) change state when ( ) change state when ( change state every clock cycle) (

27 2.3 esign of inary ounters Loadable ounter with ount Enable (Figure 29) Loadable counter (Figure 29(a)) Summarizes the counter operation (Figure 29(b)) lrn Ld t present state ( load) ( no change) (b)

28 2.3 esign of inary ounters ircuit for Figure 29 (Figure 22)

29 2.3 esign of inary ounters The nextstate equations for the counter of Figure 22 ( Ld Ld in ) Ld t ( Ld Ld in ) Ld t c ( Ld Ld in ) Ld t

30 2.4 ounters for Other Sequences The sequence of states of a counter is not in straight binary order. State Graph for ounter (Figure 22) State Table for Figure 2.2 (Table 23)

31 2.4 ounters for Other Sequences The nextstate maps in Figure 222(a) are easily plotted from inspection of Table 23 Use TF/F Figure 222

32 2.4 ounters for Other Sequences Input for T FlipFlop T (Table 24) T ounter Using T FlipFlops (Figure 223)

33 2.4 ounters for Other Sequences Timing iagram for Figure 223 (Figure 224) State Graph for ounter (Figure 225)

34 2.4 ounters for Other Sequences Summary:.Form a state table which gives the next F/F states for each combination of present F/F states. 2.Plot the nextstate maps from the table. 3.Plot a T input map for each F/F. 4.Find the T input equations from the maps and realize the circuit.

35 2.4 ounters for Other Sequences ounter esign Using FlipFlop Following equations can be read from Figure 222(a): ( ) ounter of Figure 22 Using FlipFlops (Figure 226)

36 2.5 ounter esign Using SR and JK FlipFlops SR FlipFlop Inputs (Table 25) R S Inputs not allowed (a) S R (b) S R (c)

37 2.5 ounter esign Using SR and JK FlipFlops With columns added for the S and R flipflop inputs (Table 26) R S R S R S

38 2.5 ounter esign Using SR and JK FlipFlops ounter esign Using SR FlipFlop

39 2.5 ounter esign Using SR and JK FlipFlops K J K J K J (a) (b) (c) JK FlipFlop Inputs (Table 27)

40 2.5 ounter esign Using SR and JK FlipFlops K J K J K J With columns added for the J and K flipflop inputs (Table 28)

41 2.6 erivation of FlipFlop Input EquationsSummary ounter of Figure 22 Using JK FlipFlops (Figure 228)

42 2.6 erivation of FlipFlop Input EquationsSummary etermination of FlipFlop Input Equations from NextState Equations Using Karnaugh Maps (Table 29)

43 2.6 erivation of FlipFlop Input EquationsSummary Example (illustrating the use of Table 29)

44 2.6 erivation of FlipFlop Input EquationsSummary erivation of FlipFlop Input Equations Using 4Variable Maps (Figure 229)

EE 459/500 HDL Based Digital Design with Programmable Logic. Lecture 6 Combinational and sequential circuits

EE 459/500 HDL Based Digital Design with Programmable Logic. Lecture 6 Combinational and sequential circuits EE 459/5 HL Based igital esign with Programmable Logic Lecture 6 ombinational and sequential circuits Read before class: hapter 2 from textbook Overview ombinational circuits Multiplexer, decoders, encoders,