Abstraction of State Elements. Sequential Logic Implementation. Forms of Sequential Logic. Finite State Machine Representations

Transcription

1 Sequential ogic Implementation! Models for representing sequential circuits " Finite-state machines (Moore and Mealy) " epresentation of memory (states) " hanges in state (transitions)! Design procedure " State diagrams " State transition table " Next state functions bstraction of State Elements! Divide circuit into combinational and state! ocalize feedback loops and make it easy to break cycles! Implementation of storage elements leads to various forms of sequential Inputs ombinational ogic Outputs State Inputs State Outputs Storage Elements S 5 - Spring 27 ec #6: Moore and Mealy Machines - S 5 - Spring 27 ec #6: Moore and Mealy Machines - 2 Forms of Sequential ogic! synchronous sequential state changes occur whenever state inputs change (elements may be simple wires or delay elements)! Synchronous sequential state changes occur in lock step across all storage elements (using a periodic waveform - the clock) Finite State Machine epresentations! States: determined by possible values in sequential storage elements! Transitions: change of state! lock: controls when state can change by controlling storage elements In = In = In =! Sequential ogic In = " Sequences through a series of states " ased on sequence of values on input signals " lock period defines elements of sequence lock S 5 - Spring 27 ec #6: Moore and Mealy Machines - 3 S 5 - Spring 27 ec #6: Moore and Mealy Machines - 4 Example Finite State Machine Diagram an ny Sequential System be epresented with a State Diagram?! ombination lock from first lecture E! Shift egister " Input value shown on transition arcs " Output values shown within state node IN K OUT OUT2 OUT3 D Q D Q D Q reset not equal not equal not equal S S2 S3 OPEN open mux= equal mux=2 equal mux=3 equal not new not new not new S 5 - Spring 27 ec #6: Moore and Mealy Machines - 5 S 5 - Spring 27 ec #6: Moore and Mealy Machines - 6

2 ounters are Simple Finite State Machines! ounters " Proceed thru well-defined state sequence in response to enable! Many types of counters: binary, D, Gray-code " 3-bit up-counter:,,,,,,,,,... " 3-bit down-counter:,,,,,,,,,... 3-bit up-counter Verilog Upcounter module binary_cntr (q, clk) inputs clk; outputs [2:] q; reg [2:] q; reg [2:] p; //alculate next state case (q) 3 b: p = 3 b; 3 b: p = 3 b; 3 b: p = 3 b; endcase clk) //next becomes current state q <= p; endmodule S 5 - Spring 27 ec #6: Moore and Mealy Machines - 7 S 5 - Spring 27 ec #6: Moore and Mealy Machines - 8 How Do We Turn a State Diagram into ogic?! ounter " Three flip-flops to hold state " ogic to compute next state " lock signal controls when flip-flop memory can change # Wait long enough for combinational to compute new value # Don't wait too long as that is low performance K OUT OUT2 OUT3 D Q D Q D Q FSM Design Procedure! Start with counters " Simple because output is just state " Simple because no choice of next state based on input! State diagram to state transition table " Tabular form of state diagram " ike a truth-table! State encoding " Decide on representation of states " For counters it is simple: just its value! Implementation " Flip-flop for each state bit " ombinational based on encoding "" S 5 - Spring 27 ec #6: Moore and Mealy Machines - 9 S 5 - Spring 27 ec #6: Moore and Mealy Machines - FSM Design Procedure: State Diagram to Encoded State Transition Table Implementation! Tabular form of state diagram! ike a truth-table (specify output for all input combinations)! Encoding of states: easy for counters just use value 3-bit up-counter current state next state S 5 - Spring 27 ec #6: Moore and Mealy Machines -! D flip-flop for each state bit! ombinational based on encoding N3 3 2 N3 N2 N 2 3 N2 N := ' N2 := 2' + '2 := xor 2 N3 := 23' + '3 + 2'3 := 23' + (' + 2')3 := (2) xor 3 3 N 2 S 5 - Spring 27 ec #6: Moore and Mealy Machines - 2 notation to show function represent input to D-FF 2 3

3 Implementation (cont'd) nother Example! Programmable ogic uilding lock for Sequential ogic " Macro-cell: FF + # D-FF # Two-level capability like P (e.g., 8 product terms) S 5 - Spring 27 ec #6: Moore and Mealy Machines - 3 D Q Q! Shift egister " Input determines next state In 2 3 N N2 N3 N := In N2 := N3 := 2 IN K S 5 - Spring 27 ec #6: Moore and Mealy Machines - 4 D Q D Q D Q OUT OUT2 OUT3 More omplex ounter Example More omplex ounter Example (cont d)! omplex ounter " epeats five states in sequence " Not a binary number representation! Step : Derive the state transition diagram " ount sequence:,,,,! Step 2: Derive the state transition table from the state transition diagram! Step 3: K-maps for Functions Present State note the don't care conditions that arise from the unused state codes S 5 - Spring 27 ec #6: Moore and Mealy Machines := + := ' + '' + := ' S 5 - Spring 27 ec #6: Moore and Mealy Machines - 6 Self-Starting ounters (cont d)! e-deriving state transition table from don't care assignment + + Present State S 5 - Spring 27 ec #6: Moore and Mealy Machines Self-Starting ounters! Start-up States " t power-up, counter may be in an unused or invalid state " Designer must guarantee it (eventually) enters a valid state! Self-starting Solution " Design counter so that invalid states eventually transition to a valid state " May limit exploitation of don't cares S 5 - Spring 27 ec #6: Moore and Mealy Machines - 8 implementation on previous slide

4 State Machine Model State Machine Model (cont d)! Values stored in registers represent the state of the circuit! ombinational computes: " Next state # Function of current state and inputs " Outputs # Function of current state and inputs (Mealy machine) # Function of current state only (Moore machine)! States: S, S 2,..., S k! Inputs: I, I 2,..., I m Inputs! Outputs: O, O 2,..., O n! Transition function: F s (S i, I j )! Output function: F o (S i ) or F o (S i, I j ) output next state urrent State Outputs Inputs output next state Outputs State lock urrent State S 5 - Spring 27 ec #6: Moore and Mealy Machines - 9 S 5 - Spring 27 ec #6: Moore and Mealy Machines - 2 First Midterm Exam 5 February 27! Topics to be covered: " ombinational design # From spec to truth table to K-map to oolean Expression anonical forms of oolean Expressions onversions of ND-O to NND or NO # Two level implementations using gates, P, MU, DE, OM, ilinx FPG structures omparing implementation complexities/figures of merit ombinational Verilog (lab expertise!) " asic Sequential design # Flip flop behavior, analysis, and timing diagrams # Using flip flops to design registers, shifters, counters # From spec to state diagram to Sequential Verilog # mount of FSM implementation through end of today First Midterm Exam 5 February 27! Exam mechanics " Worth ON % of course grade " In class, designed for hour, full 8 minutes available " WI TKE PE IN 25 O OTO!!! " No lue ook all work to be done on the exam paper! # ring pencil and eraser DUM to use pen! # heating = on exam DO NOT DO IT! F in class plus letter to file for second offense " losed ook, losed Notes UT # 8.5 x two-sided crib sheet OK Developing your crib sheet is a great way to study Don t forget old exams and solutions are all on-line # No calculators, PDs, laptops, camera phones, icq to experts " Write assumptions if problem spec is ambiguous # Difficult to ask questions during the exam itself " Written regrade appeals policy S 5 - Spring 27 ec #6: Moore and Mealy Machines - 2 S 5 - Spring 27 ec #6: Moore and Mealy Machines - 22 Example: nt rain (Ward, MIT) nt rain! Sensors: and antennae, if in touching wall! ctuators: F - forward step, T/T - turn left/right slightly! Goal: find way out of maze! Strategy: keep the wall on the right S 5 - Spring 27 ec #6: Moore and Mealy Machines - 23 S 5 - Spring 27 ec #6: Moore and Mealy Machines - 24

5 nt ehavior Designing an nt rain : Following wall, touching Go forward, turning left slightly : Following wall, not touching Go forward, turning right slightly! State Diagram + : reak in wall Go forward, turning right slightly D: Hit wall again ack to state OST + (T) (T, F) E: Wall in front Turn left until... F:...we are here, same as state (T, F) (T, F) OST: Forward until we touch something G: Turn left until... S 5 - Spring 27 ec #6: Moore and Mealy Machines - 25 S 5 - Spring 27 ec #6: Moore and Mealy Machines - 26 Synthesizing the nt rain ircuit Transition Truth Table! Encode States Using a Set of State Variables " rbitrary choice - may affect cost, speed! Use Transition Truth Table " Define next state function for each state variable " Define output function for each output! Implement next state and output functions using combinational " 2-level (OM/P/P) " Multi-level " Next state and output functions can be optimized together! Using symbolic states and outputs OST state next state outputs OST OST F OST F OST F T, F T, F T, F T, F T, F (T) (T, F) + (T, F) (T, F) S 5 - Spring 27 ec #6: Moore and Mealy Machines - 27 S 5 - Spring 27 ec #6: Moore and Mealy Machines - 28 Synthesis Synthesis of and Output Functions! 5 states : at least 3 state variables required (,, Z) " State assignment (in this case, arbitrarily chosen) state next state outputs,,z ', ', Z' F T T it now remains to synthesize these 6 functions OST state inputs next state outputs,,z +, +,Z + F T T e.g. T = + Z + = + Z = T S 5 - Spring 27 ec #6: Moore and Mealy Machines - 29 S 5 - Spring 27 ec #6: Moore and Mealy Machines - 3

6 ircuit Implementation! Outputs are a function of the current state only - Moore machine output next state urrent State + + Z + Z F T T Verilog Sketch module ant_brain (F, T, T,, ) inputs, ; outputs F, T, T; reg,, Z; assign F = function(,, Z,, ); assign T = function(,, Z,, ); assign T = function(,, Z,, ); clk) begin <= function (,, Z,, ); <= function (,, Z,, ); Z <= function (,, Z,, ); end endmodule S 5 - Spring 27 ec #6: Moore and Mealy Machines - 3 S 5 - Spring 27 ec #6: Moore and Mealy Machines - 32 Don t ares in FSM Synthesis State Minimization! What happens to the "unused" states (,, )?! Exploited as don't cares to minimize the " If states can't happen, then don't care what the functions do " if states do happen, we may be in trouble + (T) + (T, F) (T, F) (T, F) nt is in deep trouble if it gets in this state S 5 - Spring 27 ec #6: Moore and Mealy Machines - 33! Fewer states may mean fewer state variables! High-level synthesis may generate many redundant states! Two state are equivalent if they are impossible to distinguish from the outputs of the FSM, i. e., for any input sequence the outputs are the same! Two conditions for two states to be equivalent: " ) Output must be the same in both states " 2) Must transition to equivalent states for all input combinations S 5 - Spring 27 ec #6: Moore and Mealy Machines - 34 nt rain evisited New Improved rain! ny equivalent states? +! Merge equivalent and states! ehavior is exactly the same as the 5-state brain! We now need only 2 state variables rather than 3 OST + (T) (T, F) (T, F) (T, F) OST + (T) / (T, F) + (T, F) S 5 - Spring 27 ec #6: Moore and Mealy Machines - 35 S 5 - Spring 27 ec #6: Moore and Mealy Machines - 36

7 New rain Implementation Sequential ogic Implementation Summary state inputs next state outputs, ',' F T T F + T + T! Models for representing sequential circuits " bstraction of sequential elements " Finite state machines and their state diagrams " Inputs/outputs " Mealy, Moore, and synchronous Mealy machines! Finite state machine design procedure " Deriving state diagram " Deriving state transition table " Determining next state and output functions " Implementing combinational S 5 - Spring 27 ec #6: Moore and Mealy Machines - 37 S 5 - Spring 27 ec #6: Moore and Mealy Machines - 38