CSE 271 Introduction to Digital Systems Supplementary Reading Datapath and Control for Basic Algorithmic Statements

Transcription

1 CSE 271 Introduction to igital Systems Supplementary Reading atapath and Control for Basic Algorithmic Statements In this supplementary reading, we present the basic structure of datapath and control for four basic algorithmic statements along with examples. These basic algorithmic statements and basic datapath and control structures can serve as building blocks for more complicated algorithms. Assignment Statement Consider the assignment statement in the form of X=value The datapath and control structure required to realize the assignment statement is shown in Figure 1. value control oad Buffer Reg Q X Figure 1. Basic structure of datapath and control for the assignment statement. Remark 1. The followings are some remarks on Figure 1. (a) In the state in Figure 1, a typical control signal to include is a signal for the load capability of the buffer register in the datapath unit. In fact, we may enable the oad bits of two or more registers simultaneously, which allows simultaneous assignments of several variables in one clock cycle. (b) In Figure 1, for illustration purpose, we only show a control signal between the control and datapath units. In many cases, depending on the specific needs, we may need to include one or more and/or control signals. (c) In Figure 1, the transition arc from the to the states is a default transition, which means that for all valid control input valuations, the transition will always take place at the next active clock edge. For such a default transition, we may simply draw the arc without labeling it with any input valuation. Also, due to this default transition, the FSM for the control unit will only stay at the state for one clock cycle. Example 1. esign a circuit using the datapath and control approach for the following statement. X = 3 where X is an -bit binary number. A circuit for the above statement is shown in Figure 2 (for clarity of presentation, we do not explicitly show the and Clock signals, which are connected to the appropriate lines of the circuit). 1

2 3 bit Buffer Reg X Figure 2. A circuit for Example 1. For the FSM of the control unit, there is no input (i.e., signal of the datapath unit) and one output (i.e., control signal of the datapath unit). The following table lists the meaning of the output valuations. Output 1 load register holdregdata State Output 1 Conditional Statement Consider the conditional statement in the form of if (condition) then Body1 else Body2 Here Body1andBody2 may contain none or several statements. The datapath and control structure required to realize this conditional statement is shown in Figure 3. Body1 Body2 Figure 3. Basic structure of datapath and control for the conditional statement. Remark 2. The followings are some remarks on Figure 3. (a) In Figure 3, a typical signal to include is a signal indicating whether the condition is true or false. 2

3 (b) In Figure 3, the label from to Body1 corresponds to the case when the condition is satisfied (i.e., = true). Note that if the signal is active-high, this transition corresponds to =1;ifthe signal is active-low, this transition corresponds to =. (c) The transitions from Body1 andbody2 to are default transitions (see Remark 1 above for more on default transitions). Example 2. esign a circuit using the datapath and control approach for the following statement. if (X > 2) Y = X; else Y = 2; where X and Y are -bit unsigned binary numbers. A circuit for the above statement is shown in Figure. G G G X 2 bit Comparator E G Stmt1 Stmt2 SelMux s 1 bit 2 to 1 MUX bit Buffer Reg Y Figure. A circuit for Example 2. For the FSM of the control unit, the following table lists the inputs and outputs and the meaning of their valuations. Input G SelMux 1 X>2 1 s =1forMUX 1 load register X 2 s =formux holdregdata State SelMux Stmt1 1 1 Stmt2 1 for oops Consider the looping statement in the form of for(i=n1;i< N2;i=i+1)Body Here Body may contain none or several statements. The datapath and control structure required to realize this looping statement is shown in Figure 5. 3

4 N1 Enable Up Counter Comp Body N2 Comparator E G Figure 5. Basic structure of datapath and control for the for loop. Remark 3. The followings are some remarks on Figure 5. (a) At the state in Figure 5, the FSM sends control signal to the datapath to initialize i = N1. (b) In Figure 5, a typical signal to include is a signal indicating that i<n2. Also two control signals are included. In many cases, depending on the specific needs, we may include more and/or control signals. (c) The transitions from to Comp and from Body to Comp are default transitions. Example 3. esign a circuit using the datapath and control approach for the following statement. A = ; for (i = 1; i < 9; i = i+1) {A = A+i;} where i and A are -bit and 6-bit unsigned binary numbers, respectively. A circuit for the above statement is shown in Figure 6. Comp Add EnCnt dcnt 1 Enable bit Up Counter i 9 bit Comparator E G 6 6 bit Adder s bit Buffer Reg A 6 Figure 6. A circuit for Example 3. For the FSM of the control unit, the following table lists the inputs and outputs and the meaning of their valuations.

5 Input G EnCnt dcnt 1 i<9 1 enable counter (in 1 load counter 1 load register this case, if also oad=, count; oad=1, load) i 9 disable counter (in this case, if also oad=, hold; oad=1, load) not load counter holdregdata State EnCnt dcnt 1 Comp Add 1 1 Note from the table that here we update A and i simultaneously at the active clock edge after the FSM moves to the Add state. while oops Consider the looping statement in the form of while (condition) Body Here Body may contain none or several statements. The datapath and control structure required to realize this looping statement is shown in Figure 7. Comp Body Figure 7. Basic structure of datapath and control for the while loop. Remark. The followings are some remarks on Figure 7. (a) At the state in Figure 7, the FSM may send control signal to the datapath to initialize some variables. (b) In Figure 7, the label from Comp to Body corresponds to the case when the condition is satisfied (i.e., = true). Note that if the signal is active-high, this transition corresponds to =1;ifthe signal is active-low, this transition corresponds to =. (c) The transitions from to Comp and from Body to Comp are default transitions. 5

6 Example. esign a circuit using the datapath and control approach for the following statement. A = ; i = ; while ( M[i]!= ) {A = A + M[i]; i = i + 1;} where i and A are -bit and 16-bit unsigned binary numbers, respectively. M[i] is the -bit data stored at address i of a 256 RAM. The above statement sums up the data stored in the RAM from address up to the address immediately before the occurrence of the first data. (This first indicates the tail of the nonzero data sequence. Here we assume that there is at least one data in the RAM.) A circuit for the above statement is shown in Figure. Comp Tail Tail Add Tail CS,RE,WE EnCnt dcnt Enable 16 bit Up Counter x 16 bit Adder s 16 y address 256 X RAM CS,RE,WE data M[i] bit Comparator E G 16 bit Buffer Reg A 16 Figure. A circuit for Example. For the FSM of the control unit, the following table lists the inputs and outputs and the meaning of their valuations. Input Tail CS RE WE EnCnt dcnt 1 tail of 1 RAM 1 readenabled 1 write 1 enable 1 load 1 load seq reached activated enabled counter counter register tail of RAM readdisabled write disable not load holdreg seq reached deactivated disabled counter counter data State CS RE WE EnCnt dcnt 1 Comp 1 1 Add Note from the table that here we update A and i simultaneously at the active clock edge after the FSM moves to the Add state. 6

7 A Minimum Search Example By combining the aforementioned basic algorithms, we can build many useful datapath and control circuits to solve many interesting problems. Example 5. esign a circuit using the datapath and control approach that searches for the minimum integer in a 256 RAM. The numbers are stored at addresses, 1,, 179 (assume that the RAM has already been loaded with the data). The following is an algorithm for this minimum search problem. min = 255; for (i = ; i < 1; i = i+1) if ( M[i] < min ) {min = M[i];} } where i is an -bit unsigned binary numbers. M[i] is the -bit data stored at address i of a 256 RAM. A circuit for the above statement is shown in Figure 9. Cnt CompI CompM M Cnt M CS,RE,WE 3 Enable bit Up Counter i 1 bit Comparator E G address 256 X RAM CS, RE,WE data Cnt M IncI NewMin EnCnt dcnt SelMux \s bit 2 to 1 MUX bit Buffer Reg bit Comparator E G min Figure 9. A circuit for Example 5. For the FSM of the control unit, the following tables lists the inputs and outputs and the meaning of their valuations. Inputs Cnt M 1 i<1 1 M[i] <min i 1 M[i] min CS RE WE EnCnt dcnt SelMux 1 RAM 1 readenabled 1 write 1 enable 1 load 1 s = 1 1 load activated enabled counter counter for MUX register RAM readdisabled write disable not load s = holdreg deactivated disabled counter counter for MUX data 7

8 State CS RE WE EnCnt dcnt SelMux 1 1 CompI CompM 1 1 NewMin IncI 1