CS 151 Midterm. Instructions: Student ID. (Last Name) (First Name) Signature

Transcription

1 CS 151 Midterm Name Student ID Signature :, (Last Name) (First Name) : : Instructions: 1. Please verify that your paper contains 11 pages including this cover. 2. Write down your Student-Id on the top of each page of this quiz. 3. This exam is closed book. No notes or other materials are permitted. 4. Total credits of this midterm are 70 points. 5. To receive credit you must show your work clearly. 6. For possible re-grade request make sure that your write clearly. 7. Calculators are NOT allowed. CS 151 Digital Logic Design, Spring Quarter 2007, Midterm Page 1

2 Q1: [ALU] [20 points] We are going to design a 4-bit Arithmetic Unit (AU) with the following functional table: M1 M0 Function Name F(A,B) 0 0 A + A multiplied by 8 times B A*(8*B)+A 0 1 If (A>B) subtract B from A; otherwise add A and B If (A>B) then A-B; else A+B 1 0 Decrement A A Add 1 to A+B A+B+1 A and B are two 4-bit binary numbers a3a2a1a0 and b3b2b1b0. M1, M0 are the control inputs to this AU. For doing this, the block labeled AL-Extender in the following block diagram should be designed. In this question you should design the logic inside AL-Extender using JUST Comparators and Multiplexers if needed. ALU a 3 a 2 a 1 a 0 b 3 b 2 b 1 b 0 M1 AL-Extender M0 IA IB Full Adder Cin IS s 3 s 2 s 1 s 0 CS 151 Digital Logic Design, Spring Quarter 2007, Midterm Page 2

3 <This page is intentionally left blank> A[3:0] B[3:0] Comparator B [3:0] B[3:0] a I1 A<=B 0 I0 A>B I1 C[3:0] I0 I1 I0 D b 0 X b 3 1 c 3 d b 2 1 c 2 0 b 1 1 c 1 0 b 0 0 c X 0 S0 I 0 I 1 I 2 I 3 S0 I 0 I 1 I 2 I 3 S0 I 0 I 1 I 2 I 3 S0 I 0 I 1 I 2 I 3 S0 I 0 I 1 I 2 I 3 IB 3 IB 2 IB 1 IB 0 Cin CS 151 Digital Logic Design, Spring Quarter 2007, Midterm Page 3

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5 Q2: [High-Level State Machine Design] [15 points] Design the high-level state machine for a DVD player with the following functionality: Initially when we turn on the system it is in STOP mode and we can assume that there is a DVD already inserted in. The DVD player has four buttons: STOP, PLAY, FF (Fast Forward) and FB (Fast Backward). While in STOP mode if we hit STOP or FF or FB button we should stay at the same state. As well whenever we reach the STOP mode the value of the timer resets to ZERO. Once we hit PLAY button, the DVD player starts playing and every cycle the timer of the player is incremented by one unless it reaches the end of the DVD (time 200) when it goes to STOP mode automatically. While in play mode if we hit FF button and keep it depressed for just one clock cycle the timer is incremented by 50 and then we automatically go back to play mode. If we hit the FF button the next clock cycle the DVD player goes to Fast Forward mode and the timer is incremented by 5 for each cycle. The DVD player will remain at the same state unless: we hit the PLAY button or the FB button which takes us to the PLAY mode; or the end of the DVD is reached or we hit the STOP button which puts the player in STOP mode; The same thing happens if we push FB button with the difference that the timer is decremented by the same amount of FF mode. The player remains at FB mode unless: we hit the PLAY button or the FF button which takes the player to the PLAY mode; the beginning of the DVD is reached where the timer is set to ZERO and the player goes to the PLAY mode automatically; the STOP button is hit which puts the player in STOP mode; CS 151 Digital Logic Design, Spring Quarter 2007, Midterm Page 5

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7 Q3: [RTL design] [35 points] Considering the following high-level state machine and assuming that X, Y, START and STOP are one bit control inputs and T is an 8-bit output of the circuit:!start T<30 X START Standby T=T+1 T>=30 & Y T<30 Y T>=30 STOP T=T+1 S2 START T>=30 STOP!START T=T+1 T>=60 STOP Z=1 T<60 CS 151 Digital Logic Design, Spring Quarter 2007, Midterm Page 7

8 3a. Design the data-path for this system. [15 points] 1 S T-sel T 1 T-ld T Reg Adder T S T Comp-Sel A Comparator T>=A T<A CS 151 Digital Logic Design, Spring Quarter 2007, Midterm Page 8

9 3b. Design the interface of the system and the interface between the controller and the datapath. [5 points] START STOP X Y T>=A T<A Controller T-Sel Data path T-ld Comp-Sel T[7:0] CS 151 Digital Logic Design, Spring Quarter 2007, Midterm Page 9

10 3c. Design the FSM of the controller. [15 points] HINT: There is no timing issue for this system so you do not have to consider timing issues in designing the controller s FSM.!START T<A Standby X START T-ld = 1 Comp_sel = 1 T>=A & Y T<A Y T-ld = 1 Comp_sel = 1 S2!START START T-ld = 1 Comp_sel = 0 T>=A STOP T>=A STOP T=1 T>=A STOP T<A In fact there is a timing issue in each of the states that increments T. To solve the timing issue we have to add a dummy state for each problematic state. This dummy state is just supposed to provide one more clock cycle for the register to load the value. All the incoming edges still enter to the original state. On the other hand all the outgoing edges exit the dummy state. For the sake of grading, the students do not have to be concerned about the timing issue as the problem had wanted them to ignore it. CS 151 Digital Logic Design, Spring Quarter 2007, Midterm Page 10

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