DOD, VHSIC ~1986, IEEE stnd 1987 Widely used (competition Verilog) Commercial VHDL Simulators, Synthesizers, Analyzers,etc Student texts with CDROMs

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1 DOD, VHSIC ~1986, IEEE stnd 1987 Widely used (competition Verilog) Commercial VHDL Simulators, Synthesizers, Analyzers,etc Student texts with CDROMs

2 Entity Architecture Blocks CAE Symbol CAE Schematic Schematic Sheets Component instantiation Behaviorally model function VHDL executes in parallel Processes within architectures (statements in processes execute sequentially)

3 Heavily typed language Parallel execution Type of object: Set of values it can take & operations. CONCURRENT signal assignment Control, selection among Sequential statements in Processes alternative courses of action Composite data types Arrays, records Subprograms Packages, Use Functions, procedures Design unit whose items can be referred to by other designs

4 library ieee; A 9 valued logic system W weak unknown U uninitialized X unknown - don t care 0 low L weak low 1 high H weak high Z high impedance Import all the names in Package std_logic_1164 in library ieee Type, subtypes, resolutions defined. Logic and other functions and,not,nand,or,nor,xor,type conversions,edge functions

5 library ieee; entity fdcr is port ( ); end fdcr; architecture fdcr of fdcr is Q : out std_logic; D, C, CE, R : in std_logic process(c) if (C'event and C = '1') then if (R = '1') then Q <= '0'; else if (CE = '1') then Q <= D; end if; end if ; end if; end process; end fdcr; D R CE C Q

6 library ieee; entity or3 is port(a,b,c : IN STD_LOGIC; d : OUT std_logic); end or3; architecture synth of or3 is d<= a OR b OR c; end synth;

7 library ieee; entity fdcr is port ( Q : out std_logic; D, C, CE, R : in std_logic ); end fdcr; architecture fdcr of fdcr is process(c) if (C'event and C = '1') then Beginning of FileA.vhd if (R = '1') then Q <= '0'; else if (CE = '1') then Q <= D; end if; end if ; end if; end process; end fdcr;

8 ... FileA.vhd continued library ieee; entity datadelay is port(clk,r,en: IN std_logic; din: IN std_logic_vector(7 downto 0); dout : OUT std_logic_vector(7 downto 0)); end datadelay; architecture synth of datadelay is component fdcr port(q:out std_logic; d,c,ce,r: in std_logic ); end component; signal q1,q2: std_logic_vector(7 downto 0); signal one: std_logic;

9 FileA.vhd the end one<= (not r); DDelay: for i in 7 downto 0 generate r1: fdcr port map (q1(i),din(i),clk,one,r); r2: fdcr port map (q2(i),q1(i),clk,one,r); end generate; dout <= q1 when en = '1' else q2; end synth;

10 Beginning of addera.vhd library ieee; entity fulladd is port (a,b,ci: IN STD_LOGIC ; s,co: out STD_LOGIC ) ; end fulladd; architecture fulladd of fulladd is s <= ci xor a xor b; co <= (ci and (a or b)) or (a and b); end fulladd; library ieee; entity halfadd is port (a,b : IN STD_LOGIC ; s,co : OUT STD_LOGIC ); end halfadd; architecture halfadd of halfadd is s <= a xor b; co <= a and b; end halfadd;

11 library ieee; entity adder is port (ain : IN std_logic_vector(15 downto 0); sout : OUT std_logic_vector(15 downto 0); clk,reset : IN STD_LOGIC; cout : OUT std_logic ); end adder; architecture adder of adder is component fulladd port ( a,b,ci : in std_logic; s,co : out std_logic); end component; component halfadd port ( a,b : in std_logic; s,co : out std_logic ); end component;... addera.vhd continued

12 signal carry : std_logic_vector(14 downto 0); signal a,b,s : std_logic_vector(15 downto 0); G: for i in 15 downto 0 generate G1: if i=0 generate halfadd0 : halfadd port map (a(0),b(0),s(0),carry(0)); end generate; G2: if i = 15 generate fulladd15 : fulladd port map (a(15),b(15),carry(14),s(15),cout); end generate; G3: if i /=0 and i/=15 generate fulladdi: fulladd port map (a(i),b(i),carry(i-1),s(i),carry(i)); end generate; end generate;... addera.vhd

13 sout <= s; reg_process : process wait until clk'event and clk = '1' ; a <= ain; if reset = '1' then b <= " "; else b <= s; end if; end process; end adder;... addera.vhd...the end

14 entity muxc is port (i0,i1,i2,i3,a,b: IN STD_LOGIC ; q: out STD_LOGIC ) ; end muxc; architecture muxc of muxc is process(i0,i1,i2,i3,a,b) variable muxval:integer; muxval:=0; if (a='1') then muxval:=muxval+1; end if; if(b='1')then muxval:=muxval+2; end if; case muxval is when 0=> q<=i0; when 1=> q<=i1; when 2=> q<=i2; when 3=> q<=i3; when others=> q<='x'; end case; end process; end muxc;

15 Variables values assigned immediately local storage in processes variable results:bit:= 1 ; Signals values are scheduled circuit interconnections signal VDD: bit:= 1 ; (no guarantee of initial values for signals