Instruction Set Overview

Transcription

1 MicroBlaze Instruction Set Overview ECE 3534 Part 1 1

2 The Facts MicroBlaze Soft-core Processor Highly Configurable 32-bit Architecture Master Component for Creating a MicroController Thirty-two 32-bit general purpose registers 32-bit instruction word with three operands and two addressing modes 32-bit address bus Single issue pipeline

3 Overview Organization The MicroBlaze embedded soft core is a reduced instruction set computer (RISC) optimized for implementation in Xilinx field programmable gate arrays (FPGAs). See Figure 1-1 for a block diagram depicting the MicroBlaze core. Instruction-side bus interface Data-side bus interface Program Counter Special Purpose Registers IXCL_S Shift Barrel Shift D-Cache I-Cache IXCL_M DOPB ALU IOPB DXCL_M DXCL_S Multiplier Divider Bus IF ILMB FPU Instruction Buffer Bus IF DLMB Instruction Decode Register File 32 X 32b MFSL 0..7 SFSL 0..7 Optional MicroBlaze feature Figure 1-1: MicroBlaze Core Block Diagram Features The MicroBlaze embedded soft core is highly configurable, allowing users to select a specific set of features required by their design. The processor s fixed feature set includes

4 Major Components Harvard Architecture R Chapter 2: MicroBlaze Signal Interface Description Bus Interfaces IXCL_M Special Purpose Registers IXCL_S DXCL_M DXCL_S Divider Bus IF FPU Instruction Buffer Special Function Instruction Processing Shift Barrel Shift Multiplier ILMB ALU DOPB ALU Program Counter D-Cache General Purpose Data-side bus interface IOPB I-Cache Registers Instruction-side bus interface Bus IF DLMB Instruction Decode Register File 32 X 32b MFSL 0..7 SFSL 0..7 Optional MicroBlaze feature Figure 2-1: MicroBlaze Core Block Diagram Table 2-1: Summary of MicroBlaze Core I/O Signal Interface I/O DM_ABus[0:31] DOPB O Data interface OPB address bus Description DM_BE[0:3] DOPB O Data interface OPB byte enables DM_busLock DOPB O Data interface OPB bus lock DM_DBus[0:31] DOPB O Data interface OPB write data bus DM_request DOPB O Data interface OPB bus request DM_RNW DOPB O Data interface OPB read, not write

5 Harvard Architecture See Harvard Architecture

6 Princeton Architecture

7 Microcontroller Attributes (1/3) Attribute Instruction / data ports Option 1 Option 2 Separate ( Harvard ) Unified ( Princeton ) Data memory read/ write operations Only by load/store instructions ( RISC ) Any instruction can read/write memory ( CISC ) External input/ output Use load/store instructions ( memory-mapped ) Special I/O instructions See Harvard Architecture See RISC and CISC See Memory Mapped I/O 7

8 Microcontroller Attributes (2/3) Attribute Option 1 Option 2 Pipeline depth Classic 3-stage (fetch/ decode/execute) Classic 5-stage (fetch/ decode/execute/ access/writeback) Word size (instructions, integers, addresses) 16-bit 32-bit Memory organization Byte-addressable Word-addressable See Pipeline See Word Size See Byte Addressable 8

9 Microcontroller Attributes (3/3) Attribute Option 1 Option 2 Byte order within words Big-endian Little-endian # of instruction operands Two operand (rd rd op rs) Three operand (rd ra op rb) Addressing modes Few (RISC) Many (CISC) See Endianness See Addressing Modes 9

10 Simplified MicroBlaze Architecture Overview The MicroBlaze embedded soft core is a reduced instruction set computer (RISC) optimized for implementation in Xilinx field programmable gate arrays (FPGAs). See Figure 1-1 for a block diagram depicting the MicroBlaze core. Instruction-side bus interface Data-side bus interface Program Counter Special Purpose Registers IXCL_S Shift Barrel Shift D-Cache I-Cache IXCL_M DOPB ALU IOPB DXCL_M DXCL_S Multiplier Divider Bus IF ILMB FPU Instruction Buffer Bus IF DLMB Instruction Decode Register File 32 X 32b MFSL 0..7 SFSL 0..7 Optional MicroBlaze feature Which of the preceding processor Figure 1-1: MicroBlaze Core Block Diagram attributes may be inferred from this block Features The MicroBlaze embedded soft core is highly configurable, allowing users to select a diagram? 10 specific set of features required by their design. The processor s fixed feature set includes

11 Simplified MicroBlaze Architecture croblaze Architecture iew The MicroBlaze embedded soft core is a reduced instruction set computer (RISC) optimized for implementation in Xilinx field programmable gate arrays (FPGAs). See Figure 1-1 for a block diagram depicting the MicroBlaze core. Instruction-side bus interface Data-side bus interface Program Counter Special Purpose Registers _S Shift Barrel Shift D-Cache I-Cache _M DOPB ALU IOPB DXCL_M DXCL_S Multiplier Divider FPU Bus IF Instruction Buffer ILMB Bus IF RISC DLMB Load/Store Architecture Instruction Decode Register File 32 X 32b Harvard Architecture MFSL 0..7 SFSL 0..7 Optional MicroBlaze feature Figure 1-1: MicroBlaze Core Block Diagram Features ANSWERS 3 or 5 Stage Pipeline (currently 5) 32-bit Datapaths The MicroBlaze embedded soft core is highly configurable, allowing users to select a specific set of features required by their design. The processor s fixed feature set includes the following: Thirty-two 32-bit general purpose registers 32-bit instruction word with three operands and two addressing modes 32-bit address bus Single issue pipeline Processor Reference Guide 3) October 5, 2005 Byte Addressable Big Endian Two Addressing Modes or 3 Operand Instructions

12 Advanced Processor Attributes Superscalar Speculative, out-of-order execution Branch prediction Multi-threaded These techniques improve performance, but increase power consumption For more info, click on the above links and/or take an advanced computer 12 architecture course

13 MicroBlaze Native Data Types 1/3 32-bit word Address: n n+1 n+2 Alignment: n should be a multiple of 4 Bit labeling: [0...31] Byte significance: [most,,,least] n+3 Big-endian Example: 0x Viewed as a 32-bit word at address n 0x12 0x34 (4 bytes) 0x56 0x78 Viewed as a sequence of 4 bytes starting at address n 13

14 MicroBlaze Native Data Types 2/3 16-bit word n Address: Alignment: n+1 (2 bytes) n should be a multiple of 2 Bit labeling: [0..15] Byte significance: [most, least] Example: 0x2468 Viewed as a 16-bit word at address n 0x24 Big-endian 0x68 Viewed as a sequence of 2 bytes starting at address n 14

15 MicroBlaze Native Data Types 3/3 8-bit word n Address: Alignment: Bit significance: (1 byte) none most least Bit labeling: [0 7] Example: 0x13 15

16 MicroBlaze Instruction Set ~ 124 instructions 2 addressing modes Type A 22 integer arithmetic 8 logical Up to 2 source registers 1 destination register 9 shift Type B 36 branch 1 source register 1 immediate operand 11 floating point 16-bit or 32-bit constant 12 load/store 1 destination register 4 return 22 other 16

17 Type A Instructions Opcode Bit: 0 Destination reg Source reg A 6 11 Source reg B Example: Add contents of r24 and r27, and store the sum in register r25 Assembly language: add r25, r24, r27 Machine code:

18 Does Not Add Up 6-bit opcode => 64 instructions How are the other 60 instructions distinguished? 18

19 Dealing Efficiently with Constants Occurrence

20 Questions 1. Why is it important for an embedded processor to deal efficiently with constants? 2. How should we optimize using 0? 3. Should we make a special case of n-bit constants, where n < 32? 4. What if we need a 32-bit constant? 20