CPE 626 Advanced VLSI Design Lecture 7: VHDL Synthesis

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1 CPE 626 Lecture 7 VHDL Synthes Aleksar Milenkovic http// http// milenka@ece.uah.edu Asstant Pressor Electrical Computer Engineering Dept. University Alabama in Huntsville Design Flow Overview A. Milenkovic 2

2 Schematic Capture RTL code Carefully Select Design Hierarchy Architectural Wizards (Clocking, RocketIO) Core Generator A. Milenkovic 3 Core Generator Design tool that delivers parameterized cores optimized for Xilinx FPGAs E.g., adders, multipliers, filters, FIFOs, memories Core Generator outputs *.EDN file > EDIF (Electronic Data Interchange Format) netlt file; it includes information required to implement the module in a Xilinx FPGA *.VHO > VHDL template file; used as a model for instantiating a module in a VHDL design *.VHD > VHDL wrapper file; provides support for functional simulation A. Milenkovic 4

3 Functional Simulation Very the syntax functionality Separate simulation for each module > easier to debug When each module behaves as expected, create a test bench for entire design A. Milenkovic 5 Coding for Synthes A. Milenkovic 6

4 Avoid Ports Declared as Buffers Entity alu port( A in STD_LOGIC_VECTOR(3 B in STD_LOGIC_VECTOR(3 CLK in STD_LOGIC; C out STD_LOGIC_VECTOR(3 0) ); alu; architecture BEHAVIORAL alu -- dummy C_INT STD_LOGIC_VECTOR(3 C C_INT; process (CLK event CLK 1 ) C_INT < UNSIGNED(A) + UNSIGNED(B) + UNSIGNED(C_INT); process; BEHAVIORAL; Entity alu port( A in STD_LOGIC_VECTOR(3 B in STD_LOGIC_VECTOR(3 CLK in STD_LOGIC; C buffer STD_LOGIC_VECTOR(3 0) ); alu; architecture BEHAVIORAL alu process (CLK event CLK 1 ) C UNSIGNED(A) + UNSIGNED(B) UNSIGNED(C); process; BEHAVIORAL; A. Milenkovic 7 Signals vs. Variables for Synthes -- XOR_VAR.VHD Library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity xor_var port ( A, B, C in STD_LOGIC; X, Y out STD_LOGIC ); xor_var; architecture VAR_ARCH xor_var VARprocess (A,B,C) variable D STD_LOGIC; D A; X C xor D; D B; Y C xor D; process; VAR_ARCH; A. Milenkovic 8

5 Signals vs. Variables for Synthes -- XOR_SIG.VHD Library IEEE; use IEEE.std_logic_1164.all; entity xor_sig port ( A, B, C in STD_LOGIC; X, Y out STD_LOGIC ); xor_sig; architecture SIG_ARCH xor_sig D STD_LOGIC; SIGprocess (A,B,C) D A; -- ignored!! X C xor D; D B; -- overrides!! Y C xor D; process; SIG_ARCH; A. Milenkovic 9 Guidelines for synthes VHDL/Verilog are not originally planned as languages for synthes Many HDL simulation constructs are not supported in synthes Omit wait for XX statements Omit delay statements after XX; Omit initial values Order grouping arithmetic statement can influence synthes A. Milenkovic 10

6 If Statement vs. Case Statement If statement generally produces priorityencoded logic can contain a set dferent expressions Case statement generally creates balanced logic evaluated against a common controlling expression In general, use the Case statement for complex decoding use the If statement for speed critical paths A. Milenkovic 11 MUX 4-1 Synthes -- IF_EX.VHD library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity _ex port ( SEL in STD_LOGIC_VECTOR(1 A,B,C,D in STD_LOGIC; MUX_OUT out STD_LOGIC); _ex; architecture BEHAV _ex IF_PRO process (SEL,A,B,C,D) (SEL 00 ) MUX_OUT A; els (SEL 01 ) MUX_OUT B; els (SEL 10 ) MUX_OUT C; els (SEL 11 ) MUX_OUT D; else MUX_OUT '0'; process; --END IF_PRO BEHAV; -- CASE_EX.VHD library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity case_ex port ( SEL in STD_LOGIC_VECTOR(1 A,B,C,D in STD_LOGIC; MUX_OUT out STD_LOGIC); case_ex; architecture BEHAV case_ex CASE_PRO process (SEL,A,B,C,D) case SEL when 00 > MUX_OUT A; when 01 > MUX_OUT B; when 10 > MUX_OUT C; when 11 > MUX_OUT D; when others > MUX_OUT '0'; case; process; --End CASE_PRO BEHAV; A. Milenkovic 12

7 MUX 4-1 Implementation A. Milenkovic 13 Resource Sharing An optimization that uses a single functional block (adder, multiplier, shter, ) to implement several HDL operators Pros less gates, simpler routing Cons adds extra logic levels > increase delay (avoid sharing on the critical path) A. Milenkovic 14

8 Resource Sharing VHDL Example -- RES_SHARING.VHD library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; use IEEE.std_logic_arith.all; entity res_sharing port ( A1,B1,C1,D1 in STD_LOGIC_VECTOR (7 COND_1 in STD_LOGIC; Z1 out STD_LOGIC_VECTOR (7 0)); res_sharing; architecture BEHAV res_sharing P1 process (A1,B1,C1,D1,COND_1) (COND_1 1 ) Z1 A1 + B1; else Z1 C1 + D1; process; -- P1 BEHAV; A. Milenkovic 15 Implementation W/WO Resource Sharing Enabled Dabled A. Milenkovic 16

9 Regters Asynchronous Preset/Set -- FF_EXAMPLE.VHD -- Example Implementing Regters library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity ff_example port ( RESET, SET, CLOCK, ENABLE in STD_LOGIC; D_IN in STD_LOGIC_VECTOR (7 A_Q_OUT out STD_LOGIC_VECTOR (7 B_Q_OUT out STD_LOGIC_VECTOR (7 C_Q_OUT out STD_LOGIC_VECTOR (7 D_Q_OUT out STD_LOGIC_VECTOR (7 E_Q_OUT out STD_LOGIC_VECTOR (7 0)); ff_example; architecture BEHAV ff_example -- D flip-flop FF process (CLOCK) (CLOCK event CLOCK 1 ) A_Q_OUT D_IN; process; -- End FF -- Flip-flop with asynchronous reset FF_ASYNC_RESET process (RESET, CLOCK) (RESET 1 ) B_Q_OUT ; els (CLOCK'event CLOCK B_Q_OUT D_IN; -- Flip-flop with asynchronous set FF_ASYNC_SET process (SET, CLOCK) (SET C_Q_OUT ; els (CLOCK'event CLOCK C_Q_OUT D_IN; process; -- End FF_ASYNC_SET A. Milenkovic 17 Regters Asynchronous Preset/Set -- Flip-flop with asynchronous reset -- clock enable FF_CLOCK_ENABLE process (ENABLE, RESET, CLOCK) (RESET 1 ) D_Q_OUT ; els (CLOCK'event CLOCK (ENABLE D_Q_OUT D_IN; process; -- End FF_CLOCK_ENABLE Flip-flop Flip-flop with with asynchronous asynchronous reset reset asynchronous asynchronous set set clock clock enable enable FF_ASR_CLOCK_ENABLE FF_ASR_CLOCK_ENABLE process process (ENABLE, (ENABLE, RESET, RESET, SET, SET, CLOCK) CLOCK) (RESET (RESET E_Q_OUT E_Q_OUT " "; " "; els els (SET (SET E_Q_OUT E_Q_OUT " "; " "; els els (CLOCK'event (CLOCK'event CLOCK CLOCK (ENABLE (ENABLE E_Q_OUT E_Q_OUT D_IN; D_IN; process; process; End End FF_ASR_CLOCK_ENABLE FF_ASR_CLOCK_ENABLE BEHAV; BEHAV; A. Milenkovic 18

10 Use Clock_Enable instead gated Clock -- Better implementation to use clock enable rather than gated clock library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity gate_clock port (IN1,IN2,DATA,CLK,LOAD in STD_LOGIC; OUT1 out STD_LOGIC); gate_clock; architecture BEHAVIORAL gate_clock GATECLK STD_LOGIC; GATECLK (IN1 IN2 CLK); GATE_PR process (GATECLK,DATA,LOAD) (GATECLK event GATECLK 1 ) (LOAD 1 ) OUT1 DATA; process; -- End GATE_PR BEHAVIORAL; Th implementation introduces Glitches Clock delays Clock skew A. Milenkovic 19 Use Clock Enable Instead Gated Clocks -- CLOCK_ENABLE.VHD library IEEE; use IEEE.std_logic_1164.all; use IEEE.std_logic_unsigned.all; entity clock_enable port (IN1,IN2,DATA,CLOCK,LOAD in STD_LOGIC; DOUT out STD_LOGIC); clock_enable; architecture BEHAV clock_enable ENABLE STD_LOGIC; ENABLE IN1 IN2 LOAD; EN_PR process (ENABLE,DATA,CLOCK) (CLOCK event CLOCK 1 ) (ENABLE 1 ) DOUT DATA; process; -- End EN_PR BEHAV; A. Milenkovic 20

11 HDL Coding Techniques for Common Building Blocks Multiplication in FPGAs http// A. Milenkovic 22

12 Multiplier library ieee; use ieee.std_logic_1164.all; use ieee.std_logic_unsigned.all; entity mult port( ); mult; A in std_logic_vector(17 B in std_logic_vector(17 RES out std_logic_vector(35 0) architecture archi mult RES A * B; archi; Device utilization summary Selected Device 3s50tq144-5 Number Slices 19 out 768 2% Number 4 input LUTs 36 out % Number bonded IOBs 72 out 97 74% Number MULT18X18s 3 out 4 75% Delay ns (Levels Logic 25) A. Milenkovic 23 Inferring Pipelined Multiplier library IEEE; use IEEE.STD_LOGIC_1164.ALL; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity multpipe generic( A_port_size integer 18; B_port_size integer 18 ); port( clk in std_logic; A in unsigned (A_port_size-1 B in unsigned (B_port_size-1 MULT out unsigned ( (A_port_size+B_port_size-1) 0)); multpipe; A. Milenkovic 24

13 Inferring Pipelined Multiplier (cont d) architecture architecture Behavioral Behavioral multpipe multpipe a_in, a_in, b_in b_in unsigned unsigned (A_port_size-1 (A_port_size-1 mult_res mult_res unsigned unsigned ( ( (A_port_size+B_port_size-1) (A_port_size+B_port_size-1) pipe_1, pipe_1, pipe_2, pipe_2, pipe_3 pipe_3 unsigned unsigned ((A_port_size+B_port_size-1) ((A_port_size+B_port_size-1) mult_res mult_res a_in a_in * * b_in; b_in; process process (clk) (clk) (clk'event (clk'event clk clk a_in a_in A; A; b_in b_in B; B; pipe_1 pipe_1 mult_res; mult_res; pipe_2 pipe_2 pipe_1; pipe_1; pipe_3 pipe_3 pipe_2; pipe_2; MULT MULT pipe_3; pipe_3; process; process; Behavioral; Behavioral; > Four pipeline stages A. Milenkovic 25 Pipelined Multiplier RTL Schematic Device utilization summary Selected Device 3s50tq144-5 Number Slices 60 out 768 7% Number Slice Flip Flops 72 out % Number 4 input LUTs 72 out % Number bonded IOBs 72 out 97 74% Number MULT18X18s 3 out 4 75% Number GCLKs 1 out 8 12% Delay 9.824ns (Levels Logic 23) A. Milenkovic 26

14 Inferring PM Alternative Description #1 architecture beh beh mult mult a_in, a_in, b_in b_in unsigned unsigned (A_port_size-1 mult_res mult_res unsigned unsigned ((A_port_size+B_port_size-1) pipe_2, pipe_2, pipe_3 pipe_3 unsigned unsigned ((A_port_size+B_port_size-1) process process (clk) (clk) (clk event (clk event clk 1 ) a_in a_in A; A; b_in b_in B; B; mult_res a_in a_in * b_in; b_in; pipe_2 pipe_2 mult_res; mult_res; pipe_3 pipe_3 pipe_2; pipe_2; MULT MULT pipe_3; pipe_3; process; process; beh; A. Milenkovic 27 Inferring PM Alternative Description #2 architecture beh beh mult mult a_in, a_in, b_in b_in unsigned unsigned (A_port_size-1 mult_res mult_res unsigned unsigned ((A_port_size+B_port_size-1) type type pipe_reg_type array array (2 (2 0) 0) unsigned unsigned ((A_port_size+B_port_size-1) pipe_regs pipe_regs pipe_reg_type; mult_res mult_res a_in a_in * b_in; b_in; process process (clk) (clk) (clk event (clk event clk 1 ) a_in a_in A; A; b_in b_in B; B; pipe_regs pipe_regs mult_res mult_res & pipe_regs(2 1); 1); MULT MULT pipe_regs( process; process; beh; A. Milenkovic 28

15 RAMs/ROMs XST fers an automatic RAM recognition Keep you HDL code technology indepent XST can infer dtributed or Block RAM Parameters Synchronous write, Write enable, RAM enable, Asynchronous or synchronous read, Reset the data output latches, Data output reset, Single, dual or multiple-port read, Single-port write A. Milenkovic 29 Dual-port Block RAM -- --Only XST XST supports supports RAM RAM inference inference -- --Infers Dual Dual Port Port Block Block Ram Ram entity entitydpblockram dpblockram port port (clk (clk in in std_logic; std_logic; we we in in std_logic; std_logic; a in in std_logic_vector(4 dpra dpra in in std_logic_vector(4 di di in in std_logic_vector(3 spo spo out out std_logic_vector(3 dpo dpo out out std_logic_vector(3 0)); dpblockram; A. Milenkovic 30

16 Dual-port Block RAM architecture architecture syn syn dpblockram dpblockram type type ram_type ram_type array array (31 (31 0) 0) std_logic_vector std_logic_vector (3 (3 RAM RAM ram_type; ram_type; read_a read_a std_logic_vector(4 std_logic_vector(4 read_dpra read_dpra std_logic_vector(4 std_logic_vector(4 process process (clk) (clk) (clk'event (clk'event clk clk (we (we RAM(conv_integer(a)) RAM(conv_integer(a)) di; di; read_a read_a a; a; read_dpra read_dpra dpra; dpra; process; process; spo spo RAM(conv_integer(read_a)); RAM(conv_integer(read_a)); dpo dpo RAM(conv_integer(read_dpra)); RAM(conv_integer(read_dpra)); syn; syn; A. Milenkovic 31 Dual-port Dtributed RAM entity entitydpdtram dpdtram port port (clk (clk in in std_logic; std_logic; we we in in std_logic; std_logic; a in in std_logic_vector(4 dpra dpra in in std_logic_vector(4 di di in in std_logic_vector(3 spo spo out out std_logic_vector(3 dpo dpo out out std_logic_vector(3 0)); dpdtram; dpdtram; A. Milenkovic 32

17 Dual-port Dtributed RAM architecture architecture syn syn dpdtram dpdtram type type ram_type ram_type array array (31 (31 0) 0) std_logic_vector std_logic_vector (3 (3 RAM RAM ram_type; ram_type; process process (clk) (clk) (clk'event (clk'event clk clk (we (we RAM(conv_integer(a)) RAM(conv_integer(a)) di; di; process; process; spo spo RAM(conv_integer(a)); RAM(conv_integer(a)); dpo dpo RAM(conv_integer(dpra)); RAM(conv_integer(dpra)); syn; syn; A. Milenkovic 33 Dual-port RAM with Enable on Each Port Write VHDL description. A. Milenkovic 34

CPE 626 Advanced VLSI Design Lecture 6: VHDL Synthesis. Register File: An Example. Register File: An Example (cont d) Aleksandar Milenkovic

CPE 626 Advanced VLSI Design Lecture 6: VHDL Synthesis. Register File: An Example. Register File: An Example (cont d) Aleksandar Milenkovic CPE 626 Lecture 6: VHDL Synthesis Aleksandar Milenkovic http://www.ece.uah.edu/~milenka http://www.ece.uah.edu/~milenka/cpe626-04f/ milenka@ece.uah.edu Assistant Professor Electrical and Computer Engineering