Based on slides/material by. Topic 7-4. Memory and Array Circuits. Outline. Semiconductor Memory Classification

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1 Based on slides/material by Topic 7 Memory and Array Circuits K. Masselos J. Rabaey Digital Integrated Circuits: A Design Perspective, Prentice Hall D. Harris Weste and Harris, CMOS VLSI Design: A Circuits and Systems Perspective, Addison Wesley Peter Y. K. Cheung Department of Electrical & Electronic Engineering Imperial College London Recommended Reading: J. Rabaey et. al. Digital Integrated Circuits: A Design Perspective : Chapter 12 URL: Weste and Harris, CMOS VLSI Design: A Circuits and Systems Perspective : Chapter 11 Topic 7-1 Topic 7-2 Outline Semiconductor Memory Classification Memory classification Basic building blocks RWM NVRWM Non Volatile Read Write Memories Static RAM (SRAM) Dynamic RAM (DRAM) Memory peripheral circuit Random Access Non-Random Access EP E 2 P Mask-Programmed Programmable (P) Content Addressable Memory (CAM) Serial access memories Reliability and Yield Memory trends SRAM DRAM FIFO LIFO Shift Register CAM FLASH Topic 7-3 Topic 7-4

2 Memory Arrays Outline Static RAM (SRAM) Mask Read/Write Memory (RAM) (Volatile) Memory Arrays Random Access Memory Serial Access Memory Content Addressable Memory (CAM) Dynamic RAM (DRAM) Programmable (P) Read Only Memory () (Nonvolatile) Erasable Programmable (EP) Serial In Parallel Out (SIPO) Shift Registers Parallel In Serial Out (PISO) Electrically Erasable Programmable (EEP) Queues Flash First In First Out (FIFO) Last In First Out (LIFO) Memory classification Basic building blocks Non Volatile Read Write Memories Static RAM (SRAM) Dynamic RAM (DRAM) Memory peripheral circuit Content Addressable Memory (CAM) Serial access memories Reliability and Yield Memory trends Topic 7-5 Topic 7-6 Memory Architecture: Decoders Array-Structured Memory Architecture N Words S 0 S 1 S 2 S N-2 S N_1 M bits Word 0 Word 1 Word 2 Word N-2 Word N-1 Storage Cell A 0 A 1 A K-1 Decoder S 0 M bits Word 0 Word 1 Word 2 Word N-2 Word N-1 Storage Cell A K A K+1 A L-1 Problem: ASPECT RATIO or HEIGHT >> WIDTH Row Decoder 2 L-K Bit Line Sense Amplifiers / Drivers Word Line M.2 K Storage Cell Amplify swing to rail-to-rail amplitude Input-Output (M bits) N words => N select signals Too many select signals Input-Output (M bits) Decoder reduces # of select signals K = log 2 N A 0 A K-1 Column Decoder Input-Output (M bits) Selects appropriate word Topic 7-7 Topic 7-8

3 Hierarchical Memory Architecture Memory Timing: Definitions Row Address Read Cycle Column Address READ Block Address WRITE Read Access Read Access Write Cycle Control Circuitry Block Selector Global Amplifier/Driver Global Data Bus DATA Data Valid Write Access I/O Advantages: 1. Shorter wires within blocks 2. Block address activates only 1 block => power savings Data Written Topic 7-9 Topic 7-10 Memory Timing: Approaches Outline Address Bus RAS CAS MSB Row Address LSB Column Address RAS-CAS timing DRAM Timing Multiplexed Adressing Address Bus Address Address transition initiates memory operation SRAM Timing Self-timed Memory classification Basic building blocks Non Volatile Read Write Memories Static RAM (SRAM) Dynamic RAM (DRAM) Memory peripheral circuit Content Addressable Memory (CAM) Serial access memories Reliability and Yield Memory trends Topic 7-11 Topic 7-12

4 Read-Only Memories Example Read-Only Memories are nonvolatile Retain their contents when power is removed Mask-programmed s use one transistor per bit Presence or absence determines 1 or 0 A1 A0 4-word x 6-bit Represented with dot diagram Dots indicate 1 s in weak pseudo-nmos pullups Word 0: Word 1: Word 2: Word 3: :4 DEC Array Y5 Y4 Y3 Y2 Y1 Y0 Looks like 6 4-input pseudo-nmos NORs Topic 7-13 Topic 7-14 MOS NOR MOS NOR Layout Metal1 on top of diffusion Pull-up devices WL[0] (diffusion) WL[0] WL[1] WL[1] Basic cell 10 λ x 7 λ WL[2] Polysilicon Metal1 2 λ WL[2] WL[3] WL[3] [0] [1] [2] [3] Only 1 layer (contact mask) is used to program memory array Programming of the memory can be delayed to one of last process steps Topic 7-15 Topic 7-16

5 MOS NOR Layout MOS NAND [0] [1] [2] [3] Threshold raising implant Pull-up devices WL[0] Basic Cell 8.5 λ x 7 λ WL[1] (diffusion) Metal1 over diffusion WL[0] [0] [1] [2] [3] Polysilicon WL[1] WL[2] WL[2] WL[3] WL[3] Threshold raising implants disable transistors All word lines high by default with exception of selected row Topic 7-17 Topic 7-18 MOS NAND Layout Precharged MOS NOR Diffusion φpre Precharge devices Polysilicon Basic cell 5 λ x 6 λ WL[0] WL[1] Threshold lowering implant WL[2] WL[3] No contact to VDD or necessary; drastically reduced cell size Loss in performance compared to NOR [0] [1] [2] [3] PMOS precharge device can be made as large as necessary, but clock driver becomes harder to design. Topic 7-19 Topic 7-20

6 Building Logic with s Outline Use as lookup table containing truth table n inputs, k outputs requires 2 n words x k bits Changing function is easy reprogram Finite State Machine n inputs, k outputs, s bits of state Build with 2 n+s x (k+s) bit and (k+s) bit reg inputs n DEC 2 n wordlines Array k outputs inputs n k s state outputs k s Memory classification Basic building blocks Non Volatile Read Write Memories Static RAM (SRAM) Dynamic RAM (DRAM) Memory peripheral circuit Content Addressable Memory (CAM) Serial access memories Reliability and Yield Memory trends Topic 7-21 Topic 7-22 Nonvolatile Read-Write Memories (NVRW) Ps and EPs Architecture virtually identical to the structure the memory core consists of an array of transistors placed on a word-line/bitline grid The memory is programmed by selectively disabling or enabling some of those devices in a this is accomplished by mask level alterations in a NVRW memory a modified transistor that permits its threshold to be altered electrically is used instead the modified threshold is retained indefinitely (or long) even when the supply voltage is turned off To reprogram the memory the programmed values must be erased after which a new programming round can be started The method of erasing is the main differentiating factor between the various classes of reprogrammable non volatile memories The programming of the memory is typically an order of magnitude slower than the reading operation Programmable s Build array with transistors at every site Burn out fuses to disable unwanted transistors Electrically Programmable s Use floating gate to turn off unwanted transistors EP, EEP, Flash Source n+ Gate p Drain n+ bulk Si Polysilicon Floating Gate Thin Gate Oxide (SiO 2) Topic 7-23 Topic 7-24

7 Floating-gate transistor (FAMOS) Floating-Gate Transistor Programming Source Floating gate Gate Drain D 20 V 0 V 5 V t ox G 20 V 10 V 5 V 5 V 0 V 2.5 V 5 V n + Substrate p t ox n + S S D S D S D (a) Device cross-section (b) Schematic symbol Avalanche injection. Removing programming voltage leaves charge trapped. Programming results in higher V T. Topic 7-25 Topic 7-26 Characteristics of Non Volatile Memories Outline Memory classification Basic building blocks Non Volatile Read Write Memories Static RAM (SRAM) Dynamic RAM (DRAM) Memory peripheral circuit Content Addressable Memory (CAM) Serial access memories Reliability and Yield Memory trends Topic 7-27 Topic 7-28

8 Read-Write Memories (RAM) 6-transistor CMOS SRAM Cell STATIC (SRAM) WL Data stored as long as supply is applied Large (6 transistors/cell) Fast Differential M5 Q M2 M4 Q M6 DYNAMIC (DRAM) M1 M3 Periodic refresh required Small (1-3 transistors/cell) Slower Single Ended Topic 7-29 Topic 7-30 SRAM Read/Write CMOS SRAM Analysis (Read) Precharge both bitlines high Then turn on wordline One of the two bitlines will be pulled down by the cell word Ex: A = 0, A_b = 1 bit discharges, bit_b stays high But A bumps up slightly Read stability A_b bit_b A must not flip 1.5 N1 >> N2 bit N2 A P1 N1 P2 N3 A_b bit_b N4 1.0 word bit 0.5 A time (ps) Topic 7-31 Topic 7-32

CMOS SRAM Analysis (Write) SRAM Sizing Drive one bitline high, the other low Then turn on wordline Bitlines overpower cell with new value Ex: A = 0, A_b = 1, bit = 1, bit_b = 0 Force A_b low, then A

9 CMOS SRAM Analysis (Write) SRAM Sizing Drive one bitline high, the other low Then turn on wordline Bitlines overpower cell with new value Ex: A = 0, A_b = 1, bit = 1, bit_b = 0 Force A_b low, then A rises high Writability Must overpower feedback inverter N2 >> P1 word bit N2 P1 P2 A N1 N3 A_b 1.5 A bit_b 1.0 A_b bit_b N4 High bitlines must not overpower inverters during reads But low bitlines must write new value into cell bit bit_b word weak med med A A_b strong 0.5 word time (ps) Topic 7-33 Topic T-SRAM Layout Resistance-load SRAM Cell WL M2 M4 R L R L M3 Q Q M4 Q Q M1 M2 M1 M3 M5 M6 WL Static power dissipation -- Want R L large Bit lines precharged to to address t p problem Topic 7-35 Topic 7-36

10 Multiple Ports Dual-Ported SRAM We have considered single-ported SRAM One read or one write on each cycle Multiported SRAM are needed for register files Examples: Multicycle MIPS must read two sources or write a result on some cycles Pipelined MIPS must read two sources and write a third result each cycle Superscalar MIPS must read and write many sources and results each cycle Simple dual-ported SRAM Two independent single-ended reads Or one differential write Do two reads and one write by time multiplexing Read during ph1, write during ph2 Topic 7-37 Topic 7-38 True dual port SRAM Multi-Ported SRAM Adding more access transistors hurts read stability Multiported SRAM isolates reads from state node Single-ended design minimizes number of bitlines Topic 7-39 Topic 7-40

Outline 3-Transistor DRAM Cell Memory classification Basic building blocks Non Volatile Read Write Memories Static RAM (SRAM) Dynamic RAM (DRAM) Memory peripheral circuit Content Addressable Memory

11 Outline 3-Transistor DRAM Cell Memory classification Basic building blocks Non Volatile Read Write Memories Static RAM (SRAM) Dynamic RAM (DRAM) Memory peripheral circuit Content Addressable Memory (CAM) Serial access memories Reliability and Yield Memory trends WWL RWL 1 M1 C S X M3 M2 2 WWL RWL X 1 2 -V T No constraints on device ratios Reads are non-destructive Value stored at node X when writing a 1 = V WWL -V Tn -V T ΔV Topic 7-41 Topic T-DRAM Layout 1-Transistor DRAM Cell WL WL Write "1" Read "1" M1 C S X V T C /2 sensing /2 Write: C S is charged or discharged by asserting WL and. Read: Charge redistribution takes places between bit line and storage capacitance C S Δ V = V V PRE = ( V BIT V PRE ) C S + C Voltage swing is small; typically around 250 mv. Topic 7-43 Topic 7-44

DRAM Cell Observations 1-T DRAM Cell 1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out. DRAM memory cells are single ended in contrast to SRAM cells.

Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design. When writing a 1 into a DRAM cell, a threshold voltage is lost.

Metal word line n + poly n + poly Inversion layer induced by plate bias (a) Cross-section SiO 2 Field Oxide Diffused bit line Polysilicon gate Capacitor Polysilicon plate M1 word line (b) Layout Used

12 DRAM Cell Observations 1-T DRAM Cell 1T DRAM requires a sense amplifier for each bit line, due to charge redistribution read-out. DRAM memory cells are single ended in contrast to SRAM cells. The read-out of the 1T DRAM cell is destructive; read and refresh operations are necessary for correct operation. Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be explicitly included in the design. When writing a 1 into a DRAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than. Metal word line n + poly n + poly Inversion layer induced by plate bias (a) Cross-section SiO 2 Field Oxide Diffused bit line Polysilicon gate Capacitor Polysilicon plate M1 word line (b) Layout Used Polysilicon-Diffusion Capacitance Expensive in Area Topic 7-45 Topic 7-46 Advanced 1T DRAM Cells Outline Cell Plate Si Capacitor Insulator Storage Node Poly 2nd Field Oxide Refilling Poly Si Substrate Word line Insulating Layer Cell plate Transfer gate Isolation Storage electrode Capacitor dielectric layer Memory classification Basic building blocks Non Volatile Read Write Memories Static RAM (SRAM) Dynamic RAM (DRAM) Memory peripheral circuit Content Addressable Memory (CAM) Serial access memories Reliability and Yield Memory trends Trench Cell Stacked-capacitor Cell Topic 7-47 Topic 7-48

13 Periphery Row Decoders Decoders Sense amplifiers Input/output buffers Collection of 2 M complex logic gates Organized in regular and dense fashion (N)AND Decoder Control/timing circuit NOR Decoder Topic 7-49 Topic 7-50 A NAND Decoder using 2-input Pre-Decoders Dynamic Decoders Precharge devices WL 1 WL 3 WL 3 WL 0 WL 2 WL 2 WL 1 WL 1 A 0 A 1 A 0 A 1 A 0 A 1 A 0 A 1 A 2 A 3 A 2 A 3 A 2 A 3 A 2 A 3 WL 0 WL 0 φ A 0 A 0 A 1 A 1 A 0 A 0 A 1 A 1 φ Dynamic 2-to-4 NOR decoder 2-to-4 MOS dynamic NAND Decoder A 1 A 0 A 0 A 1 A 3 A 2 A 2 A 3 Splitting decoder into two or more logic layers produces a faster and cheaper implementation Propagation delay is primary concern Topic 7-51 Topic 7-52

14 4 input Pass-Transistor based Column Decoder 4-to-1 Tree based Column Decoder A 0 A 1 2 inputnordecoder S 0 S 1 S 2 S 3 A 0 A 0 A 1 A 1 D Advantage: speed (t pd does not add to overall memory access time) only 1 extra transistor in signal path Disadvantage: large transistor count D Number of devices drastically reduced Delay increases quadratically with # of sections; prohibitive for large decoders Solutions: buffers progressive sizing combination of tree and pass transistor approaches Topic 7-53 Topic 7-54 Decoder for Circular Shift-Register Sense Amplifiers t p = C ΔV I av make ΔV as small as possible WL 0 WL 1 WL 2 φ φ φ φ R φ φ R φ φ R φ φ φ φ... large Idea: Use Sense Amplifer small transition small s.a. input output Topic 7-55 Topic 7-56

15 Differential Sensing - SRAM Latch-Based Sense Amplifier PC EQ y M3 M4 x M1 M2 SE M5 x x y SE x SE EQ WL i (b) Doubled-ended Current Mirror Amplifier SRAM cell i Diff. x Sense x Amp y y D D (a) SRAM sensing scheme. y y x x SE (c) Cross-Coupled Amplifier SE Initialized in its meta-stable point with EQ Once adequate voltage gap created, sense amp enabled with SE Positive feedback quickly forces output to a stable operating point. Topic 7-57 Topic 7-58 Single-to-Differential Conversion Open Bitline Architecture WL R EQ L 1 L 0 R 0 R 1 L x Diff. x SE cell S.A. + _ V ref L R y y C S... C S C S SE... C S C S C S How to make good V ref? dummy cell dummy cell Topic 7-59 Topic 7-60

16 DRAM Read Process with Dummy Cell Single-Ended Cascode Amplifier 6.0 VDD V (Volt) V (Volt) t (nsec) (a) reading a zero V (Volt) WL 3.0 SE 2.0 EQ (c) control signals V casc WLC WL t (nsec) (b) reading a one Topic 7-61 Topic 7-62 DRAM Timing (nightmare!) Address Transition Detection A 0 DELAY t d ATD ATD A 1 DELAY t d A N-1 DELAY t d... Topic 7-63 Topic 7-64

17 Outline Content Addressable Memories (CAMs) Memory classification Basic building blocks Extension of ordinary memory (e.g. SRAM) Read and write memory as usual Also match to see which words contain a key Non Volatile Read Write Memories Static RAM (SRAM) Dynamic RAM (DRAM) adr data/key Memory peripheral circuit Content Addressable Memory (CAM) Serial access memories Reliability and Yield Memory trends read write CAM match Topic 7-65 Topic 7-66 CAM Cell Operation 10T CAM Cell Read and write like ordinary SRAM For matching: Leave wordline low Precharge matchlines Place key on bitlines Matchlines evaluate address Miss line Pseudo-nMOS NOR of match lines Goes high if no words match row decoder CAM cell clk weak miss match0 match1 match2 Add four match transistors to 6T SRAM match3 read/write column circuitry data Topic 7-67 Topic 7-68

18 Outline Serial Access Memories Memory classification Basic building blocks Non Volatile Read Write Memories Static RAM (SRAM) Dynamic RAM (DRAM) Serial access memories do not use an address Shift Registers Tapped Delay Lines Serial In Parallel Out (SIPO) Parallel In Serial Out (PISO) Queues (FIFO, LIFO) Memory peripheral circuit Content Addressable Memory (CAM) Serial access memories Reliability and Yield Memory trends Topic 7-69 Topic 7-70 Shift Register Denser Shift Registers Shift registers store and delay data Flip-flops aren t very area-efficient Simple design: cascade of registers Watch your hold times! For large shift registers, keep data in SRAM instead Move read/write pointers to RAM rather than data Initialize read address to first entry, write to last Increment address on each cycle clk Din counter counter readaddr writeaddr dual-ported SRAM reset Dout Topic 7-71 Topic 7-72

19 Tapped Delay Line Serial In Parallel Out A tapped delay line is a shift register with a programmable number of stages Set number of stages with delay controls to mux Ex: 0 63 stages of delay 1-bit shift register reads in serial data After N steps, presents N-bit parallel output Topic 7-73 Topic 7-74 Parallel In Serial Out Queues Load all N bits in parallel when shift = 0 Then shift one bit out per cycle Queues allow data to be read and written at different rates. Read and write each use their own clock, data Queue indicates whether it is full or empty Build with SRAM and read/write counters (pointers) Topic 7-75 Topic 7-76

20 FIFO, LIFO Queues Outline First In First Out (FIFO) Initialize read and write pointers to first element Queue is EMPTY On write, increment write pointer If write almost catches read, Queue is FULL On read, increment read pointer Last In First Out (LIFO) Also called a stack Use a single stack pointer for read and write Memory classification Basic building blocks Non Volatile Read Write Memories Static RAM (SRAM) Dynamic RAM (DRAM) Memory peripheral circuit Content Addressable Memory (CAM) Serial access memories s Reliability and Yield Memory trends Topic 7-77 Topic 7-78 PLAs AND PLANE x 0 x 1 x 2 Product Terms OR PLANE A performs any function in sum-of-products form. Literals: inputs & complements Products / Minterms: AND of literals Outputs: OR of Minterms bc ac Example: Full Adder ab x 0 x 1 x 2 f 0 f 1 s = c = ab+ bc+ ac out a b c s cout Topic 7-79 Topic 7-80

21 NOR-NOR PLAs Pseudo-Static PLA ANDs and ORs are not very efficient in CMOS Dynamic or Pseudo-nMOS NORs are very efficient Use DeMorgan s Law to convert to all NORs bc ac ab bc ac ab x 0 x 0 x 1 x 1 x 2 x 2 f 0 f 1 a b c s c out a b c s c out AND-PLANE OR-PLANE Topic 7-81 Topic 7-82 PLA Schematic & Layout Dynamic PLA AND Plane OR Plane φ AND bc ac ab φ OR a b c s c out φ AND x 0 x 0 x 1 x 1 x 2 x 2 f 0 f 1 φ OR AND-PLANE OR-PLANE Topic 7-83 Topic 7-84

Clock Signal Generation for self-timed dynamic PLA PLA Layout And-Plane Or-Plane φ φ φ φand Dummy AND Row φ AND φand Dummy AND Row φor φor (a) Clock signals (b) Timing generation circuitry.

22 Clock Signal Generation for self-timed dynamic PLA PLA Layout And-Plane Or-Plane φ φ φ φand Dummy AND Row φ AND φand Dummy AND Row φor φor (a) Clock signals (b) Timing generation circuitry. x 0 x 0 x 1 x 1 x 2 x 2 Pull-up devices f 0 f 1 Pull-up devices Topic 7-85 Topic 7-86 PLA versus Outline structured approach to random logic two level logic implementation NOR-NOR (product of sums) NAND-NAND (sum of products) IDENTICAL TO! Main difference : fully populated PLA: one element per minterm Note: Importance of PLA s has drastically reduced 1. slow 2. better software techniques (mutli-level logic synthesis) Memory classification Basic building blocks Non Volatile Read Write Memories Static RAM (SRAM) Dynamic RAM (DRAM) Memory peripheral circuit Serial access memories Content Addressable Memory (CAM) Reliability and Yield Memory trends Topic 7-87 Topic 7-88

23 Reliability and Yield Open Bit-line Architecture Cross Coupling EQ C WL 1 WL 0 WL D WL D WL 0 WL 1 C W C W Sense C C C Amplifier C C C C Topic 7-89 Topic 7-90 Folded-Bitline Architecture Transposed-Bitline Architecture... C C C WL 1 C WL 1 C WL 0 C W C WL 0 C WL D C WL D x EQ x Sense Amplifier y y " " C cross (a) Straightforward bitline routing. C cross SA SA C W (b) Transposed bitline architecture. Topic 7-91 Topic 7-92

24 Yield Redundancy Redundant Row Address rows Fuse : Bank Redundant columns Memory Array Row Decoder Yield curves at different stages of process maturity (from [Veendrick92]) Column Decoder Column Address Topic 7-93 Topic 7-94 Redundancy and Error Correction Outline Memory classification Basic building blocks Non Volatile Read Write Memories Static RAM (SRAM) Dynamic RAM (DRAM) Memory peripheral circuit Serial access memories Content Addressable Memory (CAM) Reliability and Yield Memory trends Topic 7-95 Topic 7-96

25 Semiconductor Memory Trends Semiconductor Memory Trends Increasing die size factor 1.5 per generation Combined with reducing cell size factor 2.6 per generation Memory Size as a function of time: x 4 every three years Topic 7-97 Topic 7-98 Semiconductor Memory Trends Technology feature size for different SRAM generations Topic 7-99

Memory. Outline. ECEN454 Digital Integrated Circuit Design. Memory Arrays. SRAM Architecture DRAM. Serial Access Memories ROM

Memory. Outline. ECEN454 Digital Integrated Circuit Design. Memory Arrays. SRAM Architecture DRAM. Serial Access Memories ROM ECEN454 Digital Integrated Circuit Design Memory ECEN 454 Memory Arrays SRAM Architecture SRAM Cell Decoders Column Circuitry Multiple Ports DRAM Outline Serial Access Memories ROM ECEN 454 12.2 1 Memory