Basic Processing Unit (Chapter 7)
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1 Basic Processing Unit (Chapter 7) IN1212-PDS 1
2 Problem instruction? y Decoder a ALU y f Reg IN1212-PDS 2
3 Basic cycle Assume an instruction occupies a single word in memory Basic cycle to be implemented: 1. Fetch instruction pointed to by PC and put it in Instruction Register (IR) [IR] M([PC]) 2. Increment PC: [PC] [PC] Perform actions as specified in IR IN1212-PDS 3
4 memory bus Organization PC MAR MDR Y ALU Z CPU bus Decoder control IR R0 R1 R2 R3 register file IN1212-PDS 4
5 Const 4 Register gating Y_in CPU bus x Y x Ri_in Select MUX Ri ALU x Z_in x Z Ri_out Z_out x IN1212-PDS 5
6 Operation Operation cycle includes: - Fetch contents of memory location and put in one of the CPU registers - Store contents of CPU register in memory location - Transfer data from register tot register or to ALU - Perform Arithmetic or Logic operation IN1212-PDS 6
7 Fetch from Memory (1) Memory bus Data lines MDR_outE Internal processor bus MDR_out x x MDR x x MDR_inE MDR_in IN1212-PDS 7
8 Fetch from memory (2) 1. [MAR] [Ri] e.g. LHZ Rj,Ri 2. Start read on memory bus 3. Wait for MFC response 4. Load MDR from memory bus 5. [Rj] [MDR] Memory Address Data CPU Read MFC IN1212-PDS 8
9 Fetch from memory (3) Signal Sequence Activation 1. Ri_out, MAR_in, Read 2. MDR_inE, WMFC 3. MDR_out, Rj_in IN1212-PDS 9
10 CLK Timing of read MAR_in address Read MR MDR_inE Data MFC MDR_out IN1212-PDS 10
11 Store to memory e.g. STW Rj,Ri 1. Ri_out, MAR_in 2. Rj_out, MDR_in, Write 3. MDR_outE, WMFC Memory Address Data Write MFC CPU IN1212-PDS 11
12 Register Transfers CPU bus R_out Y_in F_alu Z_in Y ALU Z R0 R1 R2 R3 register file Z_out Address _out R_in Address _in IN1212-PDS 12
13 Copy of registers Copy contents R1 to R3 1. Address_out = R1 2. R_out 3. Address_in = R3 4. R _ in IN1212-PDS 13
14 Register Transfers CPU bus R_out Y_in F_alu Z_in Y ALU Z R0 R1 R2 R3 register file Z_out Address _out R_in Address _in IN1212-PDS 14
15 Arithmetic Operation Step Action 1. Address_out R1 Y_in R_out ADD R3,R2,R1 2. Address_out R2 F_alu ADD Z_in 3. Address_in R3 Z_out R_in IN1212-PDS 15
16 Register Transfers CPU bus R_out Y_in F_alu Z_in Y ALU Z R0 R1 R2 R3 register file Z_out Address _out R_in Address _in IN1212-PDS 16
17 Arithmetic Operation Step Action 1. Address_out R1 Y_in R_out ADD R3,R2,R1 2. Address_out R2 F_alu ADD Z_in 3. Address_in R3 Z_out R_in IN1212-PDS 17
18 Register Transfers CPU bus R_out Y_in F_alu Z_in Y ALU Z R0 R1 R2 R3 register file Z_out Address _out R_in Address _in IN1212-PDS 18
19 Arithmetic Operation Step Action 1. Address_out R1 Y_in R_out ADD R3,R2,R1 2. Address_out R2 F_alu ADD Z_in 3. Address_in R3 Z_out R_in IN1212-PDS 19
20 Register Transfers CPU bus R_out Y_in F_alu Z_in Y ALU Z R0 R1 R2 R3 register file Z_out Address _out R_in Address _in IN1212-PDS 20
21 Steps in time Step Y_in Z_in Z_out R_in IN1212-PDS 21
22 Register gating R/W I R/W I R/W I C C C C D C D C D Q Q Q R1_out R2_out R3_out 1 bit of common bus line Tri-state based gate IN1212-PDS 22
23 Timing Rising edge of clock turn output on transmission time delay through ALU set-up time hold time R_ out data available at next register IN1212-PDS 23
24 Complete instruction 1. Fetch instruction 2. Fetch the operand 3. Perform operation 4. Store result Example ADD (R3),R1 [R1] M([R3]) + [R1] IN1212-PDS 24
25 Execution fetch (1) Step Action 1 PC_out, MAR_in, Read Set carry-in ALU F_alu = ADD Z_in 2 Z_out, PC_in Wait for MFC 3 MDR_out, IR_in Step 1-3: instruction fetch and PC update [PC] [PC ]+1 [IR] M([PC ]) Note: for architectures having PC:=PC+4 a different scheme must be used IN1212-PDS 25
26 Fetch instruction MAR_in MAR PC_in PC IR IR_in ADD Z_in ALU Z PC_out carry MDR MDR_in Read MDR_out WFMC Z_out IN1212-PDS 26
27 Execution fetch (2) Step Action 1 PC_out, MAR_in, Read Set carry-in ALU F_alu = ADD Z_in 2 Z_out, PC_in Wait for MFC Step 1-3: instruction fetch and PC update [PC] [PC ]+1 3 MDR_out, IR_in [IR] M([PC ]) IN1212-PDS 27
28 Fetch instruction MAR_in MAR PC_in PC IR IR_in ADD Z_in ALU Z PC_out carry MDR MDR_in Read MDR_out WFMC Z_out IN1212-PDS 28
29 Execution fetch (3) Step Action 1 PC_out, MAR_in, Read Set carry-in ALU F_alu = ADD Z_in 2 Z_out, PC_in Wait for MFC 3 MDR_out, IR_in Step 1-3: instruction fetch and PC update [PC ] [PC ]+1 [IR] M([PC ]) IN1212-PDS 29
30 Fetch instruction MAR_in MAR PC_in PC IR IR_in ADD Z_in ALU Z PC_out carry MDR MDR_in Read MDR_out WFMC Z_out IN1212-PDS 30
31 Execute Step Action 4 Address_out=R3 MAR_in Read Step 4 and 5: operand fetch 5 Address_out=R1, R_out Y_in, Wait for MFC 6 MDR_out, Z_in F_alu = ADD 7 Address_in=R1 Z_out, R_in, End Perform addition Store Result IN1212-PDS 31
32 Execute Read memory bus PC MAR MDR CPU bus control Decoder IR Y R0 R1 ALU Z R2 R3 register file IN1212-PDS 32
33 Execute Step Action 4 Address_out=R3 MAR_in Read 5 Address_out=R1, R_out Y_in, Wait for MFC 6 MDR_out, Z_in F_alu = ADD 7 Address_in=R1 Z_out, R_in, End Step 4 and 5: operand fetch Perform addition Store Result IN1212-PDS 33
34 Execute WFMC memory bus PC MAR MDR CPU bus Decoder control IR Y R0 R1 ALU Z R2 R3 register file IN1212-PDS 34
35 Execute Step Action 4 Address_out=R3 MAR_in Read 5 Address_out=R1, R_out Y_in, Wait for MFC 6 MDR_out, Z_in F_alu = ADD 7 Address_in=R1 Z_out, R_in, End Step 4 and 5: operand fetch Perform addition Store Result IN1212-PDS 35
36 Execute memory bus PC MAR MDR CPU bus Decoder control IR Y R0 R1 ALU Z R2 R3 register file IN1212-PDS 36
37 Execute Step Action 4 Address_out=R3 MAR_in Read Step 4 and 5: operand fetch 5 Address_out=R1, R_out Y_in, Wait for MFC 6 MDR_out, Z_in F_alu = ADD 7 Address_in=R1 Z_out, R_in, End Perform addition Store Result IN1212-PDS 37
38 Execute memory bus PC MAR MDR CPU bus Decoder control IR Y R0 R1 ALU Z R2 R3 register file IN1212-PDS 38
39 Branching Step Action 1-3 <instruction fetch as in previous example> 4 PC_out, Y_in 5 Off-set-field-IR_out F_alu = ADD Z_in 6 PC_in Z_out, End IN1212-PDS 39
40 memory bus PC MAR MDR Y ALU Z Branching CPU bus Decoder control IR R0 R1 R2 R3 register file IN1212-PDS 40
41 Branching Step Action 1-3 <instruction fetch as in previous example> 4 PC_out, Y_in 5 Off-set-field-IR_out F_alu = ADD Z_in 6 PC_in Z_out, End IN1212-PDS 41
42 memory bus PC MAR MDR Y ALU Z Branching CPU bus Decoder control IR R0 R1 R2 R3 register file IN1212-PDS 42
43 Branching Step Action 1-3 <instruction fetch as in previous example> 4 PC_out, Y_in 5 Off-set-field-IR_out F_alu = ADD Z_in 6 PC_in Z_out, End IN1212-PDS 43
44 memory bus PC MAR MDR Y ALU Z Branching CPU bus Decoder control IR R0 R1 R2 R3 register file IN1212-PDS 44
45 Conditional branching Step Action 1-3 <instruction fetch as in previous example> 4 PC_out, Y_in If N=0 then End 5 Off-set-field-IR_out F_alu = ADD Z_in 6 PC_in Z_out, End IN1212-PDS 45
46 Control mechanisms There are two basic control organizations: - Hardwired control - Micro-programmed control IN1212-PDS 46
47 Control Unit Organization Clock CLK Control step counter IR Encoder/ Decoder Status Flags Condition Codes Control signals IN1212-PDS 47
48 Separating decoding/encoding Clock Control step counter Reset IR Instruction decoder Step decoder T_1 T_n Ins_1 Encoder Ins_n Status Flags Condition Codes Run End IN1212-PDS 48
49 Generation of control signals ADD T_6 BR T_5 T_1 Z_in = T_1 + T_6. ADD + T_5. BR Z_in IN1212-PDS 49
50 End signal Other example: End = T_7. ADD + T_6. BR +(T_6. N + T_4. /N). BRN IN1212-PDS 50
51 PLA s PLA AND array OR array IR counter Flags Control signals IN1212-PDS 51
52 Performance Performance is dependent on: - Power of instructions - Cycle time - Number of cycles per instruction Performance improvement by: - Multiple datapaths - Instruction prefetching and pipelining - Caches IN1212-PDS 52
53 Multiple datapaths Y R0 R1 R2 ALU R3 register file IN1212-PDS 53
54 Complete CPU Instruction unit Integer unit Floating-point unit Instruction Cache Data Cache Bus Interface CPU Main Memory Input/ Output IN1212-PDS 54
55 Microprogrammed control All control bits are organized as memory Each memory location represents a control setting Memory words are called microinstructions IN1212-PDS 55
56 Example micro- PC_in MAR_in Addr_in Z_in... instruction IN1212-PDS 56
57 Basic organization IR Starting address generator Clock micro-pc Control Store Control Signals IN1212-PDS 57
58 Micro-routine Address Micro-instruction 0 PC_out, MAR_in, Read, Set carry-in ALU, F_alu = ADD, Z_in 1 Z_out, PC_in, Wait for MFC 2 MDR_out, IR_in Fetch Instruction 3 Branch to starting address routine (here 25) PC_out, Y_in, if N=0 then goto address 0 Test N bit 26 Offset-field-of-IR_out, F_alu = ADD, Z_in 27 Z_out, PC_in, End New PC address IN1212-PDS 58
59 Detailed organization IR Starting address generator Status flags Control codes Clock micro-pc Control Store Control Signals IN1212-PDS 59
60 micro-pc Micro-PC is incremented by 1, except: - At End» Micro-PC is set to first micro-instruction of instruction fetch routine - After loading IR» Micro-PC is set to first micro-instruction for executing machine instruction - At Branch instruction IN1212-PDS 60
61 Why micro-programming Flexibility - emulation of different instruction sets on same hardware Support for powerful instructions IN1212-PDS 61
62 Structure micro-instructions Most simple organization: 1 bit per control signal However, - Many bits needed (e.g bits) - For many signals only one is needed per cycle; hence they can be grouped - Coding is possible: e.g. an address instead of a single control bit per register IN1212-PDS 62
63 Example F1 F2 F3 F4 F5 F6 F7 F8 Field 1(4 bits): Register address_in Field 2(4 bits): Register address_out Field 3(4 bits): Other registers_in Field 4(4 bits): Function ALU Field 5(2 bit) : Read/Write/Nop Field 6(1 bit) : Carry-in ALU Field 7(1 bit) : WMFC Field 8(1 bit) : End IN1212-PDS 63
64 Forms of organization Little coding: horizontal organization - Large words - Little decoding logic - Fast Much coding: vertical organization - Small control store - Much decoding logic - Slower Mixed organization IN1212-PDS 64
65 Horizontal/Vertical F0 F1 F2 F3 Horizontal R0 R1 R2 R3 F0 F1 Decoder Vertical R0 R1 R2 R3 IN1212-PDS 65
66 Sequencing Thus far only branch after fetch No sharing of micro-code between microroutines micro-subroutines leads to more efficient control store IN1212-PDS 66
67 Multi-way branching Number of two-way branches - disadvantage: slows down More than one branch address in microinstruction - disadvantage: more bits required bit-oring if specified branch address IN1212-PDS 67
68 Example branch address x x x 0 0 micro-instruction x x x x x.. actual branch address OR Part IR IN1212-PDS 68
69 Example microroutine (1) ADD (Rsrc)+, Rdst IR Mode OP code 010 Rsrc Rdst Instruction Format bit 8: direct/indirect bit 9,10: indexed (11) autodecrement(10) autoincrement(01) register(00) IN1212-PDS 69
70 Example microroutine (2) Address Micro-instruction 0 PC_out, MAR_in, Read, Set carry-in ALU, F_alu = ADD, Z_in 1 Z_out, PC_in, Wait FETCH for MFC use bits from IR for 2 MDR_out, IR_in adressing mode 3 µbranch{µpc 101 (from PLA); µpc_5,4 [IR_10,9]; µpc_3 [not.ir_10].[not.ir_9].[ir_8]} Rsrc_out, MAR_in, Set carry-in ALU,Read, F_alu = ADD, Z_in 122 Z_out, Rscr_in 123 µbranch{µpc 170; µpc_0 [not.ir_8]}, WMFC 170 direct MDR_out, MAR_in, Read, WMFC autoincrement 171 MDR_out, Y_in 172 Rdst_out, F_alu = ADD, Z_in indirect 173 Z_out, Rdst_in, End IN1212-PDS 70
71 Micro branch address IR Mode OP code 010 Rsrc Rdst /IR10./IR9.IR8 PLA IN1212-PDS 71
72 Micro branch address IR Mode OP code 010 Rsrc Rdst /IR8 PLA IN1212-PDS 72
73 Next-address field (1) Micro-instruction contains address next micro-instruction Larger store needed Branch micro-instructions no longer needed IN1212-PDS 73
74 Next-address field (2) Status flags IR Condition codes Decoding circuits micro-ar Control store Next address micro-ir Microinstruction decoder IN1212-PDS 74
75 Example F0 F1 F2 F3 F4 F5 F6 F7 F8 Field 0(8 bits): Next address Field 1(4 bits): Register address_in Field 2(4 bits): Register address_out Field 3(4 bits): Other registers_in Field 4(4 bits): Function ALU Field 5(2 bit) : Read/Write/Nop Field 6(1 bit) : Carry-in ALU Field 7(1 bit) : WMFC Field 8(1 bit) : End... PLA/ORing etc IN1212-PDS 75
76 Emulation A micro program determines machine instruction of computer Suppose we have two computers M 1 and M 2 with different instruction sets By adapting the micro-program of M 1, we can emulate M 2 IN1212-PDS 76
77 Organization Micro-program is often placed in ROM on CPU chip Some machines had writable control store, i.e. user could change instruction set IN1212-PDS 77
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