EE141-Fall 2007 Digital Integrated Circuits. ROM and Flash. Announcements. Read-Only Memory Cells. Class Material. Semiconductor Memory Classification

Transcription

1 EE4-Fall 2007 igital Integrated Circuits Lecture 29 ROM, Flash, and RAM ROM and Flash 4 4 Announcements Final ec. 20 th Room TBA Final review sessions: Mon. ec. 7 th 3:30pm, 550 Cory Tues. ec. 7 th 3:30pm, 550 Cory emiconductor Memory Classification Read-Write Memory Random Access Non-Random Access Non-Volatile Read-Write Memory EPROM E 2 PROM Read-Only Memory Mask-Programmed Programmable (PROM) RAM FIFO FLAH RAM LIFO hift Register CAM Class Material Read-Only Memory Cells Last lecture Multipliers Today s lecture ROM Flash RAM Reading Chapter 2 0 iode ROM MO ROM MO ROM

2 MO OR ROM MO NAN ROM [0] [] [2] [3] [0] [0] [] [2] Precharge devices [3] [] [0] [2] [] [2] [3] [3] Pre-discharge devices 7 7 All word lines high by default with exception of selected row 0 0 MO NOR ROM [0] [] [2] Pull-up devices MO NAN ROM Layout Cell (8λ x 7λ) Programmming using the Metal- Layer Only No contact to V or necessary; drastically reduced cell size Loss in performance compared to NOR ROM [3] [0] [] [2] [3] Metal on 8 8 MO NOR ROM Layout Cell (9.5λ x 7λ) NAN ROM Layout Cell (5λ x 6λ) Programmming using the Active Layer Only Programmming using Implants Only Metal Metal on Threshold-lowering implant

3 Floating ate Transistor Cross-sections sections of NVM cells Control gate Floating gate erasure n + source programming p-substrate Thin tunneling oxide n + drain Many other options 3 3 Flash Courtesy Intel EPROM 6 6 Programmable-Threshold Erase I 0 -state ON V T -state 2 V cell array V OFF V V open open Floating-ate Transistor Programming Write V 6 V 2 V 0 0 Avalanche injection Removing programming voltage leaves charge trapped Programming results in higher V T. 6 V

4 Read V 0 0 RAM V NAN Flash Memory elect (poly) -Transistor RAM Cell Write Read M X 2 V T C Unit Cell Word line(poly) ate ONO /2 V sensing /2 C ate Oxide F Write: C is charged or discharged by asserting and. Read: Charge redistribution takes places between bit line and storage capacitance elect2 (poly) ource line (iff. Layer) 20 Courtesy Lecture Toshiba #29 20 C V = V V PRE = V BIT V PRE C + C Voltage swing is small; typically < 200 mv NAN Flash Memory Active area elect transistor TI Bit line contact Word lines ource line contact RAM Cell Observations T RAM requires a sense amplifier for each bit line, due to charge redistribution read-out. RAM memory cells are single ended in contrast to RAM cells. The read-out of the T RAM cell is destructive; read and refresh operations are necessary for correct operation. When writing a into a RAM cell, a threshold voltage is lost. This charge loss can be circumvented by bootstrapping the word lines to a higher value than Courtesy Toshiba

5 ense Amp Operation V V() THE EN This is just the beginning V PRE V() ense amp activated Word line activated V(0) t T T RAM Cell Capacitor Metal word line Poly n + n + Inversion layer Poly induced by plate bias Cross-section io 2 Field Oxide iffused bit line gate Layout plate M word line Uses - Capacitance Expensive in Area Modern T RAM Cells Word line Insulating Layer Cell plate Capacitor dielectric layer Cell Plate i Capacitor Insulator Refilling Poly Transfer gate Isolation torage electrode torage Node Poly 2nd Field Oxide i ubstrate Trench Cell tacked-capacitor Cell 27 27