SSD Firmware Implementation Project Lab. #4
|
|
|
- Toby Washington
- 5 years ago
- Views:
Transcription
1 SSD Firmware Implementation Project Lab. #4 Sang Phil Lim SKKU VLDB Lab
2 Lab. Time Schedule Lab. Title #1 FTL Simulator Development Guide #2 FTL Simulation Guide #3 Project 1 Presentation #4 Jasmine OpenSSD platform tutorial #1 #5 Jasmine OpenSSD platform tutorial #2 #6 FTL Porting Guide #7 Firmware Debugging Guide #8 SSD Performance Evaluation Guide #9 Project 2 Presentation
3 Now, it is time to move on the REAL Environment
4 The OpenSSD Project It is an initiative to promote research and education on the recent SSD (Solid State Drive) technology by providing easy access to OpenSSD platforms on which open source SSD firmware can be developed project.org/
5 INDILINX Jasmine Platform H/W perspective
6 Jasmine Reference Board Flash Memory Socket (DIMM) (front #4, rear #4) UART port JTAG debug port 64MB SDRAM SATA 2.0 (3Gbps) Indilinx Barefoot TM SSD Controller NAND Flash Module (K9LCG08U1M, Samsung)
7 Jasmine Reference Board INDILINX Barefoot TM Controller Clock Generator UART SRAM (96KB) Controller ROM Controller ARM7TDMI-S Core APB Bridge GPIO Timer AHB WDT NAND Controller Buffer Manager SATA Device DRAM Controller Memory Utility PMU ICU DRAM Access Bus JTAG NAND Flash SATA Host interface DRAM JTAG debug port
8 1. Memory Map Overview
9 1. Memory Map DRAM footprint
10 2. SATA Controller Handling IO request from host By FIQ handler SATA NCQ(Native Command Queuing) Queuing incomplete command 32 queue depth, FIFO SATA command queue Queuing complete command 128 entry, FIFO
11 2. SATA Controller SATA NCQ & SATA command queue
12 3. Buffer Manager Buffer frame allocation & management
13 4. Memory Utility & ECC Engine DRAM access limitation E.g. mem_copy AHB DRAM Controller 132B ECC parity 128B 128B 128B 4B 4B 4B 8B 4B DRAM SRAM 8B Memory Utility DMA bus
14 5. NAND Flash Architecture Multi ch/multi way architecture 4 channel 8 way
15 5. NAND Flash Architecture Bank 16 Bit IO bus High/Low NAND chips Virtual block/page In 2 plane mode, Physical page size x 4 Physical block size x 4
16 5. NAND Flash Architecture Interleaved IO (2 plane mode) AA... 16KB 16KB High Low Plane 0 Plane 1 Plane 0 Plane 1 Per plane Page register AA Block 0 Block 1 Block 0 Block 1 interleaved
17 Ref) Two plane Page Program Timing diagram
18 5. NAND Flash Architecture Page copy back FC_CPBACK FC_MODIFY_CPBACK
19 6. NAND Flash Controller Handling flash command
20 6. NAND Flash Controller FCP BSP For setting flash cmd. For debugging
21 Getting Started to Develop an FTL
22 1. Development Environment Setup Hardware Requirement Software Requirement Jasmine Firmware Software (latest release) project.org/wiki/downloads MS Visual Studio Express Free Edition 2010 Code Sourcery G++ Lite Edition for ARM
23 1. Development Environment Setup Hardware Setting RS 232 cable Serial Host PC SATA SATA cable Power cable SATA UART Jasmine
24 1. Development Environment Setup Software Setting Install compilation tool MS Visual Studio Express Free Edition 2010 To build the firmware installer (install.exe) Code Sourcery G++ Lite Edition for ARM To build Firmware binary file (firmware.bin) Setting for serial communication Hyper terminal (BAUD_115200/8/N/1/X)
25 2. Compile & Build firmware Build the firmware software using GNU tools > cd./build_gnu > build.bat Compile the installer Open./installer/installer.sln & Build Move./installer/install.exe to./build_gnu
26 3. Install Firmware to Jasmine Board Booting the Jasmine board as Factory mode Device manager Install Firmware >./build_gnu/install.exe
27 3. Install Firmware to Jasmine Board Install for the first time Reinstall 1 2 3
28 4. Run Firmware Booting the Jasmine board as Normal mode Unplug SATA cable Jasmine would be busy doing internal low level format Plug SATA cable when LED at D4 position is lit Now that Jasmine is ready to process SATA command Try to send IO requests to Jasmine board!
29 Jasmine Technical Document You can download on the OpenSSD Project homepage project.org Technical Reference Manual Jasmine Board Specification INDILINX Barefoot TM SSD Controller Specification Jasmine Firmware Architecture Jasmine Firmware Software Specification FTL Developer s Guide FTL Porting Guide Compile, Build & Install Firmware Debugging Tips
30 Any Questions?
Dummy FTL. Dong-Yun Computer Systems Laboratory Sungkyunkwan University
Dummy FTL Dong-Yun Lee(dongyun.lee@csl.skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Troubleshooting Q. Compile errors occured in eabi-related libraries A. Modify all
Introduction to the OpenSSD Jasmine Platform
Introduction to the OpenSSD Jasmine Platform Prof. Jinkyu Jeong (Jinkyu@skku.edu) TA -- Minwoo Ahn (minwoo.ahn@csl.skku.edu) TA -- Donghyun Kim (donghyun.kim@csl.skku.edu) Computer Systems Laboratory Sungkyunkwan
SSD Firmware Implementation Project Lab. #5
SSD Firmware Implementation Project Lab. #5 Sang Phil Lim (lsfeel0204@gmail.com) SKKU VLDB Lab. 2011 05 12 Lab. Time Schedule Lab. Title #1 FTL Simulator Development Guide #2 FTL Simulation Guide #3 Project
Tutorial FTL. Jinyong Computer Systems Laboratory Sungkyunkwan University
Tutorial FTL Jinyong Ha(jinyongha@csl.skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Contents NAND Flash Memory NAND Flash Operation NAND Flash Configuration NAND Controller
SSD Firmware Implementation Project Lab. #6
SSD Firmware Implementation Project Lab. #6 Sang Phil Lim (lsfeel0204@gmail.com) SKKU VLDB Lab. 2011 05 19 Lab. Time Schedule Lab. Title #1 FTL Simulator Development Guide #2 FTL Simulation Guide #3 Project
Tutorial FTL. Sejun Kwon Computer Systems Laboratory Sungkyunkwan University
Tutorial FTL Sejun Kwon Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Contents NAND Flash Memory NAND Flash Operation NAND Flash Architecture NAND Controller Tutorial FTL ICE3028:
OSSD: Object-based Solid State Drive. Jin-Soo Kim Computer Systems Laboratory Sungkyunkwan University
OSSD: Object-based Solid State Drive Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu OSSD S S D + O S D O S S D NVRAMOS 2011, Cheju Island, Korea,
High Performance SSD & Benefit for Server Application
High Performance SSD & Benefit for Server Application AUG 12 th, 2008 Tony Park Marketing INDILINX Co., Ltd. 2008-08-20 1 HDD SATA 3Gbps Memory PCI-e 10G Eth 120MB/s 300MB/s 8GB/s 2GB/s 1GB/s SSD SATA
Fujitsu System Applications Support. Fujitsu Microelectronics America, Inc. 02/02
Fujitsu System Applications Support 1 Overview System Applications Support SOC Application Development Lab Multimedia VoIP Wireless Bluetooth Processors, DSP and Peripherals ARM Reference Platform 2 SOC
NEXT-GENERATION SSD VERIFICATION PLATFORM WITH TERA-SCALE NAND CAPACITY AND STORAGE SIGNAL PROCESSING SUPPORT
NEXT-GENERATION SSD VERIFICATION PLATFORM WITH TERA-SCALE CAPACITY AND STORAGE SIGNAL PROCESSING SUPPORT NVRAMOS 2012-10-16 Seil Lee, Myunghyun Rhee, and Sungroh Yoon Advanced Computing Laboratory, Seoul
Product Technical Brief S3C2412 Rev 2.2, Apr. 2006
Product Technical Brief S3C2412 Rev 2.2, Apr. 2006 Overview SAMSUNG's S3C2412 is a Derivative product of S3C2410A. S3C2412 is designed to provide hand-held devices and general applications with cost-effective,
Product Technical Brief S3C2413 Rev 2.2, Apr. 2006
Product Technical Brief Rev 2.2, Apr. 2006 Overview SAMSUNG's is a Derivative product of S3C2410A. is designed to provide hand-held devices and general applications with cost-effective, low-power, and
Getting Real: Lessons in Transitioning Research Simulations into Hardware Systems
Getting Real: Lessons in Transitioning Research Simulations into Hardware Systems Mohit Saxena, Yiying Zhang Michael Swift, Andrea Arpaci-Dusseau and Remzi Arpaci-Dusseau Flash Storage Stack Research SSD
MAS060X. SATA III To Flash Controller. Data Sheet 2015 年 10 月. Document No.: DAT-0151-A01
MAS060X SATA III To Flash Controller Data Sheet Document No.: DAT-0151-A01 2015 年 10 月 DAT-0151-A01 March 10, 2015, Maxio Technology (Hangzhou) Ltd. All Rights Reserved. No part of this publication may
Memory Modem TM FTL Architecture for 1Xnm / 2Xnm MLC and TLC Nand Flash. Hanan Weingarten, CTO, DensBits Technologies
Memory Modem TM FTL Architecture for 1Xnm / 2Xnm MLC and TLC Nand Flash Hanan Weingarten, CTO, DensBits Technologies August 21, 2012 1 Outline Requirements 1xnm/2xnm TLC NAND Flash Reliability Challenges
Prof. Yong Ho Song Department of Electronic Engineering, Hanyang University
Prof. Yong Ho Song Department of Electronic Engineering, Hanyang University Need a SSD platform - to develop a new firmware algorithm - to explore hardware architecture and organization Use a commercial
Product Technical Brief S3C2416 May 2008
Product Technical Brief S3C2416 May 2008 Overview SAMSUNG's S3C2416 is a 32/16-bit RISC cost-effective, low power, high performance micro-processor solution for general applications including the GPS Navigation
A Flash Scheduling Strategy for Current Capping in Multi-Power-Mode SSDs
A Flash Scheduling Strategy for Current Capping in Multi-Power-Mode SSDs Li-Pin Chang, Chia-Hsiang Cheng, and Kai-Hsiang Lin Department of Computer Science National Chiao-Tung University, Taiwan Presented
OSSD: A Case for Object-based Solid State Drives
MSST 2013 2013/5/10 OSSD: A Case for Object-based Solid State Drives Young-Sik Lee Sang-Hoon Kim, Seungryoul Maeng, KAIST Jaesoo Lee, Chanik Park, Samsung Jin-Soo Kim, Sungkyunkwan Univ. SSD Desktop Laptop
StrongARM** SA-110/21285 Evaluation Board
StrongARM** SA-110/21285 Evaluation Board Brief Datasheet Product Features Intel offers a StrongARM** SA-110/21285 Evaluation Board (EBSA-285) that provides a flexible hardware environment to help manufacturers
Zynq Architecture, PS (ARM) and PL
, PS (ARM) and PL Joint ICTP-IAEA School on Hybrid Reconfigurable Devices for Scientific Instrumentation Trieste, 1-5 June 2015 Fernando Rincón Fernando.rincon@uclm.es 1 Contents Zynq All Programmable
Avnet, Xilinx ATCA PICMG Design Kit Hardware Manual
user s guide Avnet, Xilinx ATCA PICMG Design Kit Hardware Manual Avnet Design Services 1 of 18 Rev 1.0 12/15/2004 Table of Contents 1 Overview... 5 2 Jumpers... 6 3 Personality Module Mechanicals... 8
Intelop. *As new IP blocks become available, please contact the factory for the latest updated info.
A FPGA based development platform as part of an EDK is available to target intelop provided IPs or other standard IPs. The platform with Virtex-4 FX12 Evaluation Kit provides a complete hardware environment
Core Peripherals. Speaker: Tzu-Wei Tseng. Adopted from National Chiao-Tung University IP Core Design. SOC Consortium Course Material
Core Peripherals Speaker: Tzu-Wei Tseng Adopted from National Chiao-Tung University IP Core Design SOC Consortium Course Material Goal of This Lab Familiarize with ARM Hardware Development Environment
F9 Flash Memory Controller
F9 Flash Memory Controller F9 F9 Flash Memory Controller The Hyperstone F9 family of Flash Memory Controllers together with provided application and Flash specific firmware offers an easy-to-use turnkey
Flash Memory Controller
F3 Flash Memory ler F3 Flash Memory ler The Hyperstone F3 family of Flash Memory lers together with provided application and flash specific firmware offers an easy-to-use turnkey platform for high endurance
Virtual Array Architecture for efpga April 5, 2018
Virtual Array Architecture for efpga April 5, 2018 Cheng C. Wang SVP of Engineering Copyright 2014-2018 Flex Logix Technologies, Inc. Why the Need for Virtual Arrays? Security: Keep your secret sauce design
Looking Ahead to Higher Performance SSDs with HLNAND
Looking Ahead to Higher Performance SSDs with HLNAND Roland Schuetz Director, Applications & Business Initiatives MOSAID Technologies Inc. Soogil Jeong Vice President, Engineering INDILINX Infrastructure
2001 Altera Corporation (1)
2001 Altera Corporation (1) SOPC Design Using ARM-Based Excalibur Devices Outline! ARM-based Devices Overview! Embedded Stripe! Excalibur MegaWizard! Verification Tools Bus Functional Model Full Stripe
L2 - C language for Embedded MCUs
Formation C language for Embedded MCUs: Learning how to program a Microcontroller (especially the Cortex-M based ones) - Programmation: Langages L2 - C language for Embedded MCUs Learning how to program
U9 Flash Memory Controller
U9 Flash Memory Controller U9 U9 Flash Memory Controller The Hyperstone U9 family of Flash Memory Controllers together with provided firmware offers an easy-to-use turnkey solution for industrial, high
MIRA M2320 series Halfslim SSD Specification. v0.1
1 MIRA M2320 series Halfslim SSD Specification v0.1 2 Revision History Date Version Changes compared to previous issue Jun 1 nd, 2012 0.1 - Initial Release 3 Table of Contents Introduction:... 4 Main Feature:...
Copyright 2016 Xilinx
Zynq Architecture Zynq Vivado 2015.4 Version This material exempt per Department of Commerce license exception TSU Objectives After completing this module, you will be able to: Identify the basic building
Systems in Silicon. Converting Élan SC400/410 Design to Élan SC520
Converting Élan SC400/410 Design to Élan SC520 1 Élan SC400/410 Block Diagram Am486 Core 8K Cache Parallel Port Mobile Logic Blocks PCMCIA (2) (2) PIO 16550 UART SW Compatibility Blocks PIC DMA PIT (2)
Chapter 6 Storage and Other I/O Topics
Department of Electr rical Eng ineering, Chapter 6 Storage and Other I/O Topics 王振傑 (Chen-Chieh Wang) ccwang@mail.ee.ncku.edu.tw ncku edu Feng-Chia Unive ersity Outline 6.1 Introduction 6.2 Dependability,
C900 PowerPC G4+ Rugged 3U CompactPCI SBC
C900 PowerPC G4+ Rugged 3U CompactPCI SBC Rugged 3U CompactPCI SBC PICMG 2.0, Rev. 3.0 Compliant G4+ PowerPC 7447A/7448 Processor @ 1.1 Ghz with AltiVec Technology Marvell MV64460 Discovery TM III System
I/O. Disclaimer: some slides are adopted from book authors slides with permission 1
I/O Disclaimer: some slides are adopted from book authors slides with permission 1 Thrashing Recap A processes is busy swapping pages in and out Memory-mapped I/O map a file on disk onto the memory space
MYD-IMX28X Development Board
MYD-IMX28X Development Board MYC-IMX28X CPU Module as Controller Board Two 1.27mm pitch 80-pin SMT Connectors for Board-to-Board Connections 454MHz Freescale i.mx28 Series ARM926EJ-S Processors 128MB DDR2
Blackfin ADSP-BF533 External Bus Interface Unit (EBIU)
The World Leader in High Performance Signal Processing Solutions Blackfin ADSP-BF533 External Bus Interface Unit (EBIU) Support Email: china.dsp@analog.com ADSP-BF533 Block Diagram Core Timer 64 L1 Instruction
TQ2440 Development Platform Manual
TQ2440 Development Platform Manual 0 Directory Directory... 1 Chapter 1 Introduction... 7 11Appearance of TQ2440 development platform... 7 12Hardware resource of TQ2440... 7 13Software introduction of
Designing with ALTERA SoC Hardware
Designing with ALTERA SoC Hardware Course Description This course provides all theoretical and practical know-how to design ALTERA SoC devices under Quartus II software. The course combines 60% theory
Effective System Design with ARM System IP
Effective System Design with ARM System IP Mentor Technical Forum 2009 Serge Poublan Product Marketing Manager ARM 1 Higher level of integration WiFi Platform OS Graphic 13 days standby Bluetooth MP3 Camera
SpaceWire Remote Terminal Controller
Remote Terminal Controller Presented by Jørgen Ilstad On board Payload Data Section, ESTEC Wahida Gasti, ESA ESTEC Co Authors Sandi Habinc, Gaisler Research Peter Sinander, SAAB Space Slide : 1 Overview
Interconnects, Memory, GPIO
Interconnects, Memory, GPIO Dr. Francesco Conti f.conti@unibo.it Slide contributions adapted from STMicroelectronics and from Dr. Michele Magno, others Processor vs. MCU Pipeline Harvard architecture Separate
A Caching-Oriented FTL Design for Multi-Chipped Solid-State Disks. Yuan-Hao Chang, Wei-Lun Lu, Po-Chun Huang, Lue-Jane Lee, and Tei-Wei Kuo
A Caching-Oriented FTL Design for Multi-Chipped Solid-State Disks Yuan-Hao Chang, Wei-Lun Lu, Po-Chun Huang, Lue-Jane Lee, and Tei-Wei Kuo 1 June 4, 2011 2 Outline Introduction System Architecture A Multi-Chipped
Lecture 5: Computing Platforms. Asbjørn Djupdal ARM Norway, IDI NTNU 2013 TDT
1 Lecture 5: Computing Platforms Asbjørn Djupdal ARM Norway, IDI NTNU 2013 2 Lecture overview Bus based systems Timing diagrams Bus protocols Various busses Basic I/O devices RAM Custom logic FPGA Debug
NPE-300 and NPE-400 Overview
CHAPTER 3 This chapter describes the network processing engine (NPE) models NPE-300 and NPE-400 and contains the following sections: Supported Platforms, page 3-1 Software Requirements, page 3-1 NPE-300
C901 PowerPC MPC7448 3U CompactPCI SBC
C901 PowerPC MPC7448 3U CompactPCI SBC Rugged 3U CompactPCI SBC PowerPC 7448 @ 1.4 GHz, 1.0 GHz, or 600 MHz, with AltiVec Technology 166 MHz MPX Bus Marvell MV64460 Discovery TM III System Controller One
ARM Cortex core microcontrollers 3. Cortex-M0, M4, M7
ARM Cortex core microcontrollers 3. Cortex-M0, M4, M7 Scherer Balázs Budapest University of Technology and Economics Department of Measurement and Information Systems BME-MIT 2018 Trends of 32-bit microcontrollers
Cannon Mountain Dr Longmont, CO LS6410 Hardware Design Perspective
LS6410 Hardware Design Perspective 1. S3C6410 Introduction The S3C6410X is a 16/32-bit RISC microprocessor, which is designed to provide a cost-effective, lowpower capabilities, high performance Application
Five Key Steps to High-Speed NAND Flash Performance and Reliability
Five Key Steps to High-Speed Flash Performance and Reliability Presenter Bob Pierce Flash Memory Summit 2010 Santa Clara, CA 1 NVM Performance Trend ONFi 2 PCM Toggle ONFi 2 DDR SLC Toggle Performance
MYD-IMX28X Development Board
MYD-IMX28X Development Board MYC-IMX28X CPU Module as Controller Board Two 1.27mm pitch 80-pin SMT Male Connectors for Board-to-Board Connections 454MHz Freescale i.mx28 Series ARM926EJ-S Processors 128MB
High-Speed NAND Flash
High-Speed NAND Flash Design Considerations to Maximize Performance Presented by: Robert Pierce Sr. Director, NAND Flash Denali Software, Inc. History of NAND Bandwidth Trend MB/s 20 60 80 100 200 The
Renice X2 1.8 micro SATA SSD DATA Sheet
2011 Renice X2 1.8 micro SATA SSD DATA Sheet Alee Xu Renice Technology Co., Limited 2011-1-20 1 CATALOGUE 1. Introduction......4 1.1 Product Overview...4 1.2 Feature... 4 2. Functional Block Diagram...
Sophon SC1 White Paper
Sophon SC1 White Paper V10 Copyright 2017 BITMAIN TECHNOLOGIES LIMITED All rights reserved Version Update Content Release Date V10-2017/10/25 Copyright 2017 BITMAIN TECHNOLOGIES LIMITED All rights reserved
The World Leader in High Performance Signal Processing Solutions. DSP Processors
The World Leader in High Performance Signal Processing Solutions DSP Processors NDA required until November 11, 2008 Analog Devices Processors Broad Choice of DSPs Blackfin Media Enabled, 16/32- bit fixed
NIOS II Pixel Display
NIOS Pixel Display SDRAM 512Mb Clock Reset_bar CPU Onchip Memory External Memory Controller JTAG UART Pixel DMA Resampler Scaler Dual Port FIFO VGA Controller Timer System ID VGA Connector PLL 2 tj SDRAM
Next Generation Multi-Purpose Microprocessor
Next Generation Multi-Purpose Microprocessor Presentation at MPSA, 4 th of November 2009 www.aeroflex.com/gaisler OUTLINE NGMP key requirements Development schedule Architectural Overview LEON4FT features
Improving MLC flash performance and endurance with Extended P/E Cycles
Improving MLC flash performance and endurance with Extended P/E Cycles Fabio Margaglia, André Brinkmann Johannes Gutenberg University, Mainz, Germany Motivation Flash wear out is dependent on the number
OK335xS Users Manual Part I - Introduction
OK335xS Users Manual Part I - Introduction Copyright@2013-2014 http://www.arm9board.net COPYRIGHT STATEMENT Contents (content being images, text, programs and scripts) of this manual is copyright Witech
VSSIM: Virtual Machine based SSD Simulator
29 th IEEE Conference on Mass Storage Systems and Technologies (MSST) Long Beach, California, USA, May 6~10, 2013 VSSIM: Virtual Machine based SSD Simulator Jinsoo Yoo, Youjip Won, Joongwoo Hwang, Sooyong
Samsung S3C4510B. Hsung-Pin Chang Department of Computer Science National Chung Hsing University
Samsung S3C4510B Hsung-Pin Chang Department of Computer Science National Chung Hsing University S3C4510B A 16/32-bit RISC microcontroller is a cost-effective, highperformance microcontroller 16/32-bit
Product Series SoC Solutions Product Series 2016
Product Series Why SPI? or We will discuss why Serial Flash chips are used in many products. What are the advantages and some of the disadvantages. We will explore how SoC Solutions SPI and QSPI IP Cores
OpenSSD Platform Simulator to Reduce SSD Firmware Test Time. Taedong Jung, Yongmyoung Lee, Ilhoon Shin
OpenSSD Platform Simulator to Reduce SSD Firmware Test Time Taedong Jung, Yongmyoung Lee, Ilhoon Shin Department of Electronic Engineering, Seoul National University of Science and Technology, South Korea
CoLinkEx_LPC11C14 EVB Kit User Guide
CoLinkEx_LPC11C14 EVB Kit User Guide Rev. 1.0 Release: 2012-05-07 Website: http://www.coocox.org Forum: http://www.coocox.org/forum/forum.php?id=1 Techinal: master@coocox.com Market: market@coocox.com
Product Technical Brief S3C2440X Series Rev 2.0, Oct. 2003
Product Technical Brief S3C2440X Series Rev 2.0, Oct. 2003 S3C2440X is a derivative product of Samsung s S3C24XXX family of microprocessors for mobile communication market. The S3C2440X s main enhancement
Design Choices for FPGA-based SoCs When Adding a SATA Storage }
U4 U7 U7 Q D U5 Q D Design Choices for FPGA-based SoCs When Adding a SATA Storage } Lorenz Kolb & Endric Schubert, Missing Link Electronics Rudolf Usselmann, ASICS World Services Motivation for SATA Storage
NS9210/NS9215. Overview. Block Diagram. NS µ CMOS, 265-pin BGA. Features/Benefits. Platforms and Services.
NS9210/NS9215 32-bit NET+ARM Processor Family Cost-efficient, small footprint ARM926EJ-S processor with integrated encryption and unique interface flexibility. Overview The NS9210/NS9215 processor family
GLS89SP032G3/064G3/128G3/256G3/512G3/001T3 Industrial Temp 2.5 SATA ArmourDrive PX Series
Features Industry Standard 2.5 SATA Host Interface - SATA 1.5Gb/s, 3Gb/s and 6Gb/s - SATA Revision 3.2 - ATA/ATAPI-8 compliant - Supports 48-bit address feature set Performance - Sequential data read:
AT-501 Cortex-A5 System On Module Product Brief
AT-501 Cortex-A5 System On Module Product Brief 1. Scope The following document provides a brief description of the AT-501 System on Module (SOM) its features and ordering options. For more details please
Getting Real: Lessons in Transitioning Research Simulations into Hardware Systems
Getting Real: Lessons in Transitioning Research Simulations into Hardware Systems Mohit Saxena, Yiying Zhang Michael M. Swift, Andrea C. Arpaci-Dusseau and Remzi H. Arpaci-Dusseau University of Wisconsin-Madison
Introduction to ARM LPC2148 Microcontroller
Introduction to ARM LPC2148 Microcontroller Dr.R.Sundaramurthy Department of EIE Pondicherry Engineering College Features of LPC2148 in a Nut Shell CPU = ARM 7 Core Word Length = 32 Bit ROM = 512 KB RAM
Introduction to ASIC Design
Introduction to ASIC Design Victor P. Nelson ELEC 5250/6250 CAD of Digital ICs Design & implementation of ASICs Oops Not these! Application-Specific Integrated Circuit (ASIC) Developed for a specific application
FA3 - i.mx51 Implementation + LTIB
Formation i.mx51 Implementation + LTIB: This course describes the i.mx51 multimedia processor and Linux Target Image Builder tool - Processeurs ARM: NXP ARM SoCs FA3 - i.mx51 Implementation + LTIB This
EMBEDDED HARDWARE. Core Board. ARM7 Development board. ARM7 Evaluation Board. Page 1 of 5
Core Board * Size: 71.2mm *50.8mm * Industrial grade 32-bit RISC micro-controller * Mass storage device support * Industrial grade 16C550 Serial Interface * 10/100M Industrial Ethernet interface * USB
NAND Flash-based Storage. Jin-Soo Kim Computer Systems Laboratory Sungkyunkwan University
NAND Flash-based Storage Jin-Soo Kim (jinsookim@skku.edu) Computer Systems Laboratory Sungkyunkwan University http://csl.skku.edu Today s Topics NAND flash memory Flash Translation Layer (FTL) OS implications
New System Solutions for Laser Printer Applications by Oreste Emanuele Zagano STMicroelectronics
New System Solutions for Laser Printer Applications by Oreste Emanuele Zagano STMicroelectronics Introduction Recently, the laser printer market has started to move away from custom OEM-designed 1 formatter
Designing with NXP i.mx8m SoC
Designing with NXP i.mx8m SoC Course Description Designing with NXP i.mx8m SoC is a 3 days deep dive training to the latest NXP application processor family. The first part of the course starts by overviewing
Lab 1. OMAP5912 Starter Kit (OSK5912)
Lab 1. OMAP5912 Starter Kit (OSK5912) Developing DSP Applications 1. Overview In addition to having an ARM926EJ-S core, the OMAP5912 processor has a C55x DSP core. The DSP core can be used by the ARM to
GLS87BP032G3/064G3/128G3/256G3/512G3/001T3 Industrial Temp SATA M.2 ArmourDrive PX Series
Features Industry Standard M.2 Serial ATA (SATA) Host Interface - SATA 1.5Gb/s, 3Gb/s and 6Gb/s - SATA Revision 3.2 - ATA/ATAPI-8 compliant - Supports 48-bit address feature set Performance - Sequential
FriendlyARM. Mini2440.
FriendlyARM Mini2440 www.friendlyarm.net 1 Introduction...3 1.1 Features...4 2 Hardware Resource...6 2.1 Jumpers and Interfaces...6 2.2 Memory Map...7 2.2.1 Memory Adress Allocation...7 2.3 Power Supply...8
Hi Hsiao-Lung Chan, Ph.D. Dept Electrical Engineering Chang Gung University, Taiwan
Processors Hi Hsiao-Lung Chan, Ph.D. Dept Electrical Engineering Chang Gung University, Taiwan chanhl@maili.cgu.edu.twcgu General-purpose p processor Control unit Controllerr Control/ status Datapath ALU
AN Migrating to the LPC1700 series
Rev. 01 6 October 2009 Application note Document information Info Keywords Abstract Content LPC1700, Migration, LPC2300/2400, ARM7, Cortex-M3 This application note introduces the important features of
Unblinding the OS to Optimize User-Perceived Flash SSD Latency
Unblinding the OS to Optimize User-Perceived Flash SSD Latency Woong Shin *, Jaehyun Park **, Heon Y. Yeom * * Seoul National University ** Arizona State University USENIX HotStorage 2016 Jun. 21, 2016
Datasheet. Embedded Storage Solutions. Industrial. SATA III 2.5 Solid State Drive. SED2FIV Series CSXXXXXRC-XX09XXXX. 04 Jul 2016 V1.
Embedded Storage Solutions Industrial SATA III 2.5 Solid State Drive SED2FIV Series CSXXXXXRC-XX09XXXX 1 Table of Contents 1. Product Description... 4 1.1. Product Overview... 4 1.2. Product Features...
Presented by: Nafiseh Mahmoudi Spring 2017
Presented by: Nafiseh Mahmoudi Spring 2017 Authors: Publication: Type: ACM Transactions on Storage (TOS), 2016 Research Paper 2 High speed data processing demands high storage I/O performance. Flash memory
CS311 Lecture 21: SRAM/DRAM/FLASH
S 14 L21-1 2014 CS311 Lecture 21: SRAM/DRAM/FLASH DARM part based on ISCA 2002 tutorial DRAM: Architectures, Interfaces, and Systems by Bruce Jacob and David Wang Jangwoo Kim (POSTECH) Thomas Wenisch (University
ESA Contract 18533/04/NL/JD
Date: 2006-05-15 Page: 1 EUROPEAN SPACE AGENCY CONTRACT REPORT The work described in this report was done under ESA contract. Responsibility for the contents resides in the author or organisation that
User Manual. LPC-StickView V3.0. for LPC-Stick (LPC2468) LPC2478-Stick LPC3250-Stick. Contents
User Manual LPC-StickView V3.0 for LPC-Stick (LPC2468) LPC2478-Stick LPC3250-Stick Contents 1 What is the LPC-Stick? 2 2 System Components 2 3 Installation 3 4 Updates 3 5 Starting the LPC-Stick View Software
Embest SOC8200 Single Board Computer
Embest SOC8200 Single Board Computer TI's AM3517 ARM Cortex A8 Microprocessors 600MHz ARM Cortex-A8 Core NEON SIMD Coprocessor POWERVR SGX Graphics Accelerator (AM3517 only) 16KB I-Cache, 16KB D-Cache,
Reference System: PLB DDR2 with OPB Central DMA Author: James Lucero
Application Note: Embedded Processing XAPP935 (v1.1) June 7, 2007 R Reference System: PLB DDR2 with OPB Central DMA Author: James Lucero Abstract This reference system demonstrates the functionality of
SPEAr: an HW/SW reconfigurable multi processor architecture
Welcome to the «SPEAr Age» Structured Processor Enhanced Architecture SPEAr: an HW/SW reconfigurable multi processor architecture COMPUTER PERIPHERAL GROUP Outline Economics of Moore s law and market view
UNC20 Module. User's Manual. D Breisach, Germany D Breisach, Germany Fax +49 (7667)
UNC20 Module User's Manual P.O: Box 1103 Kueferstrasse 8 Tel. +49 (7667) 908-0 sales@fsforth.de D-79200 Breisach, Germany D-79206 Breisach, Germany Fax +49 (7667) 908-200 http://www.fsforth.de Copyright
Memory Controller. Speaker: Tzu-Wei Tseng. Adopted from National Taiwan University SoC Design Laboratory. SOC Consortium Course Material
Memory Controller Speaker: Tzu-Wei Tseng Adopted from National Taiwan University SoC Design Laboratory SOC Consortium Course Material Goal of This Lab Familiarize with ARM memory interface Know ARM Integrator
SheevaPlug Development Kit Reference Design. Rev 1.2
SheevaPlug Development Kit Reference Design Rev 1.2 INTRODUCTION...4 SECTION 1 OVERVIEW...6 1.1 SHEEVAPLUG DESCRIPTION....6 Figure 1.1: SHEEVAPLUG Components and JTAG test card...6 Figure 1.2: SheevaPlug
S950 3U cpci Radiation Tolerant PowerPC SBC
S950 3U cpci Radiation Tolerant PowerPC SBC Designed for LEO, Mars Terrestrial with an Option for GEO Environments Single-Slot Conduction-Cooled 3U CompactPCI (cpci) Single Board Computer (SBC) High Performance
Experimental Results of Implementing NV Me-based Open Channel SSDs
Experimental Results of Implementing NV Me-based Open Channel SSDs Sangjin Lee, Yong Ho Song Hanyang University, Seoul, Korea Santa Clara, CA 1 OpenSSD Project Open source SSD for search and education
A ONE CHIP HARDENED SOLUTION FOR HIGH SPEED SPACEWIRE SYSTEM IMPLEMENTATIONS
A ONE CHIP HARDENED SOLUTION FOR HIGH SPEED SPACEWIRE SYSTEM IMPLEMENTATIONS Joseph R. Marshall, Richard W. Berger, Glenn P. Rakow Conference Contents Standards & Topology ASIC Program History ASIC Features
DTK2410 Specification
version 1.0 DIGNSYS Inc. FEATURES Hardware DTK2410 reference board Reference board for embedded application SAMSUNG S3C2410 MCU NOR/NAND Flash and SDRAM USB host and device UART interface JTAG interface
Introduction read-only memory random access memory
Memory Interface Introduction Simple or complex, every microprocessorbased system has a memory system. Almost all systems contain two main types of memory: read-only memory (ROM) and random access memory