Can MRAM be a factor for HPC?

Transcription

1 IC Power Consumption ITRS roadmap (W/cm2) Can MRAM be a factor for HPC? 1. Introduction 2. Can MRAM help? 3. Which MRAM? Logic is the major issue! Memory Wall High Performance Computing Current HPC! Pétaflops (1015 flop/s) Memory vs. CPU speed mismatch : Logic keeps awaiting Data! >MW overall operating power consumption + Same amount for cooling > 100m² area Memory Hierarchy VOLATILE CPU NON VOLATILE Registers CACHE MEMORY L1 Cache (SRAM) L2 Cache (SRAM) L3 Cache (SRAM / edram) 4 to 32 KB ~ns Up to 512 KB ~10 ns 4 to 8MB ~30 ns WORKING MEMORY >GB ~100 ns Random Access Memory (DRAM) SOLID STATE MEMORY Non Volatile (Flash) VIRTUAL MEMORY Storage memory (HDD) Towards Exaflop (1018 Flops/s) requires drastic increase of compactness and energy efficiency! Logic issue is becoming a memory issue

2 Logic Power Losses Static Loss : Current leakage Gate-Channel tunneling Dynamic Loss : Interconnects capacitance and Joule heating Source-Drain leakage (direct tunneling) Can MRAM be of any help? Technology 90nm 65nm 45nm 32nm 22nm # transistors Wire length ~10km ~30km ~ 100km ~ 300km The (Memory) Holy Grail Why MRAM? " Non-Volatile to save data while logic OFF Non-volatile like Flash 10+ years retention Dense like DRAM 10F 2, small overheads Fast Like SRAM ~10ns in normal mode High Endurance like SRAM / DRAM cycles, up to " Low active power " Fast enough to match logic speed " Infinitely endurant to act as cache " Easy to embedd within logic " With minimal wire length to minimize dynamic (RC) loss " Single technology to answer multiple needs (RAM, ROM, Store) MRAM is not the best but Can replace SRAM at 1/6th of size, zero leakage Can replace e-flash at >10 5 x speed, lower power Can replace DRAM (if running out of steam)

3 An easy to embed memory - «End-of-back-end» process (above-ic) MRAM cell - Cell R compatible with CMOS (~ kω ) - V dd driven switching - No charge pumps required - No trade-off with logic process - Cheap (only 3 add-masks) CMOS Logic MRAM Cache Janus architecture Option 1 : DRAM & L2,L3 cache same overall architecture Option 2 : Memory blocks distributed within (above) logic core(s) Logic-In Memory concept - First introduced in 1969 VOLATILE NON VOLATILE CPU Registers CACHE MEMORY L1 Cache (SRAM) L2 Cache (SRAM) L3 Cache (SRAM / edram) WORKING MEMORY CPU NV-Registers CACHE MEMORY L1 (SRAM/MRAM) L2 Cache (MRAM) Level 3 Cache (MRAM) WORKING MEMORY Chip Random Access Memory (DRAM) Random Access Memory (MRAM) SOLID STATE MEMORY SOLID STATE MEMORY Non Volatile (Flash) Non Volatile (Flash) VIRTUAL MEMORY VIRTUAL MEMORY Storage memory (HDD) Storage memory (HDD) Reduced Static power, (NV cache, no DRAM refresh) Reduced silicon footprint Multiple / short interconnects Distributed memory within logic! Faster memory-logic communication Reduced dynamic power Advanced power management High data resilience

4 evaderis STT-based MCU for the IoT Hybrid CMOS-MRAM logic Energy Battery Sensor Wireless Controle r Connected Object Off-Chip Processing-Storage Energy On-Chip Processing-Storage Near-zero standby Performances, Intelligence (computing, amount of data) 10% Autonomy (battery life,co2) NVRM everywhere Non-volatile data-centric control processor 10 to 100X less energy translates into extended lifetime, more intelligence, less CO2 Option 3 : Non-volatility inside logic blocks (NV-Flip-flop, NV-latch, ) VOLATILE NON VOLATILE CPU NV-Registers CACHE MEMORY L1 (SRAM/MRAM) L2 Cache (MRAM) Level 3 Cache (MRAM) WORKING MEMORY Random Access Memory (MRAM) SOLID STATE MEMORY Non Volatile (Flash) VIRTUAL MEMORY Storage memory (HDD) Fast save / restore of logic states! «Normally-OFF / Instant-ON Computing CPU NV-Registers CACHE MEMORY L1 (SRAM/MRAM) L2 Cache (MRAM) Level 3 Cache (MRAM) WORKING MEMORY Random Access Memory (MRAM) SOLID STATE MEMORY Non Volatile (Flash) VIRTUAL MEMORY Storage memory (HDD) evaderis STT-based MCU NV Flip-Flop User Case 19 Mb MRAM + 1Mb SRAM 10 6 scalar measures 32 uncompressed 320x240 grayscale pictures (security standard) 5 Jan 2009 Divide by 3 to 100 (depends on data profile) Balance of RF gain and on-chip process cost Relative Energy Divide by 10 5 >1000 X faster then Flash Divide by 10 to to 100 X faster (parallelized boot from distributed memory blocks) Divide by 10 to 100 Instant on! full shutoff (no more sleep/deep sleep states) Near Zero Send Store Wake-up Sleep Standby

5 Rad-Hard NV Look-up Table There Are Many MRAMS! " DRAM%based+Configura3on+memory+ Field-driven Toggle STT (SPRAM) Planar Perpendicular DW motion " Periodic+refresh+of+DRAM+using+MRAM+ content+(scrubbing)+ " Advantages:++ " High+density+(DRAM)+ " No+redundancy+required+ " Shadowed+reconfigura3on+ " Low+power+(non%vola3le)+ Thermally Assisted (TAS) STT-TAS OST (Precessional) SOT (Spin-Orbit Torque) " Implemented+ on+ hybrid+ TowerJazz+ 130nm+CMOS+/+Crocus+MRAM+process+ The Magnetic Tunnel Junction (MTJ) Which MRAM? Giant&(Tunneling)&Magnetoresistance& Ac#ng&on&current&through&magne#za#on& Parallel+ 0 ++%++Low+R+ An3parallel+ 1 +%+High+R+ Hard mask Ta Etch stop layer Ru Capping layer Ta Storage layer CoFeB Tunnel barrier (MgO) Reference layer CoFeB Spacer (Ta) 1Kb Ferrite core Control Data Corp (1965) 1Mb Bubble memory Intel (1980) 16Kb AMR Honeywell (1984) 4Mb Toggle Everspin (2004) 64Mb STT Hynix (2010) R H R R TMR = R Pinning layer (Pt/Co) n Ru (MgO(Pt/Co) n Seed layer Pt Smoothing layer Ta/CuN/Ta Base electrode

6 MRAM (Read) Why STT MRAM? Field-driven MRAM STT MRAM 1T-1R architecture Logic state = Magnetization (resistance) state 10 0 Smallest cell size Lowest current Full scalability Normalised Count Rmin >25σ Rmax 2X Address Data out (R high ) Resistance Figure of merit is ΔR/σ not ΔR Data ref Data out (R low ) Field-Driven MRAM What is STT? Use current pulses to generate overlapping magnetic fields at word/bit line crosspoint Spin&Transfer&Torque&(STT)& Ac#ng&on&magne#za#on&through&current& Current%only+ switching++ (no+field)+ Field term (precession) Gilbert Damping Spin torque (antidamping) Transistor OFF Large cell size (30F²) High power (2x16 ma / bit) Low speed (35ns R/W) Not scalable dm dt = γm ( H eff + bi.m p ) +γai.m ( M M p ) +αm dm dt Zeeman Field-torque Spin-torque Gilbert Damping

7 Why perpendicular? STT-MRAM is now becoming real! Q3, 2014 Q3, 2014 Switching probability P± = 1 e Thermal stability factor Δ= t τ± K eff V k BT τ = τ 0e Δ k BT Barrier to switching Thermal activation plan K eff = K v 2π M s2! 4e $ α kbt! π M s2v $ jcplan = # & #Δ + & "! % g(0)pa " k BT % Critical current α = damping P = polarization A = Area g(0)~1 τ0 = 10-9s perp K eff = (K s1 + K s2 ) t + Kv! 4e $ α kbt jcperp = # & Δ "! % g(0)pa Q4, 2014 P-STT MRAM Demo How Fast Can STT-MRAM Be? I c I c0 1 τ " kt τ % I c I c0 = $1 B ln ' E τ0 & # 50ns 10ns

8 Thermally Activated Switching Precessional STT demo Marins de castro Sousa et al, Journal of Applied Physics 111 (2012) 07C912 Liu et al, APL97, (2010) Γ!" = a j M!"! (P!" M!"! ) Transmitted voltage (mv) Stochastic reversal Incubation time preceding a large thermal fluctuation Devolder et al., Phys. Rev. Let. vol 100 (2008) Time after pulse (ns) Switching Probability mV 562mV 631mV centered bias 631mV AP bias 631mV P bias mV Pulse width (ns)! In-plane precession! Ultrafast deterministic switching.! ultra low power (switching with 90 fj) Precessional STT (Orthogonal Spin Torque OST) Spin Orbit Torque (SOT) MRAM d M dt 2 STT contributions α d M 0 M H eff + M + a ja M ( A M ) + a jp M ( P M M S dt = γ ) AlO x &2&nm& Co&0.5+nm& Pt&3&nm& H EFF ~&M H R& M+ H R + Reference&& Layer+ MgO Free&& Layer++ MgO Perpendicular&& Polarizer++ P A &STT&from&reference&layer&A&:&& &&&&&Bipolar&switching&of&free&layer&magne>za>on& &STT&from&Perpendicular&polarizer&P:&& &&&&&Precession&of&free&layer&magne>za>on& -If a jp >>a ja (perpendicular Polarizer dominates) Steady Precessions (e.g. RF devices) " ++3%Terminals+ " Infinite+Endurance+/+Reliability++ " +Independent+Read+and+Write+paths+ o +Adjustable+Impedance++ o +Maximized+TMR+ Fast+Read+ o +No+read+disturb+ -If a ja >>a jp (in-plane Analyzer dominates) +Bipolar non-oscillatory switching (e.g. memory) " +High+speed+?+ 30

9 SOT Fast Switching Moore s Law SRAM cell size Core technology End-Users 65nm (2005) 0.6 µm2 45nm (2007) 0.35 µm2 32nm (2009) 0.17 µm2 22nm (2011) 0.1 µm2 14nm (2014) 0.06 µm2 90nm (2003) 1 µm2 Models Tools IDM Foundries

10 Memory Hierarchy (Almost) All Non-Volatile Data Path! Technology enabler : The STT-RAM MCU / SoC Implementation 10-9 MRAM+performances+may+be+tuned+by+shape+/+size+(same+core+technology) ! Replace&simultaneously&mul>ple&memory&instances& Energy(J/bit) Endurance (# cycles) Write speed (sec) Write speed (sec)

11 NV LUT silicon demonstrator " Hybrid&TowerJazz&130nm&CMOS&/&CrocusVMRAM&process& & " Digital&Test&at&Spintec& " MRAM&programming&and&input&transferred&to&DRAM&& " All&inputs&combina>ons&tested&and&corresponding&output&checked& Process Speed Power Retention