Enabling success from the center of technology. Xilinx DSP Model-Based Design Solutions

Transcription

1 Xilinx DSP Model-Based Design Solutions

2 Course Goals 2 Present the integrated Xilinx model-based DSP design flows and their benefits Demonstrate how AccelDSP explores and implements a MATLAB design in a Xilinx FPGA Show how System Generator 9.1 uses Simulink to integrate system-level designs into FPGA hardware

3 Agenda 3 Why use FPGAs for DSP? Model-based design concepts Xilinx DSP tool flows AccelDSP 9.1 Demo System Generator 9.1 Demo Synplify DSP Overview Summary & Questions

4 Agenda 4 Why use FPGAs for DSP? Model-based design concepts Xilinx DSP tool flows AccelDSP 9.1 Demo System Generator 9.1 Demo Synplify DSP Overview Summary & Questions

5 DSP Performance Gap 5 Performance (GMACs*) (Algorithmic and Processor Forecast) 350 GMACs 30 GMACs 1 GMACs Algorithm Complexity Shannon s Law DSP/GPP Performance Limit Virtex-DSP Spartan-DSP 3D Medical Imaging Base Stations HD Audio/Video Broadcast Radar & Sonar HD Video Surveillance Mounted Software Defined Radio MIMO Ultrasound Pico/Femto Base Stations Consumer Video Video Surveillance Mobile Software Defined Radio Source: Jan Rabaey BWRC * 18x18 multiply and 48-bit accumulate Time

6 Power of Parallel Processing. 6 Programmable DSP FPGA - Sequential - Fully Parallel Implementation Data In In Reg Reg Reg Reg Reg Reg Reg Reg Coefficients 256 clock cycles needed X C0 + Reg Data Out 1 GHz 256 clock cycles X MAC Unit + C1 Reg C0 X C2 400 MHz = 4 MSPS 1 clock cycle X C3 X C Reg Reg = 400 MSPS Reg Reg X Data Out 256-tap filter implementation is 100 times faster

7 Xilinx Enabling Technology. 7 ECC and Interconnect 18 Kbit FIFO Logic 18 Kbit Dual-Port Block RAM / FIFO up to 10Mbits DSP Slices Up to 640 at 550MHz = 500MSPS Tri-Mode Ethernet Clock Management 550 MHz DCM + PLL DCM DCM PLL

8 Virtex-5 SXT / Spartan-DSP Family 8 Logic Cells DSP48E Slices Block Memory (kbits) Clock Mgmt Tiles PCI Express Endpoint Blocks Ethernet MAC Blocks GTP 3.2Gbps Transceivers XC5VSX35T 34, XC5VSX50T 52, XC5VSX95T 94, Logic Cells DSP48A Slices Block Memory (kbits) XC3SD1800A 37, ,512 XC3SD3400A 53, ,268

9 Agenda 9 Why use FPGAs for DSP? Model-based design concepts Xilinx DSP tool flows AccelDSP 9.1 Demo System Generator 9.1 Demo Synplify DSP Overview Summary & Questions

10 Problems in Traditional Development 10 Requirements and Specifications Design Implementation Test and Verification Text-based - Prevents rapid iteration Simulation - Incomplete and expensive Manual coding - Introduces human errors Traditional testing - Errors found too late

11 Advantages of Model-Based Design. 11 Requirements and Specifications Design Implementation Test and Verification Model elaboration Continuous verification Executable Models Simulation Automatic Code Generation Test with Design

12 The Platform For Model-Based Design. 12 The leading environment for technical computing The leading environment for modeling, simulating, and implementing dynamic and embedded systems

13 Model-Based Design Environment 13 Blocksets (video, comms, etc.) Real-time Workshop Toolboxes (signal, comms, etc.) ANSI C for MCUs & DSPs HDL for Xilinx FPGAs

14 Agenda 14 Why use FPGAs for DSP? Model-based design concepts Xilinx DSP tool flows AccelDSP 9.1 Demo System Generator 9.1 Demo Synplify DSP Overview Summary & Questions

15 Xilinx Model Based Flows 15 MATLAB Simulink w/ System Generator Generate

16 Challenges In Moving Algorithms to Silicon 16 Design problem - Kalman Filters Commonly used for Satellite tracking, robotics, position and velocity systems Complexity depends on size of system being estimated Linear algebra Matrix operations How do you move this model into an FPGA? On paper MATLAB Plot

17 Benefits of AccelDSP Automates manual steps Provides ability to analyze design tradeoffs at each stage Integrated design environment Manual Design Steps Floating-Pt. Algorithm Fixed-Point Conversion Architecture Definition Create / Integrate IP Blocks Create RTL Design Refine Architecture Verify RTL RTL Synthesis Steps performed by AccelDSP Floating-Pt. Algorithm AccelDSP / AccelWare RTL Synthesis AccelDSP Design Flow

18 Fixed-Point Conversion 18 Automatically generates a fixed-point model from the floating-point model The floating-point model is treated as Golden Source User interactive and controllable Fixed-point analysis tools Addresses reduced-precision arithmetic errors Accel_probe overlays both floating-point and fixed-point

19 Design Architecture Information 19 Summary highlights areas available for design exploration Alternative architectures Loops that can be rolled and unrolled Alternative Architectures Loops

20 Destination Based Flows 20 AccelDSP compiles to multiple destinations ISE System Generator HW Co-Simulation ISE System Generator HW Co-Sim Intelligent Flow Bar automatically takes the user to the appropriate step in the design flow

21 Vector and Matrix Multiply Operations 21 The computational power of MATLAB is its ability to handle linear algebra AccelDSP understands matrices and vectors natively Allows designer to quickly evaluate both parallel and resourceshared (rolled) implementations a * b = c

22 AccelDSP 9.1 DEMO 22 Kalman Filter Simply an optimal recursive data processing algorithm All matrix operations all the time Predict Enter loop Update Compute filter gain Measurement Project One Step Ahead Update filter estimate Update filter error covariance matrix

23 Separate the Hardware Part into a Function 23 MATLAB.m file %Kalman filter example rand('state',0); t=0:0.001:2; A(:,1) = cos(0:pi/400:(5/3)*pi)/2; A(:,2) = sin(0:pi/200:(10/3)*pi)/2; A(:,3) = sin(0:pi/100:(20/3)*pi)/2; A_in = A + 0.5*(rand(size(A))-.5); DIM = size(a,2); LEN = size(a,1); DIM = size(a,2); I = eye(dim); R = [ ; ; ]; P_cap_est = P_cap+I; % correction step: K = P_cap_est * inv(p_cap_est+r); p = p + K * (A' - p); P_cap = (I - K)*P_cap_est; S = p'; Block diagram view Script File Design Function %Kalman filter example rand('state',0); t=0:0.001:2; A(:,1) = cos(0:pi/400:(5/3)*pi)/2; A(:,2) = sin(0:pi/200:(10/3)*pi)/2; A(:,3) = sin(0:pi/100:(20/3)*pi)/2; A_in = A + 0.5*(rand(size(A))-.5); DIM = size(a,2); LEN = size(a,1); for i = 1:LEN [S(i,:)] = kalman_filter(a_in(i,:)); end function [S] = kalman_filter(a) DIM = size(a,2); persistent p P_cap if isempty(p_cap) P_cap = [8 0 0;0 8 0; 0 0 8]; p = ones(dim,1)/2; end; I = eye(dim); R = [ ; ; ]; P_cap_est = P_cap+I; MATLAB Stimulus DUT (design function) MATLAB Analysis % correction step: K = P_cap_est * inv(p_cap_est+r); p = p + K * (A' - p); P_cap = (I - K)*P_cap_est; S = p';

24 Steps Needed For Demo Designer parses MATLAB into separate files a) Script (non-synthesizable) b) Design function (synthesizable) MATLAB environment 2. Verify script file in floating point 3. Analyze is it synthesizable? 4. Generate fixed point model (MATLAB) 5. Explore architectural options 6. Verify fixed point model (MATLAB) 7. Generate RTL a) VHDL and testbench 8. Verify RTL simulate in ISIM 9. Generate System Generator block AccelDSP environment

25 Agenda 25 Why use FPGAs for DSP? Model-based design concepts Xilinx DSP tool flows AccelDSP 9.1 Demo System Generator 9.1 Demo Synplify DSP Overview Summary & Questions

26 Agenda 26 Why use FPGAs for DSP? Model-based design concepts Xilinx DSP tool flows AccelDSP 9.1 Demo System Generator 9.1 Demo Synplify DSP Overview Summary & Questions

27 Xilinx Model Based Flows 27 MATLAB AccelDSP Simulink w/ System Generator Generate

28 System Generator Integration.. Design DSP applications in FPGAs without hardware design experience 28 Xilinx Reference Designs Parameterize IP Blocks Embed MATLAB m-code Integrate VHDL or Verilog code Import AccelDSP designs Library of over 90 Xilinx optimized DSP building blocks

29 FIR Filter Generation 29 FIR Compiler quickly generates performance optimized FIR filters Automatically implements DSP48 blocks to achieve up to 550 MHz performance in Virtex-5 Supports multi-rate, oversampled, multi-channel and coefficient optimization MathWorks FDA Tool integration provides graphical filter design and coefficient generation FIR Compiler FDA Tool

30 Embedded Processor Design 30 DSP system can be quickly implemented as a peripheral to a Xilinx embedded processor Integration to Xilinx Platform Studio Interface details abstracted away through a shared memory interface System Generator PLB Arbiter Embedded Processor Instruction Data PLB-OPB Bridge IP Core... IP Core On-chip Peripheral Bus (OPB) OPB Arbiter Platform Studio High-Speed DSP Block Memory Controller UART Memory Controller FPGA High-speed Data Converters DDR/DDR2 Memory RS232 Connector Flash Platform Studio pcore

31 Automatic HW/SW Interface Generation 31 Includes the software API and hardware components of a processor-to-peripheral interface Traditionally requires both HW and SW design skills Time consuming even for experienced designers System Generator automatically generates the HW/SW interface Software HW / SW Interface DSP Hardware SW API HW Interface C Program Driver Files Header Files Memory Map / Address decode Hardware Interface Logic RTL

32 Hardware Co-Simulation 32 Automated HW Co-Simulation Up to 1000x simulation performance improvement Push-button flows target over 20 commercially available evaluation boards Design Simulation Time (Seconds) Software HW Co-Sim Increase Beamformer X OFDM BER Test X DUC CFR X Color Space Converter x Video Scalar X

33 What s New in System Generator 9.1? 33 New device support Complete Virtex-5 support in version 9.1 Complete Spartan-DSP support in Service Pack 1 HW Co-Simulation BSPs for new evaluation boards Virtex-5 LX Evaluation Kit Virtex-5 LXT/SXT Evaluation Board Spartan-DSP Co-Processing Starter Kit ML506 with Virtex-5 SXT50T Spartan-DSP Starter Kit

34 Enabling IP & Reference Designs 34 Digital Communications Digital pre-distortion (DPD) WiMAX (IEEE802.16e) Digital Front End WCDMA Digital Front End J.83Modulator, A/C and B IP cores Video & Imaging Video Surveillance (VoP) Video Blockset Polyphase Scaler Color Space Converter - RGB2YCrCb and YCrCb2RGB Chroma Resampler 2D FIR Filter 2D Rank Filter

35 Complete Digital Front End (DFE) Radio Design 35 Advantages Over Traditional Multi-Chip Solutions Multi-gigabit transceivers allow lower cost single chip DFE solution 30% lower power reduces PSU costs and increases reliability Higher frequency reduces cost / channel $4 300mW CPRI SERDES (Discrete PHY x2) $29 1W DSP Processing 4 ch DUC $50 2.0W DSP Processing 8 ch DDC $ W CFR Processor $40 2.0W DPD Stand-alone ASSP DAC ADC ADC ADC

36 Agenda 36 Why use FPGAs for DSP? Model-based design concepts Xilinx DSP tool flows AccelDSP 9.1 Demo System Generator 9.1 Demo Synplify DSP Overview Summary & Questions

37 System Generator 9.1 Demo Integrate and simulate AccelDSP design from first demo in a System Generator model 2. Generate Digital Front End (DFE) decimating filter using FIR Filter Compiler and FDA Tool Demonstrate Hardware Co-Simulation over Gigabit Ethernet on Avnet s Virtex-5 LX50 evaluation platform Sampled IF Input cos DDS sin LPF 5 LPF LPF 5 LPF I Q Sample Rates 100 MSPS 20 MSPS

38 Agenda 38 Why use FPGAs for DSP? Model-based design concepts Xilinx DSP tool flows AccelDSP 9.1 Demo System Generator 9.1 Demo Synplify DSP Overview Summary & Questions

39 Synplicity s Synplify DSP 39 Model-based Design Flow Simulink-based environment Floating to fixed-point conversion Integrated flow using Synplify Pro Full RTL Generation Unique System Optimization Explore multiple architectures Retiming for performance Folding for area (cost) Multi-channelization for productivity HDL Co-Simulation Export to System Generator Synplify DSP Blockset Simulink Synplify DSP Synthesis Engine RTL Synplify Pro

40 Synplify DSP Design Optimizations 40 System-level Retiming System level re-timing/pipeline insertions Improves performance c1 c2 c3 x x x Rst Rst D Q + D Q + c1 c2 c3 x x x Rst Rst Rst D Q + DD Q QRst + D QRst En En En D Q En En Automatic Multi-channel capability Creates a multi-channel system from a single channel spec Quickly determine optimal number of channels before implementation En Folding Fast, accurate speed-area tradeoffs Shares resources like multipliers Enables optimization of high-volume designs for cost En c1 c2 c3 x x x Rst Rst Rst D Q + D Rst Rst Q Rst D Q D Q + D Q D Q En En En En En En

41 Agenda 41 Why use FPGAs for DSP? Model-based design concepts Xilinx DSP tool flows AccelDSP 9.1 Demo System Generator 9.1 Demo Synplify DSP Overview Summary & Questions

42 Part of Xilinx s Complete DSP Solution 42 AccelDSP One golden MATLAB source Floating- to-fixed-point conversion Design exploration Algorithm exploration Automated verification System Generator integration MATLAB System Generator Simulink-based design Mixed language design environment Over 90 optimized Xilinx DSP blocks

43 Minimum Tool Requirements 43 System Generator Flow System Generator $ 995 MATLAB $ 1,900 Simulink $ 2,800 Total: $ 5,695 AccelDSP Flow MathWorks DSP Recommended Options Signal Processing Toolbox $ 800 Signal Processing Blockset $ 1,000 Communications Toolbox $ 1,000 Communications Blockset $ 1,000 AccelDSP $ 4,995 MATLAB $ 1,900 Total: $ 6,895 All tools require the Xilinx ISE software for implementation Prices shown are suggested list USD

44 What s Next 44 Contact your Avnet FAE Take home the software Evaluation copies of MATLAB/Simulink on your CDs Download Xilinx tools at 30 day trial of AccelDSP 60 day trial of System Generator Get evaluation boards Avnet bundles available for all X-Fest attendees Attend Avnet s Fall Speedway workshops

45 Appendix

46 XtremeDSP Device Portfolio 46 Spartan-DSP Virtex-DSP Spartan-3A DSP Virtex-4 SX Virtex-5 SXT 3SD1800A 3SD3400A V4VSX25 4VSX35 4VSX55 5VSX35T 5VSX50T 5VSX95T DSP Performance (GMAC/s) Max Block RAM Memory Bandwidth (Gbps) 1, , , , , , , ,325 2 Max DSP Frequency (MHz) XtremeDSP DSP48* Slices Min Footprint (mm) 19x19 19x19 27x27 27x27 27x27 27x27 27x27 27x27 Distributed RAM (Kb) ,520 Block RAM (Kb) 1,512 2,268 2,304 3,456 5,760 3,024 4,752 8,784 Logic Cells 37,440 53, ,040 34,560 55, , , ,208 High Speed Connectivity 227 x 622+ Mb/s LVDS pairs 213 x 622+ Mb/s LVDS pairs 120 x 1+ Gb/s LVDS pairs 224 x 1+ Gb/s LVDS pairs 360 x 1+ Gb/s LVDS pairs 180 x 1.25 Gb/s LVDS pairs, 8 x 3.2 Gb/s Transceivers 240 x 1.25 Gb/s LVDS pairs, 12 x 3.2 Gb/s Transceivers 320 x 1.25Gb/s LVDS pairs, 16 x 3.2 Gb/s Transceivers 1 In Slow Speed Grade 2 In Fast Speed Grade

47 DSP48 Comparison 47 Function DSP48 DSP48E DSP48A Benefit Multiplier 18 x x x 18 Reduces FPGA resource needs for DSP algorithms. Pre-Adder No No Yes Reduces the critical path timing in FIR filter applications better performance. Import in FIR filter construction. Cascade Inputs One Two One Enables fast data path chaining of DSP48 blocks for larger filters. Cascade Output Yes Yes Yes Enables fast data path chaining of DSP48 blocks for larger filters. Dedicated C input No Yes Yes The C input supports many 3-input mathematical functions, such as 3-input addition and 2- input multiplication with a single addition and the very valuable rounding of multiplication away from zero. Adder 3 input 48 bit 3 input 48 bit 2 input 48 bit Supports simple add and accumulate functions. Dynamic Opmodes Yes Yes Yes One DSP48 can now provide more than one function.. Multiply, Multiply-add, multiplyaccumulate etc. ALU Logic Functions No Yes No Similar to the ALU of a microprocessor. Enables the selection of ALU function on a clock cycle basis Enables multiple functions to be selected. (Add, Subtract, or Compare) Pattern Detect No Yes No This feature supports convergent rounding, underflow/overflow detection for saturation arithmetic, and auto-resetting counters/accumulators. SIMD ALU Support No Yes No Enables parallel ALU operations on multiple data sets. Carry Signals Carry In Carry In & Out Carry In & Out Supports fast carry functions between DSP blocks. Often a speed limiting path.

48 IP Support in CIC Compiler (Sept 2007) DDS Compiler FFT FIR Compiler RS Encoder/Decoder Viterbi v6.0 Convolutional Encoder Interleaver/Deinterleaver Multiplier BaseBlox Block Memory Generator Distributed Memory Generator FIFO Virtex-5 & Spartan-DSP v1.0 v1.1 v4.1 v3.0 v6.0 v6.0 v6.0 v5.0 V10 v9.1 v2.4 v3.3 v3.3

49 Avnet Virtex-5 LX Development Platform 49 Board features XC5VLX50-1FF676 16M x 32 DDR2 4M x 16 of Flash 10/100/1000 PHY 10-bit LVDS Rx and Tx Cypress USB 2.0 RS232 Serial Port EXP Expansion Slot Clocks Programmable LVDS 100 MHz LVTTL Oscillator LVTTL Oscillator Socket 32P Platform Flash JTAG Port BPI Configuration SystemACE interface

50 Point-to-Point Hardware Co-Simulation 50 Tri-mode point-to-point Ethernet Co-simulation Configuration over JTAG / Co-simulation over Ethernet HOST System Generator for DSP PPEthernetCosim Engine Userspace WinPcap Ethernet NIC Driver OS Kernel Ethernet NIC Dedicated Point -to-point Connection Ethernet PHY Ethernet TEMAC MAC Core Filter Ingress Egress Unit Unit BPF Filter FPGA Clock Generation Hardware In -the-loop Co -simulation BRAMs BRAMs Design Under Test Control FPGA Configuration Ethernet Co -simulation Command Processor Interface Command Processor Hardware Co-simulation Interface