Samsung K9GAG08U0M-PCB0 16 Gbit Multi-Level Cell (MLC) 51 nm Process Technology NAND Flash Memory
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1 Samsung K9GAG08U0M-PCB0 16 Gbit Multi-Level Cell (MLC) 51 nm Process Technology NAND Flash Memory Structural Analysis with Additional Layout Feature Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: Fax:
2 Structural Analysis Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 1.7 Comparison to Samsung 8 Gbit MLC 60 nm Process NAND Flash 2 Device Overview 2.1 Package and Die 2.2 Die Features 3 Process 3.1 General Device Structure 3.2 Bond Pads 3.3 Dielectrics 3.4 Metallization 3.5 Vias and Contacts 3.6 Logic Transistors and Poly 3.7 High Voltage MOS Transistors 3.8 Fuses 3.9 Isolation 3.10 Wells and Substrate 4 NAND Flash Cell Analysis 4.1 Overview 4.2 NAND Flash Plan View Analysis 4.3 NAND Flash Cross-Sectional Analysis (Parallel to Bitline) 4.4 NAND Flash Cross-Sectional Analysis (Parallel to Wordline) 5 Selected Layout and Lithography Analysis 5.1 Overview 5.2 Selected NAND Flash Array Features 5.3 Selected Process Lithography
3 Structural Analysis 6 Materials Analysis 6.1 Overview 6.2 TEM-EDS Analysis of Dielectrics 6.3 TEM-EDS Analysis of Metallization and Contacts 6.4 TEM-EDS Analysis of Transistors and Contacts 7 Critical Dimensions 7.1 Vertical Dimensions 7.2 Horizontal Dimensions 8 Statement of Measurement Uncertainty and Scope Variation 9 References About Chipworks
4 Overview Overview 1.1 List of Figures 2 Device Overview Package Photograph Top Package Photograph Bottom Package X-Ray Side View Package X-Ray Plan View Die Photograph Die Markings Metal 1 Die Photograph Annotated Die Photograph Analysis Sites Die Corner A Die Corner B Die Corner C Die Corner D Minimum Pitch Bond Pads 3 Process General Device Structure Die Edge and Wafer Thickness Die Seal Overview Die Seal Bond Pad Overview Bond Pad Edge Passivation Silicon Nitride Passivation 2 TEM IMD IMD 2 TEM IMD IMD 1 TEM PMD PMD TEM Minimum Pitch Metal Metal 3 Composition TEM Minimum Pitch Metal 2 TEM End of Metal 2 Line TEM Metal Peripheral Routing Metal 1 Pitch TEM Metal 1 W Thickness Variation (TEM) Metal 1 Pitch in Logic Regions Minimum Pitch Metal 1 (Memory Array) Metal Minimum Pitch Via 2s Via 2 Overview TEM Via 2 Bottom TEM 2
5 Overview Minimum Pitch Via 1s Minimum Pitch Via 1s (Neighboring Lines) Via 1 Overview TEM Top of Via 1 TEM Bottom of Via 1 TEM Minimum Pitch Contacts to Metal 0 and Poly Contacts to Metal 0 and Poly TEM Metal 0/Poly Interface TEM Minimum Pitch Contacts to Diffusion (Periphery) Contacts to Diffusion (TEM, Periphery) Minimum Pitch Contacts (Memory Array) Bitline Contact TEM Top of Bitline Contact TEM Bitline Contact/Diffusion Interface TEM Sourceline Contact Sourceline/Diffusion Interface Interpoly Via MOS Transistor Overview Glass Etch MOS Transistors Plan View Minimum Gate Length NMOS Transistors Minimum Gate Length PMOS Transistors Minimum Pitch Poly Periphery MOS Transistor Overview TEM ONO Interpoly Dielectric MOS Transistor Interpoly Via (TEM) Logic Gate Oxide TEM HV-NMOS Gate HVMOS Substrate Doping SCM Fuse Overview Detail of Fuses SEM Peripheral STI Thickness Top of STI TEM Minimum Width Peripheral STI NAND Flash Array STI Thickness NAND Flash Array Minimum Pitch STI (TEM) NAND Flash Array Embedded P-Well SCM SRP Analysis Sites A and B SRP Analysis Site C SRP of Array Wells and Substrate Doping (A) SRP Detail of Array Wells (A) SRP of Channel Stop Implant (B) SRP of Peripheral P-Well (C) 2
6 Overview NAND Flash Cell Analysis NAND Flash Array Metal NAND Flash Array Metal NAND Flash Array Metal NAND Flash Array Metal 1 Bitlines NAND Flash Array Sourceline Contacts NAND Flash Array Poly 2 Wordlines NAND Flash Array Poly 1 Floating Gates and Diffusion Detail of Poly 1 Floating Gates NAND Flash Array Overview Parallel to Bitline Bitline Select Transistors Bitline Contact TEM Sourceline Select Transistors Sourceline Contact TEM Floating Gate Transistors Stack TEM Cell Transistors Minimum Width Poly (TEM) Tunnel Oxide TEM NAND Flash Array Overview Parallel to Wordline Wordline, Floating Gates, and STI Floating Gate Overview TEM Detail of Floating Gates TEM Shallow STI TEM ONO Interpoly Dielectric TEM Tunnel Oxide TEM Bitline Contacts Sourceline 5 Selected Layout and Lithography Analysis Analysis Sites Wordline Driver Region, Metal 1 (C) Metal 1 Patterning Edge of Poly Wordlines (C) Detail of Metal 1 Patterning Edge of Poly Wordlines (C) Wordline Contacts Poly, Right Side (C) End of Wordlines Poly, Left Side (A) Wordline Driver Overview Poly (C) Detail of Wordline Drivers Poly (C) Bitline Driver Overview Poly (B) Detail of Bitline Drivers Poly (B) Page Buffer Circuitry Overview (B) M1 Lines and Spaces Additional M1 Lines and Spaces Periodic Break in Metal 1 Bitlines Array Edge Detail of Edge of M1 Bitlines Metal 1 Bitline Line Edge Roughness (LER) 2
7 Overview Materials Analysis TEM-EDS Spectra of Passivation Sub Layers TEM-EDS Spectra of IMD 2 Sub Layers TEM-EDS Spectra of IMD 1 Sub Layers TEM-EDS Spectrum of PMD TEM-EDS Spectrum of STI TEM-EDS Spectrum of M2 Cap TEM-EDS Spectrum of M2 Barrier TEM-EDS Spectrum of Metal 1 Body TEM-EDS Spectrum of Metal 1 Barrier TEM-EDS Spectrum of Poly 3 Silicide TEM-EDS Spectrum of Contact Liner TEM-EDS Spectrum of Silicon Channel Region 1.2 List of Tables 1 Overview Device Identification Device Summary Process Summary Comparison to Previous Generation Samsung MLC NAND Flash 3 Process Measured Dielectric Thicknesses Metallization Measured Vertical Dimensions Metallization Measured Horizontal Dimensions Via and Contact Measured Dimensions Peripheral Transistor Horizontal Dimensions Transistor and Polycide Vertical Dimensions STI Measured Dimensions Measured Well Depths and Die Thickness 4 NAND Flash Cell Analysis NAND Flash Cell Critical Dimensions 5 Selected Layout and Lithography Analysis Metal 1 Bitline Line Edge Roughness 7 Critical Dimensions Dielectric Vertical Dimensions Metallization Vertical Dimensions Peripheral Transistor and Polycide Vertical Dimensions Well Depths and Die Thickness Metallization Horizontal Dimensions Via and Contact Horizontal Dimensions Peripheral Transistor Horizontal Dimensions STI Horizontal Dimensions 2
8 About Chipworks Chipworks is the recognized leader in reverse engineering and patent infringement analysis of semiconductors and electronic systems. The company s ability to analyze the circuitry and physical composition of these systems makes them a key partner in the success of the world s largest semiconductor and microelectronics companies. Intellectual property groups and their legal counsel trust Chipworks for success in patent licensing and litigation earning hundreds of millions of dollars in patent licenses, and saving as much in royalty payments. Research & Development and Product Management rely on Chipworks for success in new product design and launch, saving hundreds of millions of dollars in design, and earning even more through superior product design and faster launches. Contact Chipworks To find out more information on this report, or any other reports in our library, please contact Chipworks at: Chipworks 3685 Richmond Rd. Suite 500 Ottawa, Ontario K2H 5B7 Canada T: F: Web site: info@chipworks.com Please send any feedback to feedback@chipworks.com
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