Texas Instruments S W Digital Micromirror Device

Transcription

1 Texas Instruments S W MEMS Process Review with Supplementary TEM Analysis For comments, questions, or more information about this report, or for any additional technical needs concerning semiconductor technology, please call Sales at Chipworks Richmond Road, Suite 500, Ottawa, ON K2H 5B7, Canada Tel: Fax:

2 MEMS Process Review Table of Contents 1 Overview 1.1 List of Figures 1.2 List of Tables 1.3 Company Profile 1.4 Introduction 1.5 Device Summary 1.6 Process Summary 2 Device Overview 2.1 Package and Die 3 Package Analysis 3.1 Package Overview 3.2 Printed Wiring Board 4 Process 4.1 General Device Structure 4.2 Dielectrics 4.3 Metallization 4.4 Vias and Contacts 4.5 Transistors and Poly 4.6 Isolation 4.7 Wells and Epi 5 Architectural Analysis 5.1 Micromirror Array (Plan View) 5.2 Cross-Sectional Analysis (Parallel to Metal 1 Select Line) 5.3 Cross-Sectional Analysis (Parallel to Metal 2 Data Line) 6 Critical Dimensions 6.1 Package and Die Dimensions 6.2 Horizontal Dimensions 6.3 Vertical Dimensions 7 References 8 Statement of Measurement Uncertainty and Scope Variation Report Evaluation

3 Overview Overview 1.1 List of Figures 2 Device Overview Top Package View Bottom Package View Tilt View Package S Package Tilt View Plan View Package X-Ray Die Die Annotated with Cross Sections Die Markings Die Corner Die Corner Die Corner Bond Pads Mirror Array Corner 3 Package Analysis Decapsulated Package Package Cross Section SEM-EDS Spectrum Heat Spreader Edge of Die and Heat Spreader Left Sidewall Spacer Window and Sidewall Spacer Glass Seal Window Attached Window Support Frame on Die Left Edge of Frame DMD Die Edge Printed Wiring Board Edge of Stitch Bond Printed Wiring Board X-Ray Through Hole Via PWB M Pin Grid Array

4 Overview Process General View of S Passivation IMD IMD PMD TEM Metal TEM Metal 5 ARC TEM Edge Metal 5 Mirror Minimum Pitch Metal TEM Metal Metal TEM Metal Metal TEM Metal 2 Barrier and Adhesion Layers Minimum Pitch Metal Via Via 3s TEM Via Minimum Pitch Via 2s Minimum Pitch Via 1s Minimum Pitch Contacts to Diffusion TEM Contact to Poly Peripheral NMOS Transistor Peripheral PMOS Transistor TEM Gate Edge TEM Peripheral Transistor Gate Oxide Minimum Width Field Oxide Poly Over Oxide SRP P-Epi and Substrate SRP Peripheral P-Well SRP Peripheral N-Well Array N-Well

5 Overview Architectural Analysis T Mirror Cell S Metal 5 Mirrors S Metal 5 Mirrors Mirror Tilt View of Torsion Hinges and Electrodes Torsion Hinge Base of Mirror Support Post Metal 3 Mirror Bias Bus and Address Electrodes Bias Bus and Address Electrode Metal 2 VSS, V DD and Data Lines Metal 1 Select Line and V DD Bus Array at Poly SRAM Cell at Poly Poly and Diffusion Mirror Pixel Annotated with Cross Sections Pixel Array Through SRAM NMOS Transistors NMOS Transistors T1 and T NMOS Transistor T Mirrors and PMOS Transistors PMOS Transistor T TEM Gate Oxide T1 and T2 Inverter Pair

6 Overview List of Tables 1 Overview Device Identification Device Summary Process Summary 2 Device Overview DMD Package Dimensions 4 Process Dielectric Thicknesses Metallization Vertical Dimensions Metallization Horizontal Dimensions Via and Contact Dimensions Peripheral Transistor Horizontal Dimensions Peripheral Transistor and Polycide Vertical Dimensions 5 Architectural Analysis SRAM Transistor Sizes 6 Critical Dimensions DMD Package Dimensions Metallization Horizontal Dimensions Via and Contact Dimensions Peripheral Transistor Horizontal Dimensions SRAM Transistor Sizes Dielectric Thicknesses Metallization Vertical Dimensions Peripheral Transistor and Polycide Vertical Dimensions

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