Midterms Exam Fall 2011 Solu6ons
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1 Midterms Exam Fall 2011 olu6ons
2 olu6on to Task 1
3 m 0 1 sel0 a0_in a0 0 1 sel 2.5 points Datapath main iterate loop 0 1 sel 10 points 0 1 sel 0 1 sel 0 1 sel y=a0_out a0 en en0 en en a1 7.5 points a2 en en a3 en en k en en0 << 1 a a0 7.. addr addr dout dout b0 7.. b >> 3 a a1 7.. addr addr dout dout b1 7.. b a a2 7.. addr addr dout dout b2 7.. b b k <<< 2 b a a3 7.. addr addr dout dout b3 7.. b >> <<< 5 k_= 0 10 points 1 k0 k 7 a1_= a2_= a3_= a0_= 2.5 points
4 Datapath counters & state registers last_block 5 5 en ld Ei Li 3 3 en ld Ej Lj en El i j last_block_stored = 31 = Zi Zj 2.5 points 2.5 points 2.5 points
5 olu6on to Task 2
6 Interface with the dision into the Datapath and the Controller m last_block src_ready zi zj last_block_stored Datapath en en0 sel Ei Li Ej Lj El Controller y src_read done
7 olu6on to Task 3
8 Implemented Circuit main iterate loop a0_in 0 1 sel 0 1 sel 0 1 sel 0 1 sel 0 1 sel a0_out a0 en en0 a1 en en a2 en en a3 en en k en en0 << 1 a a0 7.. addr addr dout dout b0 7.. b >> 3 a a1 7.. addr addr dout dout b1 7.. b a a2 7.. addr addr dout dout b2 7.. b b k <<< 2 b a a3 7.. addr addr dout dout b3 7.. b >> <<< k_= k0 k 7 a1_= a2_= a3_= a0_=
9 library IEEE; use IEEE.TD_LOGIC_116.ALL; enqty reg is generic (WIDTH : INTEGER := ); port ( : in TD_LOGIC; : in TD_LOGIC; ); end reg; en : in TD_LOGIC; din : in TD_LOGIC_VECTOR(WIDTH- 1 downto 0); dout : out TD_LOGIC_VECTOR(WIDTH- 1 downto 0)
10 architecture rtl of reg is begin reg_gen : process(, ) begin if ( = '1' ) then dout <= (OTHER =>'0'); elsif rising_edge( ) then if ( en = '1' ) then dout <= din; end if; end if; end process; end rtl; 3 points
11 library IEEE; use IEEE.TD_LOGIC_116.ALL; use IEEE.NUMERIC_TD.all; enqty ROM_16x is port( addr : in std_logic_vector(3 downto 0); dout : out std_logic_vector(3 downto 0)); end ROM_16x; 5 points architecture rtl of ROM_16x is type mem is array (0 to 15) of std_logic_vector(3 downto 0); constant my_rom : mem := ( x"e", x"d", x"b", x"0", x"2", x"1", x"", x"f, x"7", x"a", x"", x"5", x"9", x"c", x"3", x"6 ); begin dout <= my_rom(to_integer(unsigned(addr))); end rtl;
12 library IEEE; use IEEE.TD_LOGIC_116.ALL; use IEEE.TD_LOGIC_UNIGNED.all; enqty main_iteraqve_loop is port ( : in TD_LOGIC; - - ystem clock : in TD_LOGIC; - - Asynchronous system sel : in TD_LOGIC; - - select signal to choose a0, a1, a2 and a3 en : in TD_LOGIC; - - enable signal for registers for a1, a2, a3, and k en0 : in TD_LOGIC; - - enable signal for registers for a0 a0_in : in TD_LOGIC_VECTOR(7 downto 0); - - a0 input a0_out : out TD_LOGIC_VECTOR(7 downto 0); - - a0 output a0_= : out TD_LOGIC_VECTOR(7 downto 0) - - a0 feedback ); end main_iteraqve_loop;
13 architecture rtl of main_iteraqve_loop is - - types type array_type_1 is array (0 to ) of TD_LOGIC_VECTOR(7 downto 0); type array_type_2 is array (0 to 3) of TD_LOGIC_VECTOR(7 downto 0); type array_type_3 is array (0 to 1) of TD_LOGIC_VECTOR(7 downto 0); - - signals signal a_in, a: array_type_1; signal b, a_= : array_type_2; signal mux_rot, mux_shii : array_type_3; signal ens : TD_LOGIC_VECTOR ( downto 0); signal k_in, k, k_= : TD_LOGIC_VECTOR (7 downto 0); - - IniQalize constants constant : TD_LOGIC_VECTOR (7 downto 0) := x"c0" ; constant k0 : TD_LOGIC_VECTOR (7 downto 0) := x"1b" ;
14 begin Muxes for once- per- message iniqalizaqon: - - a0 = ; a1 = ; a2 = ; a3 = ; k = ; a_in(0) <= when sel ='1' else a0_in; a_in(1) <= when sel ='1' else a_=(1); a_in(2) <= when sel ='1' else a_=(2); a_in(3) <= when sel ='1' else a_=(3); k_in <= when sel ='1' else k_=; Registers for ( a0, a1, a2, a3, k) a_in() <= k_in; ens <= (0=> en0, OTHER => en); reg_gen : for i in 1 to generate reg_0 : enqty work.reg(rtl) port map ( =>, =>, en => ens(i), din => a_in(i), dout => a(i) ); end generate; k <= a(); 3 points
15 - - instances of - box module ROM_gen : for i in 0 to 3 generate 5 points ROM_0 : enqty work.rom_16x(rtl) port map (addr => a(i)(3 downto 0), dout => b(i)(7 downto ) ); ROM_1 : enqty work.rom_16x(rtl) port map (addr => a(i)(7 downto ), dout => b(i)(3 downto 0) ); end generate; - - a0 = ((b3 <<< 5) + b3) mod 256 a_=(0) <= (b(3)(2 downto 0) & b(3)(7 downto 3) ) + b(3); - - a1 = (b0 >> 3) XOR b0 a_=(1) <= ( "000" & b(0)(7 downto 3) ) XOR b(0); 2 points 2 points
16 - - a2 = (b2 <<< (b1 mod ) ) XOR k mux_rot(0) <= b(2) when b(1)(0)='0' else ( b(2)(6 downto 0) & b(2)(7) ); mux_rot(1) <= mux_rot(0) when b(1)(1)='0' else ( mux_rot(0)(5 downto 0) & mux_rot(0)(7 downto 6) ); a_=(2) <= mux_rot(1) XOR k_out; points - - a3 = (b3 >> (b2 mod ) ) + b3) XOR b3 mux_shii(0) <= b(3) when b(2)(0)='0' else ( '0' & b(3)(7 downto 1) ); mux_shii(1) <= mux_shii(0) when b(2)(1)='0' else ( "00" & mux_shii(0)(7 downto 2) ); a_=(3) <= mux_shii(1) XOR b(3); - - if k(7)==0 then k = k<<1 else k=(k<<1) XOR k0 k_= <= (k(6 downto 0) & '0') when k(7) ='0' else ((k(6 downto 0) & '0') XOR k0); points 2 points end rtl; a0_out <= a(0); a0_= <= a_=(0);
17 olu6on to Task
18 Resource Utilization in Xilinx partan 3 a0_in LC 0 1 sel LC 0 1 sel LC 0 1 sel LC 0 1 sel LC 0 1 sel y=a0_out LC LC LC LC LC en en0 en en en en en en en en0 a0 a1 a2 a3 k a a0 7.. a a1 7.. a a2 7.. a a3 7.. addr addr addr addr addr addr addr addr LC LC LC LC LC LC LC LC LC dout dout dout dout dout dout dout dout b0 7.. b b1 7.. b b2 7.. b b3 7.. b LC LC 2 16 LC 2 b k_= >> 3 0 LC <<< b2 >> <<< LC LC k LC LC LC a1_= a2_= a3_= a0_= 0 LC << 1 k0 k 7
19 Resource Utilization ummary 6 x - bit 2- to- 1 MUX = 6 x MLUTs in logic mode = LC 5 x - bit register = 5 x torage Elements in FF mode = 0 LC x - by- - box = x MLUT in logic mode = 32 LC Variable Rotator = 16 MLUTs in logic mode = 16 LC Variable hiier = 16 MLUTs in logic mode = 16 LC - bit Adder = Carry & Control units = LC 3 x - bit XOR = 2 MLUTs in logic mode = 2 LC inverters = MLUTs in logic mode = LC Total = 1 LC
20 olu6on to Task 5
21 LIBRARY ieee; UE ieee.std_logic_116.all; enqty exam_top_tb is end exam_top_tb; architecture behavior of exam_top_tb is - - component declaraqon for the unit under test (uut) component exam_top port( : in std_logic; : in std_logic; m : in std_logic_vector(7 downto 0); src_ready : in std_logic; src_read : out std_logic; last_block : in std_logic; done : out std_logic; y : out std_logic_vector(7 downto 0) ); end component;
22 - - Inputs signal : std_logic := '0 ; signal : std_logic; signal m : std_logic_vector(7 downto 0); signal src_ready : std_logic; signal last_block : std_logic; - - Outputs signal src_read : std_logic; signal done : std_logic; signal y : std_logic_vector(7 downto 0); 1 point - - Clock period definiqons constant _period : Qme := 100 ns;
23 BEGIN - - instanqate the Unit Under Test (UUT) uut: exam_top PORT MAP ( =>, =>, m => m, src_ready => src_ready, src_read => src_read, last_block => last_block, done => done, y => y ); 3 points
24 - - clock generaqon _gen: process begin <= '0 ; wait for _period/2; <= '1 ; wait for _period/2; end process; - - generaqon _gen: process begin <= '1'; wait for _period; <= '0'; wait; end process; 3 points 2 points
25 - - Qmuli process sqm_proc: process begin m <= x"ff ; src_ready <= '1'; last_block <= '0'; for i in 0 to 2 loop wait unql src_read='1'; wait unql src_read='0'; end loop; last_block <= '1'; wait unql src_read='1'; wait unql src_read='0'; 2 points points wait unql done='1 ; wait; end process; end;
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