Chapter 5 - Memory. Sarah L. Harris and David Money Harris. Digital Design and Computer Architecture: ARM Edi>on 2015

Transcription

1 Chapter 5 - Memory Digital Design and Computer Architecture: ARM Edi*on Sarah L. Harris and David Money Harris Chapter 5 <1>

2 Chapter 5 :: Topics Introduc*on Arithme*c Circuits Number Systems Sequen*al Building Blocks Memory Arrays Logic Arrays Chapter 5 <2>

3 Memory Arrays Efficiently store large amounts of data 3 common types: Dynamic random access memory (DRAM) Sta>c random access memory (SRAM) Read only memory (ROM) M-bit data value read/ wriuen at each unique N-bit address Address N Array M Data Chapter 5 <3>

4 Memory Arrays 2-dimensional array of bit cells Each bit cell stores one bit N address bits and M data bits: 2 N rows and M columns Address N Array Depth: number of rows (number of words) Width: number of columns (size of word) Array size: depth width = 2 N M Address Data M Data Address 2 Array depth Data width Chapter 5 <4>

5 Memory Array Example 4 KB memory array Number of words: 1024 Word size: 32-bits (4 bytes) Address word x 32-bit Array 32 Data Chapter 5 <5>

6 Memory Array Example bit array Number of words: 4 Word size: 3-bits For example, the 3-bit word at address 10 is 100 Address Data Address 2 Array depth Data width Chapter 5 <6>

7 Memory Array Bit Cells wordline bit = = wordline = 1 wordline = 0 = = wordline = 1 wordline = 0 (a) (b) Chapter 5 <7>

8 Memory Array Bit Cells wordline bit wordline = 1 = 0 wordline = 0 = Z wordline = 1 = 1 wordline = 0 = Z (a) (b) Chapter 5 <8>

9 Memory Array Wordline: like an enable single row in memory array read/wriuen corresponds to unique address only one wordline HIGH at once 2:4 Decoder wordline 3 Address 2 10 wordline 2 01 wordline 1 00 wordline 0 Data 2 Data 1 Data 0 Chapter 5 <9>

10 Types of Memory Random access memory (RAM): vola*le Read only memory (ROM): nonvola*le Chapter 5 <10>

11 RAM: Random Access Memory Vola*le: loses its data when power off Read and wriuen quickly Main memory in your computer is RAM (DRAM) Historically called random access memory because any data word accessed as easily as any other (in contrast to sequen>al access memories such as a tape recorder) Chapter 5 <11>

12 ROM: Read Only Memory Nonvola*le: retains data when power off Read quickly, but wri>ng is impossible or slow Flash memory in cameras, thumb drives, and digital cameras are all ROMs Historically called read only memory because ROMs were wriuen at manufacturing >me or by burning fuses. Once ROM was configured, it could not be wriuen again. This is no longer the case for Flash memory and other types of ROMs. Chapter 5 <12>

13 Types of RAM DRAM (Dynamic random access memory) SRAM (Sta>c random access memory) Differ in how they store data: DRAM uses a capacitor SRAM uses cross-coupled inverters Chapter 5 <13>

14 Robert Dennard, Invented DRAM in 1966 at IBM Others were skep>cal that the idea would work By the mid-1970 s DRAM in virtually all computers Chapter 5 <14>

15 DRAM Data bits on capacitor Dynamic because the value needs to be refreshed (rewriuen) periodically and aier read: Charge leakage from the capacitor degrades the value Reading destroys the value wordline bit wordline bit Chapter 5 <15>

16 DRAM wordline wordline + + Chapter 5 <16>

17 SRAM wordline bit wordline Chapter 5 <17>

18 Memory Arrays Review 2:4 Decoder wordline 3 Address wordline 2 wordline 1 wordline 0 wordline DRAM bit cell: Data 2 Data 1 Data 0 SRAM bit cell: wordline Chapter 5 <18>

19 Mul>-ported Memories Port: address/data pair 3-ported memory 2 read ports (A1/RD1, A2/RD2) 1 write port (A3/WD3, WE3 enables wri>ng) Register file: small mul>-ported memory CLK N N A1 A2 WE3 RD1 RD2 M M N M A3 WD3 Array Chapter 5 <19>

20 ROM Storage Address 2 2:4 Decoder Address Data depth Data 2 Data 1 Data 0 width Chapter 5 <20>

21 ROM: Dot Nota>on 2:4 Decoder 11 wordline Address 2 10 bit cell containing Data 2 Data 1 Data 0 wordline bit cell containing 1 Chapter 5 <21>

22 Logic with Memory Arrays Implement the following logic func>ons using a bit memory array: X = AB Y = A + B Z = A B Chapter 5 <26>

23 Logic with Memory Arrays Implement the following logic func>ons using a bit memory array: X = AB Y = A + B Z = A B A, B 2 2:4 Decoder wordline 3 wordline 2 wordline 1 wordline X Y Z Chapter 5 <27>

24 Logic with Memory Arrays Called lookup tables (LUTs): look up output at each input combina>on (address) 4-word x 1-bit Array Truth Table A B Y A B 2:4 Decoder 00 A 1 01 A Y Chapter 5 <28>

25 Logic Arrays PLAs (Programmable logic arrays) AND array followed by OR array Combina>onal logic only Fixed internal connec>ons FPGAs (Field programmable gate arrays) Array of Logic Elements (LEs) Combina>onal and sequen>al logic Programmable internal connec>ons Chapter 5 <29>

26 Fujio Masuoka, Developed memories and high speed circuits at Toshiba, Invented Flash memory as an unauthorized project pursued during nights and weekends in the late 1970 s The process of erasing the memory reminded him of the flash of a camera Toshiba slow to commercialize the idea; Intel was first to market in 1988 Flash has grown into a $25 billion per year market Chapter 5 <30>