Diagnostic Test Vectors for Combinational and Sequential

Transcription

1 Compaction of Pass/Fail-based Diagnostic Test Vectors for Combinational and Sequential Circuits Yoshinobu Higami, Hiroshi Takahashi, Shin-ya Kobayashi and Yuzo Takamatsu(Ehime University) Kewal K. Saluja (Univ. of Wisconsin-Madison)

2 Outline Background Purpose Compaction for combinational circuits Proposed method Experimental results Compaction for sequential Circuits Proposed method Experimental results Conclusions

3 Background Increase of test cost Expensive tester equipments Long test application time Test compaction Reduce test vectors Reduce test application time Reduce the memory space of test data Fault diagnosis Locate physical defects Improve design and manufacturing process

4 Test compaction for fault diagnosis Benefits Execution time of fault diagnosis is reduced The memory space of test data stored on a tester is reduced The size of fault dictionary is reduced compaction

5 Fault diagnosis of circuits failed in BIST Fault detection in BIST A large number of test vectors are applied. Output responses are highly compacted. Neither time information nor space information is obtained. Requirements for fault diagnosis Information of failing vectors and passing vectors Extract a small number of test vectors for fault diagnosis

6 Purpose Reduce the number of test vectors from a given test set or a test sequence Constraints Keep the number of distinguished fault pairs Only use pass/fail information No information of location of faulty primary outputs and faulty scan flip-flops Targets Stuck-at faults Combinational circuits and non-scanned sequential circuits

7 Compaction for combinational circuits Problem formulation Given: a test set Output: small number of test vectors Constraint: Keep the number of distinguished fault pairs Ideal solution If a fault distinguishing table is available, then the problem can be solved as a minimum set cover problem Difficulties The number of fault pairs is huge. Difficult to use a complete fault distinguishing table Fault distinguishing table v1 v2 v3 v4 pair1 D pair2 D D pair3 D D pair4 D D D: distinguished

8 Proposed algorithm First selection Test vectors that detect oncedetected faults f1 v1 d select v2 v3 v4 v5 Once-detected fault is a fault that is detected by only one test vector f2 f3 f4 f5 d d d d d: detected d d

9 Proposed algorithm select n pairs Use of a partial fault distinguishing table A partial distinguishing table includes information about only a subset of fault pairs Repeat Make a distinguishing table for n fault pairs Select test vectors that distinguish the selected n fault pairs If the original diagnostic resolution is not achieved, then the process is repeated. pair1 pair2 pair3 pair_n v1 D D v2 D D v3 D D v4 D select {v1, v2, v3} select another set of n fault pairs among undistinguished fault pairs

10 Experimental results circuit coverage pair vectors CPU(s) c E c E c E c E c E c E c E c E cs E cs E cs E cs E random vectors were used as a given test set.

11 Test compaction for sequential circuits More difficult than that for combinational circuits When test vectors are removed State transition is changed Faults that are originally detected become undetected. Fault simulation is needed to check if all the faults are still detected. v1 v2 v3 v4 v5 v1 v2 v4 v5 Fault f is detected Fault f may be undetected

12 Reverse order restoration [Guo et al., 1998] First remove all the test vectors except for initialization vectors Restore test vectors in order to detect a subset of faults vector v1 faults Perform fault simulation to see if all the faults are detected v2 v3 f1 Ex: T= v1 v2 (only initialization vectors) v4 T = v1 v2 v9 (v9 detects f3) v5 If T detects f3, then add v6. v6 f2 Otherwise, add v8. v7 T= v1 v2 v8 - v9 v8 If T detects f3, then add v6 v9 f3 T= v1 v2 - v8 - v9 v6

13 Proposed algorithm(dcomp- S) Apply reverse order restoration for diagnostic sequences Remove all the test vectors except for initialization vectors Restore test vectors Perform fault simulation to see if all the distinguished fault pairs are distinguished. vector v1 v2 v3 v4 v5 pair pair1 Ex: T= v1 v2 (Only initialization vectors) T = v1 v2 v9 (Add v9 for distinguishing pair3) Unless T distinguishes pair3, then add v8 T1= v1 v2 v8 - v9 Check if T distinguishes pair3 T1= v1 v2 - v8 - v9 v6 v6 v7 v8 v9 pair2 pair3

14 Experimental results circuit length compacted % pair CPU(s) s , s382 2, , s , s400 2, , s526 2, , s , s , s820 1, , s , s , s , s1488 1, ,041, s1494 1, ,054, Test sequences generated by HITEC were used as original test sequences.

15 DCOMP-S Results About 10~72 % test vectors were removed. Shortcomings It needs information about when each fault pair is distinguished It is difficult to store such information for a large number of fault pairs.

16 Proposed algorithm(dcomp-ls) Most of the steps in DCOMP-LS is same as those in DCOMP-S Differences First restore test vectors v1 to vs as an initial compacted test sequence (Tc) Collect fault pairs distinguished by T0 but not by Tc distinguished by T0 v1 v2 v3 v4 v5 v6 v7 v8 v9 target fault pairs Tc undistinguished by v1 v2 v3 v4 v5 Restore S test vectors apply ROR

17 Results by DCOMP-LS compacted test length CPU(s) circuit DCOMP-S % DCOMP-LS % DCOMP-S DCOMP-LS s s s s s s s s s s s s

18 Results by DCOMP-LS Test sequences generated by HITEC, S=90% circuit length compacted % pairs CPU(s) s E s E HITEC+ 50 random vectors,1024 random vectors, S=90% circuit length compacted % pair CPU(s) s E s E

19 Conclusion Proposed diagnostic test compaction methods Methods for combinational circuits and sequential circuits Heuristics for reducing target fault pairs to be considered at a time Future work Improve the method for large sequential circuits

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21 Experimental results Comparison of results with different n. n =100,000 n =1,000 circuit vectors CPU(s) vectors CPU(s) c c cs cs cs cs random vectors were used as a given test set.