The TAU 2017 Contest

Transcription

1 The TAU 2017 Contest Timing Macro Modeling Song Chen Synopsys [Speaker] Akash Khandelwal Cadence Xin Zhao IBM Corp. Xi Chen Synopsys Sponsors: TAU 2017 Workshop March 16 th -17 th,

2 Why Timing Macro Modeling Again? 1. Very Important 2

3 Motivation Integrated circuit chip grow rapidly in performance and gate / transistor counts Process Node 16nm Transistors 15.3 Billion > 2x world population GPU Die Size 610 mm2 FP64 Compute 5.30 TFLOPs > fastest supercomputer in 1999 Source: NVIDIA GP100 Source: 3

4 Motivation Design / analysis / verification are done hierarchically with multiple level of hierarchies and in parallel. Need abstraction for low level blocks when work at higher level. SMs 56 CUDA Cores Per SM 64 CUDA Cores (Total) 3584 FP64 CUDA Cores / SM 32 FP64 CUDA Cores / GPU 1792 Texture Units 224 Memory Size 16 GB NVIDIA GP100 Source: 4

5 Hierarchical Timing Analysis Full netlist Includes top and block netlist Interface timing model Top level netlist and netlist of block interface Extracted timing model (ETM) Top level netlist and ETM for blocks Apple A10 Source: 5

6 Extracted timing model (ETM) Benefits Simple, understandable model Fast runtime, small memory footprint Do not expose IP Widely supported by many tools. Shortcoming Accuracy in advanced node Do not allow cross hierarchy timing constraint Cannot optimize block from top 6

7 Why Timing Macro Modeling Again? 2. Performance 2016 contest: focus on accuracy 2017 contest: focus on performance on usage 7

8 2016 Contest 8

9 Model Generation Methods Graph Reduction Start from full graph, eliminate / merge nodes and arcs Easy to archive accuracy Point to point extraction Directly extract the point to point delay Can add internal node Minimize model size 9

10 Model Size/Performance vs. Accuracy Original Design u1 a o b u2 a o n1 n2 u3 a o b Timing Model p1 p2 p3 p4 p5 p6 p7 p8 p1 p2 p3 p4 Slower Usage Large High Model Size** Accuracy** **general trends Faster Usage Small Low 10

11 Accuracy Evaluation u1 a o b u2 a o n1 n2 u3 a o b Original Benchmark Contestant Binary Early + Late.libs design_model u1 a o b u2 a o n1 n2 u3 a o b Vary Input and Output Conditions: input slew, put load, arrival time design_model Analysis using OpenTimer Accuracy Evaluation Golden Timing Report Contestant Timing Report 11

12 TAU 2017 Contest Infrastructure Detailed Documentation Provided to Contestants Design Connectivity Benchmarks Early and Late Libraries Design Parasitics Evaluation Block-based Post-CPPR Timing Analysis at Primary Inputs and Primary Outputs Timing and CPPR tutorials, file formats, timing model basics, evaluation rules, etc. Open Source Code and Binaries 1. PATMOS 2011: NTU-Timer 2. TAU 2013: IITiMer 3. TAU 2014: UI-Timer 4. ISPD 2013:.spef/.lib parsers Previous contest winners, utilities Verilog (.v) Liberty (.lib) wrapper file (.tau2016) 5. TAU 2015 binary: itimerc v OpenTimer (UI-Timer v2.0) SPEF (.spef) Assertions (.timing) Based on TAU 2015 Benchmarks Golden Result* Accuracy (.put) Runtime Performance Memory Usage Time frame: ~4 months Contest Scope: only hold, setup, RAT tests; no latches (flush segments); single-source clock tree *using OpenTimer 12

13 Benchmarks: 11 based on TAU 2015 Phase 1 benchmarks (3K 100K gates) 7 based on TAU 2015 Phase 2 benchmarks (1K 150K gates) 7 based on TAU 2015 Evaluation benchmarks (160K 1.6M gates) 13

14 Evaluation Metrics Query Slack at PIs and POs in in-context design : S IC Accuracy (Compared to Golden Results) Query Slack at PIs and POs in original design : S OoC 2017 Accuracy Score [0, 100] ps x (100, ) ps 0 Compute Difference d S for all PIs and POs D S : if optimistic, d S = 2d S average AVG(D S ) standard deviation STDEV(D S ) maximum MAX(D S ) Average performance Worst performance 2016 Accuracy Score [0, 5] ps 100 (5, 10] ps 80 (10, 15] ps 50 (15, ) ps 0 Runtime Factor (Relative) RF(D) = MAX_R(D) R(D) MAX_R(D) MIN_R(D) R(D) Runtime / Memory use 5:1 for model extraction vs. evaluation MF(D) = Memory Factor (Relative) MAX_M(D) M(D) MAX_M(D) MIN_M(D) M(D) Composite Design Score score(d) = A(D) ( RF(D) + 30 MF(D)) 14

15 2017 Contest Results Model Extraction Team1 Team2 Memory Runtime Model Evaluation Team1 Team2 Memory Runtime *Ratio to OpenTimer runtime / memory, large designs Model QoR Team1 Team2 Score Model Size Team1 Team2 Pin Arc

16 TAU 2017 Contestants University Team Texas A&M University AggieTimer National Chiao Tung University itimerm 2.0 University of Illinois at Urbana-Champaign International Institute of Information Technology Federal University of Santa Catarina LibAbs Alpha Ophidian 16

17 Acknowledgments Akash Khandelwal Contest Committee Member Xin Zhao Contest Committee Member Xi Chen Contest Committee Member Qiuyang Wu Workshop General Chair Tom Spyrou Workshop Technical Chair Tsung-Wei Huang OpenTimer Support The TAU 2017 Contestants This contest would not have been successful with your hard work and dedication 17

18 TAU 2017 Timing Contest on Macro Modeling 1st Prize Presented to Pei-Yu Lee and Iris Hui-Ru Jiang For itimerm 2.0 National Chiao Tung University Qiuyang Wu General Chair Tom Spyrou Technical Chair Song Chen Contest Chair 18

19 TAU 2017 Timing Contest on Macro Modeling 2 nd Prize Presented to Tin-Yin Lai, and Martin D. F. Wong For LibAbs University of Illinois at Urbana-Champaign Qiuyang Wu General Chair Tom Spyrou Technical Chair Song Chen Contest Chair 19