VHDL's OSVVM, The Death of SystemVerilog?
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1 VHDL's OSVVM, The Death of SystemVerilog? by Jim Lewis VHDL Training VHDL's OSVVM, the Death of SystemVerilog? Copyright 20 by Design Inc. Reproduction of this entire document in whole for individual usage is permitted. All other rights reserved. In particular,without express written permission of Design Inc, You may not alter, transform, or build upon this work, You may not use any material from this guide in a group presentation, tutorial, training, or classroom You must include this page in any printed copy of this document. This material is derived from ' class, VHDL Testbenches and Verification This material is updated from time to time and the latest copy of this is available at Contact Information Jim Lewis, President Design Inc 898 SW 28th Avenue Tigard, Oregon jim@.com Copyright 20 Design Inc. 2
2 VHDL's OSVVM, the Death of SystemVerilog? OSVVM is a step ahead of SystemVerilog and UVM Topics What is OSVVM,? Constrained Random (CR) Methodology is 2X More Work Writing Functional Coverage is Easy Constrained Random is X or More Slower Intelligent Coverage OSVVM is More Capable Randomization in OSVVM OSVVM Loves Any Testbench Transactions are more than Structure Objections to VHDL OSVVM Summary Copyright 20 Design Inc. What is OS-VVM? Open Source VHDL Verification Methodology Packages + Methodology for: Functional Coverage (FC) Constrained Random (CR) Intelligent Coverage - Test generation using FC holes Leading edge verification for your VHDL team Mixes well with other approaches (directed, algorithmic, file, random) Works in any VHDL testbench Readable by All (in particlar RTL engineers) Low cost solution to leading edge verification Works with regular VHDL simulators Packages are FREE Copyright 20 Design Inc.
3 What is Functional Coverage? Code that observes execution of your test plan Tracks requirements, features, and boundary conditions Model interface and design requirements Required for randomized tests. Point Coverage (aka Item Coverage) Track relationships within a single object Bins of values, such as transfer sizes:, 2,, -27, 28-22, 2, 2, 2 Cross Coverage Track relationships between multiple objects Has the each pair of registers been used with the ALU? Test Done = 00 % Functional Coverage + 00 % Code Coverage Copyright 20 Design Inc. What is Constrained Random? Constrained Random (CR) Models input values, transactions, and/or sequences using constraints Constraints can be equations (SV) or code (VHDL) SystemVerilog uses a solver to balance the randomization Copyright 20 Design Inc.
4 CR is 2X More Work than OSVVM Constrained Random (CR) Methodology Write a randomization constraint model Write a functional coverage model Generate stimulus by randomizing using randomization constraints OSVVM Intelligent Coverage Methodology Write a functional coverage model Generate stimulus by randomizing across holes in the FC model Result: CR: OSVVM: 2 models: Randomization Constraints + FC Only need a FC Model. Less Work (2X?) Copyright 20 Design Inc. 7 Writing Functional Coverage Testing an ALU with Multiple Inputs: D0 Q SRC... D7 Q7 Mux 8: SRC2... Mux 8: Need to test every register in SRC with every register in SRC2 S R C R R R R R Copyright 20 Design Inc. R SRC2 R R R R 8
5 Writing Functional Coverage architecture Test of tb is shared variable ACov : CovPType ; begin CollectCov : process variable RV : RandomPType ; -- randomization object variable Src, Src2 : integer ; begin ACov.AddCross( GenBin(0,7), GenBin(0,7) ); while not ACov.IsCovered loop Coverage Object Create Cross Coverage Bins Covered = Done Src := RV.RandInt(0, 7) ; Src2 := RV.RandInt(0, 7) ; ACov.ICover( ( Src, Src2 ) ) ; Uniform Randomization Collect Coverage DoAluOp(TRec, Src, Src2) ; end loop ; ACov.WriteBin ; EndStatus(... ) ; end process ; Copyright 20 Design Inc. Do Transaction Functional Coverage with OSVVM is as concise as language syntax. 9 Constrained Random is X or More Slower Constrained random (CR) is at best a uniform randomization Uniform distributions repeat before generating all cases In general, to generate N cases, it takes O(N*log N) randomizations The uniform randomization in ALU test requires test iterations. is approximately X too many iterations ( test cases) The "log N" factor significantly slows down constrained random tests. S R C R R R R R 7 R 9 SRC2 R R R 0 R "From Volume to Velocity" shows CR tests that are 0X to 00X too slow Copyright 20 Design Inc. 0
6 Intelligent Coverage Randomly select holes in Functional Coverage Model "Coverage driven randomization" - but term is misused by others Goal: Generate N Unique Test Cases in N Randomizations Same goal of Intelligent Testbenches SRC2 S R C R R R R R R R R R R Copyright 20 Design Inc. Intelligent Coverage Same test using Intelligent Coverage architecture Test of tb is shared variable ACov : CovPType ; begin CollectCov : process variable Src, Src2 : integer ; begin ACov.AddCross(GenBin(0,7), GenBin(0,7) ); while not ACov.IsCovered loop (Src, Src2) := ACov.RandCovPoint ; ACov.ICover( ( Src, Src2 ) ) ; DoAluOp(TRec, Src, Src2) ; end loop ; ACov.WriteBin ; -- Report Coverage EndStatus(... ) ; end process ; Intelligent Coverage Randomization Runs X faster Copyright 20 Design Inc. 2
7 Refinement of Intelligent Coverage Refinement can be as simple or complex as needed Use either directed, algorithmic, file-based or randomization methods. while not ACov.IsCovered loop (Reg, Reg2) := ACov.RandCovPoint ; if Reg /= Reg2 then DoAluOp(TRec, Reg, Reg2) ; ACov.ICover( (Reg, Reg2) ) ; else -- Do previous and following diagional DoAluOp(TRec, (Reg-) mod 8, (Reg2-) mod 8) ; DoAluOp(TRec, Reg, Reg2 ) ; DoAluOp(TRec, (Reg+) mod 8, (Reg2+) mod 8) ; -- Can either record all or select items ACov.ICover( (Reg, Reg2) ) ; end if ; end loop ; Copyright 20 Design Inc. OSVVM is More Capable Functional Coverage is a data structure Incremental additions supported Captured sequentially - use any code (if, loops, ) Each bin can have a different coverage goal Goal = Number of times of value must occur to be covered Coverage goals are also used as randomization weights Different coverage goal for each Src crossed with any Src2 -- Goal Src Src2 ACov.AddCross(, GenBin(0), GenBin(0,7) ) ; ACov.AddCross( 2, GenBin(), GenBin(0,7) ) ; ACov.AddCross(, GenBin(2), GenBin(0,7) ) ; ACov.AddCross(, GenBin(), GenBin(0,7) ) ; ACov.AddCross(, GenBin(), GenBin(0,7) ) ; ACov.AddCross(, GenBin(), GenBin(0,7) ) ; ACov.AddCross( 7, GenBin(), GenBin(0,7) ) ; ACov.AddCross( 8, GenBin(7), GenBin(0,7) ) ; Copyright 20 Design Inc.
8 Randomization in OSVVM Implemented in RandomPkg Randomize a value in an inclusive range, 0 to, except & Data := RV.RandInt(Min => 0, Max => ) ; Data2 := RV.RandInt(0,, (,) ); -- except & Randomize a value within the set (, 2,,, 7, ), except & Data := RV.RandInt( (,2,,,7,) ); Data := RV.RandInt( (,2,,,7,), (,) ); Weighted Randomization: Value + Weight ((val, wt), (val2, wt2),...) Data := RV.DistValInt( ((,7), (,2), (, )) ); Weighted Randomization: Weight, Value = 0.. N- Data := RV.DistInt ( (7, 2, ) ) ; Copyright 20 Design Inc. OSVVM Supports Randomization OSVVM uses code patterns to create constraints Example: Weighted selection of paths (test sequences) StimGen : while TestActive loop -- Repeat until done case RV.DistInt( (7, 2, ) ) is when 0 => -- Normal Handling -- 70%... when => -- Error Case -- 20%... when 2 => -- Error Case %... See the RandomPkg Users Guide for more examples and seed setting Code patterns can create a constrained random test environment, however, OSVVM uses Intelligent Coverage as the primary randomization Code patterns are used primarily as refinement. Copyright 20 Design Inc.
9 OSVVM Loves Any Testbench We prefer transaction based testbenches TbMemIO TestCtrl CPU Model Clock and Reset DUT : MemIO CpuIf UART IntCtrl Timer MemIf UartRx Model UartTx Model SRAM Model Similar structure to other verification languages Uses regular entities & architectures. Records on interfaces. No OO required. Copyright 20 Design Inc. 7 Transactions are more than Structure Structure: Encapsulate Interface Functionality in a Model -- CPU Write nads <= '0' after tpd, '' after tperiod + tpd ; Addr <= ADD after tpd ; Data <= X"AA" after tperiod + tpd ; Wr_nRd <= '0' after tpd ; wait until nrdy = '0' and rising_edge(clk) ; Abstract Initiation: Use a procedure to initiate a transaction... CpuWrite(CpuRec, ADD, X"AA"); CpuRead (CpuRec, ADD, DataO);... Result: Test is more readable Testbench is not the exclusive domain of verification engineers Simplifies writing tests. Copyright 20 Design Inc. 8
10 Objections to VHDL No Solver Intelligent coverage more effective than the best solver No Fork & Join Fork & Join are for sequential programming - writing threads. Concurrent programming uses handshaking (like hardware) No OO More effective at bundling of a models intent Functional Coverage and Randomization needs data structures not OO No Factory Class Factory classes allow swapping of implementations in OO Architectures give the same capability for concurrent programming Copyright 20 Design Inc. 9 OSVVM Summary Intelligent Coverage = Simple, Powerful Methodology Define Functional Coverage Randomize across coverage holes Refine with directed, algorithmic, file-based or CR methods Faster Test construction: Focus on FC (2X faster) Simulations: No redundant stimulus (X faster) and No solver OSVVM Goes beyond other verification languages (SV and 'e') Readable by All (Verification and RTL engineers) Works in any VHDL environment in part or whole Is Free Open Source Downloads: SystemVerilog? Why bother! Copyright 20 Design Inc. 20
11 VHDL Training Comprehensive VHDL Introduction Days A design and verification engineer's introduction to VHDL syntax, RTL coding, and testbenches. Students get VHDL hardware experience with our FPGA based lab board. VHDL Testbenches and Verification days - OS-VVM bootcamp Learn the latest VHDL verification techniques including transactionbased testing, bus functional modeling, self-checking, data structures (linked-lists, scoreboards, memories), directed, algorithmic, constrained random and coverage driven random testing, and functional coverage. VHDL Coding for Synthesis Days Learn VHDL RTL (FPGA and ASIC) coding styles, methodologies, design techniques, problem solving techniques, and advanced language constructs to produce better, faster, and smaller logic. offers on-site, public venue, and on-line classes. See: Going Further / References Jim's Blog: OSVVM Website: Coverage Package Users Guide and Random Package Users Guide "From Volume to Velocity" by Walden Rhines of Mentor Graphics, Keynote speech for DVCon 20. See Copyright 20 Design Inc. 22
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