Bresenham s Line Algorithm in Hardware
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1 Bresenham s Line Algorithm in Hardware Stephen A. Edwards Columbia University Spring 22
2 Bresenham s Line Algorithm Objective:Draw a line...
3 Bresenham s Line Algorithm...with well-approximating pixels...
4 Bresenham s Line Algorithm...by maintaining error information.. Error = /7 Error = 3/7
5 Bresenham s Line Algorithm...encoded using integers Error = /7 Error = 3/7
6 The Pseudocode from Wikipedia function line(x, y, x, y) dx := abs(x-x) dy := abs(y-y) if x < x then sx := else sx := - if y < y then sy := else sy := - err := dx-dy loop setpixel(x,y) if x = x and y = y exit loop e2 := 2*err if e2 > -dy then err := err - dy x := x + sx end if if e2 < dx then err := err + dx y := y + sy end if end loop
7 My C Code void line(uint6 x, Uint6 y, Uint6 x, Uint6 y) { Sint6 dx, dy; // Width and height of bounding box Uint6 x, y; // Current point Sint8 sx, sy; // - or Sint6 err; // Loop-carried value Sint6 e2; // Temporary variable int right, down;// Boolean dx = x - x; right = dx > ; if (!right) dx = -dx; dy = y - y; down = dy > ; if (down) dy = -dy; err = dx + dy; x = x; y = y; for (;;) { plot(x, y); if (x == x && y == y) break; // Reached the end e2 = err << ; // err * 2 if (e2 > dy) { err += dy; if (right) x++; else x--; if (e2 < dx) { err += dx; if (down) y++; else y--;
8 Datapath for dx, dy, right, and down void line(uint6 x, Uint6 y, Uint6 x, Uint6 y) { Sint6 dx; // Width of bounding box Sint6 dy; // Height of BB (neg) Uint6 x, y; // Current point Sint8 sx, sy;// - or Sint6 err; // Loop-carried value Sint6 e2; // Temporary variable int right; // Boolean int down; // Boolean dx = x - x; right = dx > ; if (!right) dx = -dx; dy = y - y; down = dy > ; if (down) dy = -dy; err = dx + dy; x = x; y = y; for (;;) { plot(x, y); if (x == x && y == y) break; e2 = err << ; if (e2 > dy) { err += dy; if (right) x++; else x--; if (e2 < dx) { err += dx; if (down) y++; else y--;
9 Datapath for dx, dy, right, and down x x x x subtract >? negate right dx dx = x - x; right = dx > ; if (!right) dx = -dx; dy = y - y; down = dy > ; if (down) dy = -dy; err = dx + dy; x = x; y = y; y y y y subtract >? negate down dy for (;;) { plot(x, y); if (x == x && y == y) break; e2 = err << ; if (e2 > dy) { err += dy; if (right) x++; else x--; if (e2 < dx) { err += dx; if (down) y++; else y--;
10 Datapath for dx, dy, right, and down x x y y x x subtract >? negate y y subtract >? right dx down xx <= x - x; yy <= y - y; right <= not xx(); down <= not yy(); dx <= xx when right = else -xx; dy <= -yy when down = else yy; negate dy
11 Datapath for err dx dy dy add add dy << < e2 dx dx add e2_gt_dy > in_loop dx = x - x; right = dx > ; if (!right) dx = -dx; dy = y - y; e2_lt_dx err down = dy > ; if (down) dy = -dy; err = dx + dy; x = x; y = y; for (;;) { plot(x, y); if (x == x && y == y) break; e2 = err << ; if (e2 > dy) { err += dy; if (right) x++; else x--; if (e2 < dx) { err += dx; if (down) y++; else y--;
12 Datapath for err dx dy add in_loop err_next <= ("" & dx) + ("" & dy) when in_loop = else err2; dy add dx add err2 <= err + dx when e2_lt_dx = else err; << dy < e2_gt_dy dx > e2 e2_lt_dx err err <= err + dy when e2_gt_dy = else err; e2 <= err( downto ) & ""; e2_gt_dy <= when e2 > dy else ; e2_lt_dx <= when e2 < dx else ;
13 Datapath for x and y + right e2_gt_dy x in_loop x dx = x - x; right = dx > ; if (!right) dx = -dx; dy = y - y; down = dy > ; if (down) dy = -dy; err = dx + dy; x = x; y = y; x y = = + down e2_lt_dx y break in_loop y for (;;) { plot(x, y); if (x == x && y == y) break; e2 = err << ; if (e2 > dy) { err += dy; if (right) x++; else x--; if (e2 < dx) { err += dx; if (down) y++; else y--;
14 Datapath for x and y x y + = = right down e2_gt_dy e2_lt_dx x in_loop break in_loop x x_next <= x when in_loop = else xb; xb <= xa when e2_gt_dy = else x; xa <= x + when right = else x - ; y_next <= y when in_loop = else yb; yb <= ya when e2_lt_dx = else y; ya <= y + when down = else y - ; break <= when x = x and y = y else ; + y y process (clk) begin if rising_edge(clk) then err <= err_next; x <= x_next; y <= y_next; end if; end process;
15 Interface and Types library ieee; use ieee.std_logic_64.all; use ieee.numeric_std.all; entity lines is port ( clk : in std_logic; rst : in std_logic; x, y, x, y : in signed( downto ); x_p, y_p : out signed( downto ); start : in std_logic; done, plot : out std_logic); end lines; architecture datapath of lines is signal xx, yy, dx, dy : signed( downto ); signal down, right, e2_lt_dx, e2_gt_dy : std_logic; signal in_loop, break : std_logic; signal err, err, err2, e2, err_next : signed( downto ); signal x, y, x_next, y_next, xa, xb, ya, yb : signed( downto );
16 Timing clk (x,y) (,) (5,3) (x,y) (7,4) (6,4) start done in_loop break x y err dx, dy 7, 4,
17 Control FSM start break IDLE start start RUN in_loop = start DONE done = break
18 Control FSM in VHDL type states is (IDLE_STATE, RUNNING_STATE, DONE_STATE); signal state : states; fsm : process (clk) begin if rising_edge(clk) then if rst = then state <= IDLE_STATE; else case state is when IDLE_STATE => if start = then state <= RUNNING_STATE; end if; when RUNNING_STATE => if break = then state <= DONE_STATE; end if; when DONE_STATE => if start = then state <= RUNNING_STATE; else state <= IDLE_STATE; end if; end case; end if; end if; end process; in_loop <= when state = RUNNING_STATE else ; done <= when state = DONE_STATE else ; plot <= in_loop;
19 The Framebuffer component fbmem port ( data : in std_logic_vector( downto ); rdaddress : in std_logic_vector(8 downto ); rdclock : in std_logic; wraddress : in std_logic_vector(8 downto ); wrclock : in std_logic; wren : in std_logic; q : out std_logic_vector( downto )); end component; frame_buffer_memory : fbmem port map ( rdaddress => std_logic_vector(rdaddress(8 downto )), rdclock => VGA_CLK, q => q, data => data, wraddress => std_logic_vector(wraddress(8 downto )), wrclock => clk, wren => wren); read_data <= when q() = else ; data <= "" when write_data = else ""; rdaddress <= ("" & VGA_X) + (VGA_Y & "") + (VGA_Y & ""); wraddress <= ("" & VGA_XW) + (VGA_YW & "") + (VGA_YW & "");
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