1997 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS. A Hierarchical Bridging Fault Extraction Approach

Transcription

1 1997 INTERNATIONAL SYMPOSIUM ON VLSI TECHNOLOGY, SYSTEMS, AND APPLICATIONS A Hierarchical Bridging Fault Extraction Approach for VLSI Circuit Layouts Tzuhao Chen and Ibrahim N Hajj Department of Electrical and Computer Engineering and Coordinated Science Laboratory University of Illinois, Urbana, IL, USA Abstract Bridging fault extraction and analysis are crucial to deriving high quality bridging fault test generation As state-of-the-art designs integrate millions of logic gates into a VLSI circuit, a run-time and memory ecient bridging fault extraction approach must be developed to cope with the design complexity In this paper, a hierarchical bridging fault analyzer - FAULTAN is described In FAULTAN, the design hierarchy is followed while performing fault extraction resulting in both computation time and memory savings compared to the traditional at approach As part of the hierarchical extraction strategy, a cell fault library is built a priori to help accelerate the bridging fault extraction process Through the fully hierarchical extraction techniques, FAULTAN achieves on the average 5 times speedup and 1/10 memory usage as compared with an existing at fault extractor The superior accuracy of FAULTAN is also demonstrated in this paper 1 Introduction As state-of-the-art designs integrate millions of logic gates into a single VLSI circuit, testing to ensure the quality of manufactured chips has become more complex, time consuming, and expensive Due to the high integration density of VLSI circuits, bridging faults (a mode of physical faults that form a faulty resistive short between two conducting nets on a chip caused by fabrication defects), have become one of the most frequently occurring physical faults A complete bridging fault set of size? N 2 covers all node pairs in a circuit; where N is the number of nodes in the transistor netlist For large circuits, a complete bridging fault set could be extremely large Test generation targeting such a complete bridging fault set is both costly and unnecessary Fortunately, [1] showed that by analyzing the physical design layout, a small but realistic fault set of size O(N) can be This research was supported by the Semiconductor Research Corporation under Contract SRC 96-DP-109 Cell-Routing Bridge Routing Bridge Cell A Intracell Bridge Cell B Intercell Bridge Routing Channel Cell Row Figure 1: Realistic bridging fault types extracted; this technique is referred to as Inductive Fault Analysis(IFA) In a cell-based circuit layout, realistic bridging faults are grouped into three classes, according to their physical connectivities[2] as shown in Figure 1 A routing-channel bridge (class 1) involves two conducting nets external to cell instances A cell-routing bridge involves one external and one internal nets; an inter-cell bridge involves two internal nets which belong to two separate cell instances The cell-routing and inter-cell bridges are jointly named adjacency bridges (class 2) An intra-cell bridge (class 3) involves two internal nets which belong to the same cell instance In recent years, several fault extractors/analyzers such as FXT[1], FANTESTIC[3], CARAFE[4], HEM- LOCK[5], [6], and LIFT[7, 2] have been developed FXT, a pioneer eort in IFA, determines the eect of spot defects by simulating the defect eects on various layers (eg conducting, insulating, and semiconducting) using the statistical defect information A fault list which contains the transistor-level bridges with their occurrence likelihood values are then generated by FXT based on the previous simulation FAN- TESTIC uses a similar simulation approach to extract the technology decedent topology defects from layouts using defect statistics, it then converts the topology defects to one of four primary faults (hard-short, resistive short, break, and new transistor) These primary faults are then converted to transistor-level faults using the topology$logic information that are made 1

2 available during the extraction stage CARAFE, the most general and well-known fault extractor/analyzer, is able to extract intra- and cross-layer bridging faults in its bridge extraction mode For intra-layer bridging fault extraction, CARAFE takes each region of material and checks for other regions of the same material that are close enough to the original region to form a bridge For cross-layer bridging fault extraction, CARAFE looks for all overlaps in the two desired layers to determine the faults All the above tools are designed for at extraction; that is, a layout has to be attened before the extraction can be done The attened methods are able to extract all three classes (routing, adjacency, and intra-cell) of bridges, however, they may be slow and memory inecient As an accuracy-cost trade o, some routing bridge extractors were developed to extract on only the routing channels to save CPU time and memory In HEM- LOCK, a library which characterizes the ports of each cell in a standard cell library is used to maintain the connectivity of routing bridges among dierent channels [6] is a similar work with a dierent method of calculating the critical area; which determines the occurrence likelihood value for each bridge LIFT, a routing-and-intracell bridge extractor, performs a routing channel extraction to obtain the routing bridges and a table lookup for each cell instance to obtain the intra-cell bridges The table used is obtained by a topological analysis for each cell in the cell library Although faster than the at scheme, LIFT is not capable of extracting adjacency (cell-routing and inter-cell) bridges Table 1: Weighted realistic bridge compositions for ISCAS85 circuit layouts Ckt Composition (%) Routing Adjacency Intra-cell c c c c c c c c c c Table 1 shows the weighted realistic (extracted) bridging fault compositions for routing, adjacency, and intra-cell bridges for ISCAS85 benchmark circuit layouts generated using 10 micrometer CMOS standard-cell technology The results were obtained using FAULTAN and each bridge is weighted by its occurrence likelihood value so the compositions are not biased by the absolute number of bridges It can be seen that the routing-only extraction approach can miss 10% to 25% in total; the routing-and-intracell extraction approach can miss 8% to 19% in total Therefore an accurate, fast and memory ecient extraction scheme is still in need Modern circuit layouts are usually represented in a hierarchical way where an object is dened once and called repeatedly by objects at the next higher level of hierarchy; this way the layout is more compact while all the design information is preserved Realizing this fact, FAULTAN is therefore developed with the ability to fully follow the design hierarchy while performing bridging fault extraction This hierarchical fault extraction scheme allows the accurate extraction of all three bridge classes (routing, adjacency, and intra-cell) at very low CPU time and memory costs as compared with the at approach, such as the scheme used in CARAFE This paper is organized as follows: Section 2 describes the FAULTAN package - its architecture, components, and extraction algorithm Section 3 gives experimental results, comparisons, and discussions Section 4 concludes this paper 2 FAULTAN: A Hierarchical Bridging Fault Extractor/Analyzer FAULTAN, a hierarchical bridging FAULT extractor/analyzer package, is developed to eciently extract/analyze bridges that may arise due to fabrication defects for a given circuit layout FAULTAN package serves as the rst phase in an ecient bridging fault test generation scheme[9] as shown in Figure 2 Fault Extraction from Circuit Layout I DDQ Test Generation I DDQ Test Vectors Extracted Fault Set Voltage-Based Bridging Fault Simulation Using Stuck-at Fault Test Set Reduced Fault Set PHASE 1 PHASE 2 PHASE 3 Figure 2: An ecient bridging fault test generation scheme To demonstrate the feasibility of the hierarchical bridging fault extraction approach, a hierarchical standard-cell design style using publicly available MCNC scmos (scalable CMOS) standard-cell library as shown in Figure 3 has been chosen We must emphasize here, however, that this approach can be ap-

3 fts ai2s o2s Routing Channel i i1s fts oai21s o3s fts Routing Channel i+1 Cell Row i Figure 3: A hierarchical circuit design plied as well to any other hierarchical cell-based designs The advantage of a hierarchical fault extractor/analyzer is multi-fold Firstly, it preserves the hierarchical information of the circuit which is essential for mapping the bridges back to circuit-level faults Secondly, it uses only a small amount of memory as compared to a at fault extraction approach since no attening is needed and only one copy of each cell is stored Thirdly, it is fast since design hierarchy is followed while performing fault extraction; faults on the gate-cell rows are obtained via table lookups in a precomputed cell fault library Therefore a large circuit can be implicitly partitioned into routing channels and gate-cell rows In the following four subsections we describe the FAULTAN architecture, LIBAN program, FAULTAN program, and the Scanline algorithm used in the FAULTAN package, respectively 21 FAULTAN Architecture The architecture of FAULTAN bridging fault extractor/analyzer package is shown in Figure 4 There are two major components in the package: a LIBrary cell fault ANalyzer, LIBAN, and a circuit fault extractor/analyzer FAULTAN Technology Parameters LIBAN Library Cell Layouts Cell Fault Library Cell Netlist Files Process Parameters FAULTAN Hierarchical Circuit Layout Sorted Bridging Fault List Test Info Hierarchical Netlist File Figure 4: FAULTAN architecture The library cell analyzer LIBAN takes each cell layout for a library with C cells, the technology parameters, and the process parameters as inputs Technology parameters used are the denitions of layout planes, layers, connectivities, and transistor compositions Process parameters include the bridge diameter, and a symmetric LL Defect Distribution Matrix (DDM) for all L layers Each entry in the DDM represents the relative possibility of the formation of a bridge between two (not necessarily dierent) layers caused by process defects LIBAN generates a cell fault library (CFL) It contains for each cell in the library 1 a bridging likelihood (BL) value for each intra-cell net pair, 2 all boundary and port rectangles For each library cell pair, the CFL contains a BL value for each inter-cell net pair In addition to the CFL, LIBAN also generates C circuit netlist les for the cells in the library The bridging fault extractor/analyzer FAULTAN takes the cell fault library generated by LIBAN, the technology parameters, and the process parameters as inputs FAULTAN generates an extracted bridging fault list sorted by the BL value for each fault Also generated is a hierarchical circuit netlist le 22 The LIBAN Program LIBAN performs a scan analysis for each library cell layout to build an Intra-cell Bridging Strength Table (IBST) Each IBST contains? N 2 BL values for the intra-cell net pairs, N is the net number in the transistor netlist of this library cell The BL is dened as the relative likeliness of two nets being bridged together due to physical defects during the fabrication process Table 2 gives an example IBST of the library cell i1s with 4 nets (VDD, GND, a, and q) Table 2: The IBST for the library cell i1s VDD GND q a VDD GND q a In addition to the C IBST, LIBAN also performs a scan analysis for each library cell pair to build a Cross-cell Bridging Strength Table (CBST) A CBST is of size N L N R with N L and N R the number of conducting nets in the left-side cell L and the rightside cell R, respectively For a library with C cells, C C CBST need to be constructed since for a cell pair A? B, CBST AB does not equal to CBST BA Table 3 gives an example CBST for the left-side cell i1s with 4 nets and the right-side cell fts with 3 nets There is no VDD-VDD and GND-GND entries in CBST since both VDD and GND are global nets A cell fault library (CFL) of a cell library of C cells contains C IBST, C C CBST and additional useful information including: cell name, cell boundaries, list of net names, and list of boundary and port rectangles, for each cell The boundary rectangles are the rectangles that are within a predened distance to the

4 Table 3: The CBST for left-side cell i1s and right-side cell fts i1s fts VDD GND u1 VDD GND q a cell boundary; they are useful for the extraction of the cell-routing bridges The port rectangles are the rectangles that are used to connect the cell ports to the metal routes in the routing channels The CFL can be built during the library characterization process, it then can be used repeatedly by FAULTAN program to analyze circuit layouts that are built upon this cell library Table 4: The TBST for a 5 cell sample library fts aoi21s aoi22s a3s i4s fts aoi21s aoi22s a3s i4s In addition to the CFL, LIBAN generates a C C Total Bridging Strength Table (TBST) for a cell library Entry T BST(A;B) is the summation of all entries in the corresponding CBST AB, so it represents how likely bridges can occur if cell A were to be placed on the left side of cell B Table 4 gives an example TBST for a 5-cell library With the TBST, a library cell designer can re-design the cells and an automatic cell placer can produce optimal placements to achieve the goal of bridging fault suppression 23 The FAULTAN Program The hierarchical CMOS bridging fault extractor/analyzer FAULTAN takes the cell fault library (CFL) generated by LIBAN and a hierarchical circuit layout as inputs; it then follows the hierarchy of the circuit to determine the BL values between two different nets To be memory ecient, the CFL is only partially loaded into FAULTAN, depending on which library cells are present in this circuit In a hierarchical standard-cell based design as shown in Figure 3, a circuit layout is composed of interleaving routing channels and gate-cell rows A gatecell row is composed of instances of gate-cell primitives from a cell library A routing channel is dedicated to metal routes for connecting the cell instances in the gate-cell rows The most basic layout objects are rectangles at dierent layers, since the layout is used to generate masks for IC processing A common layer set includes wells, diusions, poly, contacts, metals, and vias Because of the varieties of layers (eg wells, diusions, poly, and contacts) involved, the gate-cell rows are the regions with most complex potential bridges Traditional at extractors need to atten the design to rectangles before the extraction can be done They do not recognize the gate-cells or routes, thus consuming large amount of memory and ignoring part of design information In FAULTAN, hierarchical design information is preserved and the hierarchy followed while performing bridging fault extraction FAULTAN rst scans a routing channel to extract potential routing bridges within that channel It then performs an IBST table lookup for each cell instance on the neighboring gate-cell row to nd potential intra-cell bridges and a CBST table lookup for each adjacent cell instance pair to determine the intercell bridges When the above two steps are nished, a boundary scan is performed on the boundary rectangles in the routing channel and its adjacent gate-cell row to determine the potential cell-routing bridges as shown in Figure 5 Routing Channel Cell Row Potential Cell-Routing Bridge Figure 5: Boundary scan for determining cell-routing bridges The electrical connectivity is captured by a similar hierarchical scanning prior to the bridge extraction stage Using this information, the topological bridges can be mapped into circuit-level faults The hierarchical approach used in FAULTAN maintains the design hierarchy information while performing the bridging fault extraction/analysis eciently since the same design object does not get extracted twice and all the inter- and cross-cell bridges can be found through table lookup Unlike CARAFE which can only extract the inter-layer bridges when the two involved rectangles overlap, FAULTAN can extract any inter- and intra-layer bridges with rectangles that are either overlapping or non-overlapping This exibility is due to the use of an ecient Scanline algorithm which is explained in the next section

5 24 The Scanline Algorithm The topological scan method used in FAULTAN package is a Scanline algorithm adapted from [8] for ecient bridging fault extraction as shown in Figure 6 DoScanline() 1 RectLst:Sort(CompareXMin); // sort according to their XMin 2 while not RectLst:Empty() do 3 if (LeftEdge < RectLst:Head:XMin) 4 LeftEdge = RectLst:Head:XMin; // advancing LeftEdge 5 Remove(LeftEdge); 6 Rect = RectLst:P ophead(); 7 Add(Rect); Add(Rect) 1 for every Rect1 in ScnLst 2 if (Rect:Net 6= Rect1:Net) 3 (X; Y ) = CalcXY (Rect; Rect1); 4 5 if (X 0) if (?Y < BrgDmtr) 6 BL = CalcBL(X; Y; Rect:Layer;Rect1:Layer); 7 AddBrg(Rect:Net; Rect1:Net; BL); 8 else if (?X < BrgDmtr) 9 if (Y > 0) 10 BL = CalcBL(X; Y; Rect:Layer;Rect1:Layer); 11 AddBrg(Rect:Net; Rect1:Net; BL); 12 else if (X 2 + Y 2 < BrgDmtr 2 ) 13 BL = CalcBL(X; Y; Rect:Layer;Rect1:Layer); 14 AddBrg(Rect:Net; Rect1:Net; BL); 15 ScnLst:Insert(Rect); Remove(LeftEdge) 1 for every Rect in ScnLst 2 if (Rect:XMax < LeftEdge? BrgDmtr) 3 ScnLst:Remove(Rect); 4 else 5 break; Figure 6: Scanline algorithm used in FAULTAN A primary rectangle list RectLst contains rectangles in a layout object as input and nds the bridging relationships among them A second rectangle list, ScnLst, is maintained for Scanline operations Each rectangle has properties such as Net - the conducting net it belongs to, Layer - the physical layer it is on, and (XMin,YMin,XMax,YMax) - the coordinates of this rectangle Three subroutines DoScanline, Add, and Remove compose the Scanline algorithm; DoScanline calls Add and Remove In subroutine DoScanline, the RectangleList is rst sorted in increasing XM in order, then rectangles in it are popped and processed one by one LeftEdge, the XM in value of the current rectangle processed, is a variable for subroutine Remove to determine which rectangles in ScnLst to remove Subroutine Add processes the interaction between the rectangle under examination and the rectangles already inside ScnLst Subroutine CalcXY calculates the X and Y distances between the two argument rectangles Positive distance value means overlapping; negative one means non-overlapping Subroutine CalcBL calculates the BL between the two rectangles by their sizes and relative position The BL value is equal to DDM AB multiplied by the area in which a defect centered-in with the diameter: BrgDmtr can cause a faulty bridge BL diminishes when X 2 + Y 2 = BrgDmtr 2 DDM AB is a relative defect occurrence likelihood value between layout layers A and B where the two rectangles reside, and is dened in the defect distribution matrix After the BL value is obtained, subroutine AddBridge adds this this value to the corresponding entry in the Global Bridging Strength Table (GBST) of size N N, where N is the number of nets in the transistor netlist of this circuit Since the GBST tends to be sparse, a linked-list with N nodes is used instead of an N N table to save computer memory Subroutine Insert is implemented such that after each rectangle insertion, ScnLst is a sorted list of rectangles with increasing order of XM ax This sorted list makes the removal of rectangles very ecient Subroutine Remove is called whenever LeftEdge is advanced It removes rectangles in ScnLst that are too far away from the rectangle under examination to form a bridge with it Since ScnLst is sorted in increasing order of XM ax, Remove exits whenever the rst rectangle ful- lling (XM ax >= LeftEdge? BrgDmtr) in ScnLst is met After the subroutine DoScanline is nished, all entries in GBST are examined, ranked, and exported to the bridging fault list In addition to the bridging fault list, FAULTAN is also capable of producing information on the BL distribution and statistics, crowded regions of bridges, and extracted hierarchical circuit netlist which is useful for design verication and testing 3 Experimental Results FAULTAN package was implemented in C++ In the experiment, we used ISCAS85 layouts generated with the MCNC 1m SCMOS standard-cell library with 38 components The BrgDmtr was set to 10m; the DDM used is shown in Table 5 In the DDM used in our experiment, 7 layers were dened which belong to three planes: plane1 (poly, n-di, p-di, n-trans, p-trans), plane2 (metal1), and plane3 (metal2) Intra-plane entries were set to 1(unitless) except for plane1, cross-plane entries were set to 1e?4 for plane1-plane2 and plane2-plane3 The DDM entries were set as such because we assumed the intra-plane bridges to be much more likely to happen than the cross-plane bridges BL values contributed by vias and intra-plane1 objects were not considered because we assumed them to be relatively unimportant Though the DDM was set as above, any DDM may be used in FAULTAN For an accuracy verica-

6 Table 5: The Defect Distribution Matrix poly n-di p-di n-trans p-trans metal1 metal2 poly e?4 0 n-di e?4 0 p-di e?4 0 n-trans e?4 0 p-trans e?4 0 metal1 1e?4 1e?4 1e?4 1e?4 1e?4 1 1e?4 metal e?4 1 tion, CARAFE Release Alpha5, a at bridge extractor, was used with the same parameters to compare the bridging fault extraction results; In CARAFE, the bridge extraction mode was used All experiments were done on a SparcStation 20 with 224 mega-bytes of RAM The CFL used by FAULTAN was generated by LIBAN in 61 CPU seconds; it consumed 6 mega-bytes of memory FAULTAN extraction results are given in Table 6 along with the results of CARAFE as a comparison The relations between T, TF, MF, and HF in Table 6 are shown in Figure 7 MF FT TF FT MF CR F HF CR TF CR Figure 7: Relations Between F, TF, MF and HF in Table 6 In Table 6, each sub-column FT represents FAULTAN results and each CR sub-column represents CARAFE results Column 2 (TF) is the total number of extracted faults Except for circuit c499, FAULTAN always nd more faults than CARAFE does Column 1 (F) is the number of matched faults, which are the faults found by both FAULTAN and CARAFE Column 3 (MF) is the number of missed faults which are faults found by one program but not by the other program FAULTAN, in general, has very few missed faults We carefully examined the FAULTAN missed faults into the layout and no error or inaccuracy of FAULTAN has been found We also sampled the CARAFE missed bridging faults some of them seem to be indirect bridges, eg bridge A-C if A is adjacent to B and B is adjacent to C These indirect bridges can be extracted by FAULTAN, however, they can only be extracted by CARAFE under the compound fault extraction mode which takes much longer time and memory than what are showed in Table 6 Except the indirect bridges, other CARAFE missed bridges appear to be valid bridging faults Column 4 (HF) is the number of \harmless" bridges, which are de- ned as the bridges that involve one or two unused feed-through lines in a cell layout The feed-through lines are metal routes put in a cell layout to enable the over-the-cell routing, they are not connected to any net in the gate cell which they reside in and are not necessarily used in the global routing If not used, these feed-through lines become isolated metal pieces in the layout Hence a bridge involving such an unused feed-through line is harmless FAULTAN recognize the unused feed-through lines and harmless bridges through the hierarchical design information so none of the harmless bridges are reported in the fault list Judging from our experiments, harmless bridges constitute on the average 1% of the total number of faults extracted by CARAFE Column 5 in Table 6 is the used memory in kilo-bytes FAULTAN used on the average only 10% of that used by CARAFE Column 6 is the CPU time in seconds, FAULTAN runs on the average 5 times faster than CARAFE Bridge Count e-07 1e-06 1e Bridging Likeliness Figure 8: Bridge count vs BL value for c880 Figure 8 shows the distribution of extracted bridging likelihood values for circuit c880 The two peaks correspond to the two distinct DDM entries (1e?4 for c880

7 Table 6: Comparison between FAULTAN and CARAFE results using ISCAS85 circuits Circuit F TF MF HF Memory(kb) CPU Time(s) FT CR FT CR FT CR FT CR FT CR c c432 2,690 2,812 2, , c499 5,276 5,634 5, , c880 5,186 5,556 5, , c1355 6,768 7,111 6, ,196 11, c1908 7,911 8,404 8, ,296 12, c ,260 19,029 18, ,524 22, c ,233 23,293 22, , ,224 29, c ,852 51,540 50, , ,112 56, c ,707 34,304 32, , ,520 54, c ,550 70,121 68, , ,244 71, Incremental Bridge Count c Bridge Diameter (micrometer) Figure 9: Incremental routing bridge count vs bridge diameter for c1355 cross-plane and 1 for intra-plane) in Table 4 Figure 9 shows the routing bridge count vs bridge diameter for circuit c1355 We can observe that the majority of metal routes in the routing channels are 5m or 12?13m apart, so when the bridge diameter reaches these two lengths the bridge count peaks 4 Conclusion In this paper an ecient hierarchical bridging fault extractor/analyzer package - FAULTAN is described which exhibits high computational eciency, low memory usage, and excellent accuracy FAULTAN program uses a cell fault library constructed by a library analyzer LIBAN program which helps in achieving its high speed and low memory usage With its superior performance and accuracy, FAULTAN forms a key step to fast and high quality test generation for bridging faults References [1] F J Ferguson, J P Shen, W Maly, \Inductive fault analysis of nmos and CMOS integrated circuits," Dept of Elec and Comp Eng, Carnegie Mellon Univ, Pittsburg, August, 1985 [2] M Calha, M Santos, F Goncalves, J P Teixeira, \Back annotation of physical defects into gate-level, realistic faults in digital ICs," IEEE Int Test Conf, pp 720{728, 1994 [3] M Jacomet, \FANTESTIC: Towards a powerful fault analysis and test generator for integrated circuits," IEEE Int Test Conf, pp 633{642, 1989 [4] A Jee and F J Ferguson, \Carafe: An inductive fault analysis tool for CMOS VLSI circuits," IEEE VLSI Test Symp, pp 527{531, 1993 [5] A Jee, D Dahle, C Bazeghi, and F J Ferguson, \Carafe user's manual release alpha5," Board of Studies in Comp Eng, Univ of California, Santa Cruz, Santa Cruz, Jan, 1996 [6] G Spiegel, \Fault probabilities in routing channels of VLSI standard cell designs," IEEE VLST Test Symp, pp 340{347, April 1994 [7] J P Teixeira, I C Teixeira, C F B Almeida, F Goncalves, \A methodology for testability enhancement at layout level," Journal of Electronic Testing, Theory and Application (JETTA), Vol 1, No 4, pp 289{297, Kluwer Academic Publisgers, 1991 [8] R M Iimura, \icharm: Hierarchical CMOS circuit extraction with power bus extraction," Masters Thesis, Univ of Illinois, Urbana, 1990 [9] T Chen, I N Hajj, E M Rudnick, J H Patel, \An ecient IDDQ test generation scheme for bridging faults in CMOS digital circuits," IEEE Int Workshop on IDDQ Testing, pp 74{78, Oct 1996