Welcome. Microprocessor Systems 1 (CS3D1) Trinity College Dublin Mike Brady

Transcription

1 Welcome Microprocessor Systems 1 (CS3D1)

2 This is or all C/CD/D Stream Engineers Optional for Mathematics & MSISS Sophisters Visiting Students 2

3 Maths Terminology: CS3D1 + CS3D4 = Maths 372 3

4 3D1 is designed to be a prelude to: 3D2 Microprocessor Systems 2 (Architecture & Hardware) 3D4 Concurrent Systems 4

5 What is in 3D1? An introduction to a bare computer system - without compilers, operating systems, etc. We look at the basic structure or architecture of a typical microprocessor, the Motorola We look at the resources available for performing computations. 5

6 Assembly Language This is a very low-level language each statement is [almost] exactly equivalent to one machine instruction A machine instruction is obeyed directly by the machine's hardware. 6

7 Input/Output As well as writing programs, you will find out how a computer system can interact with objects and mechanisms in the outside world - i.e. external to the computer. This is Input/Output, or IO programming. 7

8 Hardware Issues You will be given a fast, brief, introduction to some aspects of the hardware of the computer no knowledge of electronics necessary! 8

9 68000 Processor The is the base member of a family of microprocessors , 68020, 68030, 68040, (?). The is a kind of CISC - a Complex Instruction Set Computer. 9

10 Course Topics (1) Review of Binary and Hexadecimal Arithmetic The Von Neumann Machine The Programmer s Model of the MC68000 Data Representation: integers, characters, signed representations, arrays 10

11 Course Topics (2) Addressing modes: immediate, direct, indirect The Condition Code Register Conditions and conditional branching Program flow control: unconditional branch and jump 11

12 Course Topics (3) High-level language constructs: while, if, for, etc. Some complex instructions Subroutines: mechanisms and parameter passing 12

13 Course Topics (4) Principles of Input/Output: polling Supervisor & user mode Interrupts and interrupt handlers Exceptions and exception handling Producer consumer organisation; queues and buffers 13

14 Course Topics (5) Introduction to the System Bus Instruction Execution Instruction Timing 14

15 Coursework There will be lots of course work: Tutorials: every week, Thursday 12 Programming: a two-hour practical every week. Practicals will be marked for Continuous Assessment, which will be worth up to 20% of your course mark 15

16 Coursework (2) The course work is a very important part of the course. The only way to learn about the computer is to use it - if you don't use it, you won't learn anything. 16

17 Coursework is Mandatory You are required to attend practicals and obtain a pass mark in Continuous Assessment. Failure to do so may result in the return of N/ S grades, withholding of results and/or a denial of permission to sit the Examination. 17

18 References Family Assembly Language by Alan Clements ISBN (Recommended, or similar, not mandatory) Look on the Web. Look at 18

19 Introduction The Von Neumann Machine Bus Central Processing Unit (CPU) Memory Subsystem (RAM) Memory Subsystem (ROM) Peripheral Interfaces Screen Networks Keyboard Disk Drives Printers 19

20 The CPU The Central Processing Unit (CPU) is where all the work is done. It contains the hardware resources required to execute instructions. These resources are used by the CPU s instruction set. 20

21 The Instruction Set This is the set of instructions that a particular make of CPU can recognise. A machine language program is a set of instructions which utilise the CPU's resources to perform some specified tasks on data. 21

22 Memory Memory is simply a mechanism in which information can be stored. The only operations that can be performed on memory are reading information from it, or writing information to it. Memory is used to store everything data and instructions that has to be accessible to the CPU. 22

23 Contents of Memory The instructions in the program currently being executed The data upon which the program is currently operating. 23

24 Peripherals Peripherals are devices external to the computer system. They are connected to the system through gateways called interfaces. 24

25 Peripherals Maketh the Machine Some peripherals include Terminals, Disk Drives, Printers, but there are many different ones in industrial applications. A telephone exchange could be considered a peripheral if it is controlled by the computer. 25

26 Embedded Computers A computer wholly contained within a machine, e.g. mobile phone, is said to be embedded. The market for embedded computers is larger than for ordinary computers. Energy consumption is often very important for embedded computers. 26

27 Microprocessor A Microprocessor is simply a CPU on a small number (usually 1) of integrated circuit packages. Often called a Microprocessor Unit (MPU). Abbreviated μp. 27

28 Microcomputer A Single-Chip Microcomputer is a complete computer system on one integrated circuit package - it has a CPU, memory and interfaces all on the chip. 28

29 Tutorial (1) Binary Representations & Arithmetic Convert the following binary numbers to decimal: , , ,

30 Tutorial (1) Binary Representations & Arithmetic Using the accompanying ASCII code table, convert the following 'character string' into binary: This is a string. 30

31 Tutorial (1) Binary Representations & Arithmetic Write an assembly language program to find the (integer) average value of ten unsigned word integers. The numbers are stored in an array starting at $2000. The result should be placed in $1FFE. You'll need the unsigned divide instruction - DIVU. 31

32 Tutorial (1) DIVU <source>,<destination> The destination must be a data register. The source can be anything sensible. This instruction will divide the longword destination by the word source, replacing the longword destination with two words. The least significant word is the integer result, and the most significant word is the integer remainder. 32

33 Microcomputer A Single-Chip Microcomputer is a complete computer system on one integrated circuit package - it has a CPU, memory and interfaces all on the chip. 33

34 Programmer s Model Of a Computer System Bus Central Processing Unit (CPU) Memory Subsystem (RAM) Memory Subsystem (ROM) Peripheral Interfaces Screen Networks Keyboard Disk Drives Printers 34

35 Simpler Version Microprocessor Address Number Contents 16,777, ,777, ,777, CPU Bus Memory 35

36 Programmer s Model of the CPU D0 D1 D2 D3 D4 D5 D6 D7 EIGHT DATA REGISTERS A0 A1 A2 A3 A4 A5 A6 SEVEN ADDRESS REGISTERS CCR 0 A7 (USP) PC SR CCR USER STACK POINTER PROGRAM POINTER COUNTER STATUS STATUS REGISTER REGISTER 36

37 Our Programmer s Model Memory -- programs and data are stored there; everything is in binary. Memory is byte-addressable -- see later. Processor -- our processor is the Motorola It has sixteen 32-bit registers plus a Status Register and a Program Counter. We ignore peripherals for the present. 37

38 Memory Organisation The smallest quantity of information in binary is the bit - it is an item that has the value 1 or 0 (just two values allowable - hence "binary"). In the 68000, as in most computers, bits are clustered into ordered groups of 8 bits, called a byte. So a byte is an item containing 8 bits. Each of these bits can be 0 or 1. 38

39 Memory Addressing In the 68000, each byte is numbered, starting at 0. So, you can refer to a particular byte by its byte number or byte address. Other terms: Memory Address, Location, Memory Location. 39

40 Memory Organisation Byte Byte Byte Byte MSB LSB MSB LSB Word Word Longword

41 Memory Organisation Since the smallest number of bits that can be addressed (by hardware) in the is 8, its memory is said to be byte addressable. In other machines, notably RISCs, the hardware can often only address a minimum of 32 bits. 41

42 Words In the 68000, two adjacent bytes together form a word. (This definitiion of a word is specific to the family.) The location of the word is taken to be the location of the byte with the smaller address. 42

43 Longwords Four adjacent bytes together form a longword. (Again, this is a specific definition) The location of the longword is the location of the byte with the smallest address. That byte is also the most significant byte. 43

44 Even Address Alignment Due to a hardware restriction in the original 68000, all words and longwords must begin on an even-numbered address. 44

45 Nybble A nybble or nibble is a four-bit quantity. Thus, two nybbles in a byte. Nybbles are historically significant -- a nybble can hold a single decimal digit. 45

46 Data Representation Everything the computer processes must be representable in binary, including all data. Also, the representation scheme used must be finite. 46

47 Data Representations Data Representation Scheme??? Bits Integers Characters Binary (signed/unsigned) Binary Coded Decimal ( BCD ) (signed/unsigned) ASCII ((American Standard Code for Information Interchange) Unicode Real Numbers IEEE Floating Point Standard

48 Our Data Representations We will examine integer and character representations, and we ll use bits for things. We will not examine floating point. The does not have floating point instructions -- they were added later in the family. 48

49 Unsigned Binary Integers are represented using ordinary binary. The architecture supports (i.e. has hardware that can operate directly on) byte-sized word-sized and longword-sized unsigned binary integers. 49

50 Sample Unsigned Byte Bit Number Weight Bits 2 7 = The weight of a binary digit is 2^(the bit number). Handy. The smallest value is ; the largest That is, 0 to 255, or 0 to

51 Sample Unsigned Word Bit Number Weight Bits Value: = 46,775. The smallest value is ; the largest is , i.e. 0 to 65,535, or 0 to Binary is unwieldy, awkward for big numbers 51

52 Hexadecimal Value Binary Hex Decimal A B C D E F 15 Hexadecimal is Base 16 number notation. Preceded by a $ (assembly) or by 0x (C, C++, etc.). There is a one-to-one bidirectional correspondence between a single hex digit and 4 binary digits. Thus, hexadecimal is a very useful shorthand for binary. 52

53 Hexadecimal Hexadecimal is base 16 number notation. Sixteen digits: 0,1,2,3,4,5,6,7,8,9,A,B,C,D,E,F. Same idea as decimal (base 10) or binary (base 2), it is a positional notation for quantities: each digit has a weight that depends on its position in the number. A digit s weight is the base raised to the power of its position number, with the rightmost position number being 0. E.g. $A6 is A* * = 1010* *110 =

54 Hexadecimal Very easy to convert between binary and hexadecimal make groups of 4 bits from least significant end, and look up their hex equivalent digit. Groups of 4 bits ( nybbles ) fit very well into bytes etc. Thus, we use hexadecimal very extensively as a shorthand for binary. Note: hexadecimal is usually used as a shorthand for the binary pattern. It is not an interpretation of the pattern s meaning. 54

55 Longword Unsigned Binary Longword unsigned binary goes from $ to $FFFFFFFF to , or: i.e. 0 to 232-1: 0 to 4,294,967,295 (Four giga-) where a giga- is

56 Unsigned Binary Unsigned binary is used to represent integers. Fast & compact. Add, subtract, multiply, divide, compare all supported in hardware. 56

57 Signed Binary Idea: to be able to represent the sign of a number, not just its magnitude, e.g. -234, +1,635. To be able to perform signed calculations, preferably without using much extra hardware. 57

58 Representation Choices Use one bit to represent sign, the other bits to represent magnitude ( Sign and Magnitude ). E.g: Bit Number Sign (1 = ) Bits Represents:

59 Problems with Sign and Magnitude Two versions of zero: +0 and -0! Extra hardware needed for calculations 59

60 Two s Complement Notation This is called Two s Complement notation. If a number is positive, represent it with straight binary If a number is negative, represent it in two s complement form. In a machine with fixed width number representation, ensure: If positive, the MS bit must be 0; If negative, the MS bit must be 1. 60

61 Getting Twos Complement To get the twos complement of a number: Size it to the correct width, introducing leading zeroes as necessary. Flip each bit: 0 to 1 and 1 to 0 Add 1. 61

62 Features One version of zero: +0 Slight asymmetry of magnitude representation. Same hardware can be used. 62

63 Tutorial 2 How would you calculate the average of an array of, say, a million unsigned word integers? What instructions or facilities do you really need to do this in a practical way? 63

64 Program Flow Control To do this sensibly, we need to get the same sequence of instructions executed multiple times -- we need to control the flow of program execution. But wait there s more 64

65 Runtime Address Calculation It s no use executing exactly the same operations over and over. For example, we have to be able to get a different element (actually the next element) each time. Here, we need to be able, while the program is executing, to vary the address an instruction uses. 65

66 Oops Sorry -- I forgot to record this lecture. 66

67 Binary Representation Summary Size Representation Range Byte Unsigned Binary ( ) Byte Signed Binary ( ) Word Unsigned Binary ( ) Word Signed Binary ( ) Longword Unsigned Binary ( ) Longword Signed Binary ( ) 67

68 Addressing Modes As well as hardware for executing instructions, a processor needs hardware to access data. Hardware needed to read and write data to and from registers and memory. The capabilities of the accessing hardware are reflected in the processor s instruction set in the so-called addressing modes it the processor instruction set recognises. 68

69 Addressing Modes (2) So, the term addressing modes refers to the allowable ways in which the processor instructions can refer to data. CISC processors tend to have many different addressing modes. RISC processors tend to have a very small number of addressing modes. 69

70 Categories of Addressing Modes You select an appropriate addressing mode for a piece od data depending on how much you know about the data item itself when you re writing the program: If you know the value of the data, use an Immediate Addressing Mode, signified by a # sign. If you know the location of the data, use a Direct Addressing Mode. If you know how to calculate the location of the data or how to calculate the data itself, use an Indirect Addressing Mode. 70

71 Kinds of Addressing Mode Summary Level of Knowledge of Data Kind of Addressing Mode Value can be known at assembly time Immediate Mode (Immediate Values are sometimes called Literals ) Location can be known at assembly time Direct Mode Location or value can be calculated at run time Indirect Mode 71

72 Addressing Modes in the The has fourteen addressing modes, I think. We will look at eleven: Two immediate modes Four direct modes Five indirect modes The remaining three are a special case of the indirect modes. 72

73 Immediate Addressing Modes Immediate : Specify the operand as a byte, word or longword item. All sensible values permitted of eight, 16 or 32 bits as appropriate. Only values known at assembly time allowed, e.g. #21, #$60FA, #$12234-$24 #(567*$ab)- x 73

74 Immediate Addressing Modes (2) These are not permissible as immediate operands: #61+D0 #$74+(A4) Why? 74

75 Quick Immediate Instructions Some instructions and operands occur very frequently in the instruction execution stream, and some of these are speeded up by making the instruction shorter: MOVE has a MOVEQ ADD and SUB have ADDQ and SUBQ Each of these instructions expects a quick immediate operand with a restricted range of values. 75

76 MOVEQ (Move Quick) Allows eight bits to represent the immediate data. The destination must be a data register. The eight bit data is sign-extended to fill all 32 bits of the data register. 76

77 ADDQ and SUBQ (Add and Subtract Quick) Allows three bits to represent the immediate data, which is mapped to the values 1 to 8 (not 0 to 7!) Size of the operation can be specified to byte, word, long The destination is not restricted to be a data register. The three bit data is sign-extended to fill the size of the operation specified 77

78 Direct Addressing Modes The Operand is in a Register ( Register Direct ): Data Register Direct Address Register Direct The Operand is in Memory ( Memory Direct ) Absolute Memory Short Absolute Memory Long 78

79 Register Direct Just specify the register on its own, no brackets or anything. E.g. A4, D3 Address Register Direct An Data Register Direct Dn 79

80 Memory Direct Just specify the memory location directly, e.g. 21, $12FA, $ a Notice the syntactic (i.e. grammatical) difference between immediate and direct: what is it? 80

81 Address Space The processor family, being a fully 32-bit family, has a 32- bit address space (i.e distinct byte locations in memory.) The itself only uses 24 bits of the available address space. This is a hardware restriction of the itself. To write portable code, write for a 32-bit address space. Memory Direct modes are used to specify where an operand is in memory. 81

82 Two Memory Direct Modes For reasons that are perhaps partly historical and partly speed motivated, the has: a 16-bit direct addressing mode called Absolute Memory Short along with a 32-bit direct addressing mode called Absolute Memory Long A 16-bit address is an address represented by only 16 bits, thus only 2 16 (i.e ) distinct locations can be specified. 82

83 Absolute Memory Long This is just the memory referencing addressing mode you would expect in a 32-bit machine. You can specify any address in the 32- bit address space, e.g. $f ,, $ a etc. As with immediate modes, you can use any expression that may be evaluated at assembly time as an absolute memory reference. The address is represented in the instruction as a 32-bit item. 83

84 Absolute Memory Short To save space in an instruction, an abbreviated address can be stored in 16 bits. It is sign-extended to the full 32 bits when needed. This means the range of addresses is limited to: $ $00007FFF, $FFFF8000 $FFFFFFFF, i.e. the bottom and the top of addresses in the full 32-bit address space Because it is only 16 bits, the instruction of which it is part is fetched faster. 84

85 Indirect Addressing Modes We will look at five indirect addressing modes in the course, but now we ll just look at one -- Address Register Indirect. You can make up the functionality of most the other indirect addressing modes from this; they are provided for convenience and speed. 85

86 Motivation for Indirection To use a number as an address. In other words, to be able to calculate the location of something, and then, crucially, to be able to use it as an address and reference something with it. 86

87 Program Flow Program flow is normally sequential: The next instruction to be executed (in the flow of program execution) is the next instruction in memory. This assumption is built in to the Von Neumann architecture. 87

88 Progam Flow -- Other Ideas Program flow could be non-sequential. An instruction could explicitly contain the address of its successor instruction. Great flexibility Performance issues Lots of different architectures tried over the years -- e.g. look up data flow machines from the 1970s and 1980s 88

89 Program Flow -- the PC The program counter register in the CPU -- the PC -- always contains the address of the next instruction. In hardware, while the current instruction is being executed, the address of the next one is in the PC. (Only the first 24 bits of the PC are used in the 68000, but like all address, you should treat it as a 32-bit quantity) 89

90 Changing Program Flow To change the flow of program execution, you need instructions that change the PC s value. These are branch and jump instructions. Branch and jump instructions operate by replacing the PC s value with the address of the desired target instruction -- the destination address 90

91 Branch vs. Jump Instructions These instructions are basically the same, and differ in how they encode the destination address: Branch instructions encode the difference (the delta ) between the current address and the destination address -- position-independent and compact. Jump instructions encode the destination address using any standard addressing mode -- more flexible, e.g. for implementing a switch statement or a computed goto. 91

92 The Instructions BRA <destination> ; branch always. Destination is encoded as a signed byte ( short branch ) or signed word. Question: what s the range of a branch? JMP <ea> ;jump. Destination can be specified using any sensible memoryreferencing effective address 92

93 Yeah, but Problem is that these are unconditional program flow-altering instruction. From a theoretical standpoint, a property of a computer program is that it can alter its own behaviour in response to data. Thus, we need to be able to alter program flow in response to data. This is done by calculating conditions and storing them in the CCR having flow-control instructions that act conditionally in response to what s in the CCR 93

94 Conditional Instructions These are instruction that only have an effect if a particular condition holds true. In the 68000, conditions are boolean expressions that take the five bits of the CCR, true, false and the boolean operators and, or and not. 94

95 Conditions the recognises Status Register X N Z V C System Byte Condition Code Register 95

96 Example Write a complete program to count all the vowels in a NULterminated character string. Define a suitable character string and also a longword result space. 96

97 Tutorial 3 Search TCD go Microprocessor Systems 1 (CS3D1) Department of Computer Science Tutorial 3 Conversion When a user enters a number to a computer, it is almost always in the form of a string of characters representing the decimal form of the number. Internally, as you know, the number can be represented in binary. Write a program that 'reads' a NUL-terminated character string that represents a decimal number and produces an unsigned binary word representation of the magnitude of that number. For example, if the number is 124, the sequence of characters will be '1','2','4',NUL. What you want to end up is the unsigned binary word representation of the number, Home Learning Outcomes Course Topics Assessment Podcast Tutorials Tutorial 2 Tutorial 3 Tutorial 4 Tutorial 5 Practicals Results Recommended Texts Online Resources Mike Brady Contact, College Green, Dublin 2, Ireland. Tel:

98 Practical 2 Search TCD go Microprocessor Systems 1 (CS3D1) Department of Computer Science Practical 2 Translation to ASCII -- 2% Write a complete program to translate a signed binary word integer to a NULterminated sequence of ASCII characters denoting its decimal numeric form. Define a sample number and reserve sufficient space to store the resulting character string where they can be examined with the debugger. Show your work to the demonstrator, who will award you a mark out of 10. The value of this practical is 2% of your year-end mark. Note Always be sure your attendance is noted. Home Learning Outcomes Course Topics Assessment Podcast Tutorials Practicals 1: Familiarisation 2: Integer - to - ASCII 3: Subroutines 4: Eratosthenes Results Recommended Texts Online Resources Mike Brady Contact, College Green, Dublin 2, Ireland. Tel:

99 Calculating Conditions in the CCR Many instructions have an effect on the X,N,Z,V and C bits of the CCR. In the Instruction Set Summary: * means the bit is affected as you might expect -- see later means the bit is unaffected -- it retains its present value 99

100 What you might expect X The extend bit. This is the same as the carry bit, but is only affected by a subset of the instructions that affect the carry bit -- the arithmetic instructions. Set if arithmetic carry or borrow has occurred. N The negative bit. Set if the result is negative; cleared otherwise. Z The zero bit. Set if the result is zero; cleared otherwise. V The arithmetic overflow bit. Set if sign overflow occurred; cleared otherwise. C The carry/borrow bit. Set if arithmetic carry or borrow; cleared otherwise. 100

101 Some Instructions Some instructions have no effect apart from their effect on the CCR: TST, CMP, BTST, etc The purpose of these instructions is to calculate an appropriate condition and place it in the CCR so that it can have a desired effect on program execution. E.g. a CMP instruction can be used to calculate the condition that, say, a variable s value is 10. CMP.L #10,D7 101

102 CMP -- the Compare Instruction This is exactly like a SUB instruction, execpt that it doesn t replace the second operand with the result. So a CMP instruction sets the CCR as if the first operand had been subtracted from the second. 102

103 TST -- the Test [against zero] Instruction This is somewhat equivalent to CMP #0, 103

104 BTST -- the Bit Test Instruction Part of a family: BTST, BSET, BCLR, BCHG Bit Test, Bit Set, Bit Clear, Bit Change If the bit you specify is zero, sets the CCR s Z bit I.e. puts the inverse of the bit into the CCR s Z bit. If the bit you specify is one, clears the CCR s Z bit 104

105 Overall Flow Control Unconditional BRA or JMP Conditional: Calculate condition into the CCR Select appropriate conditional branch Bcc, where cc is any one of the 16 conditions listed in the last page of the instruction set summary: 105

106 Conditions the recognises Status Register X N Z V C System Byte Condition Code Register 106

107 Example Check if a character is a digit character, i.e. in the range

108 So Far We know how to write regular code to specify data and operations like add, subtract, compare, etc. sufficient for any purpose. We know how to modify and control the flow of program execution, conditionally and unconditionally. We know how to map high-level flow control constructs like while, for, if to assembly language We don t yet know how to implement functions, procedures or methods at assembly language level. 108

109 Subroutines Functions, methods and procedures are mostly implemented at assembly language level as subroutines A subroutine is simply a section of code designed to be called (branched or jumped to) from many places. The first problem with subroutines is the issue of returning to the place from where the call was made. 109

110 JSR and BSR To solve the return problem, the BSR and JSR instructions store the address of the next sequential instruction just before they branch or jump to the subroutine. They store the return address in The Stack. 110

111 The Stack (A7) Stack contents: $69,$94,$D4,6D Top of Stack pointed to by a stack pointer. In the 68000, A7 is reserved for use as a stack pointer to The Stack, hence, A7 is often called the Stack Pointer (SP). You can have other stacks if you want; just don t use A7. 111

112 Pushing [to] the Stack (A7) A word was pushed into the stack: The stack grew downwards sufficiently to fit the item Contents of the stack didn t move in memory instead, the top of the stack moved (pointed to by A7) New contents: $EF,$0A,$69,$94,$D4,6D 112

113 Popping [from] the Stack A longword was pulled or popped from the stack: The stack contracted upward Contents of the stack didn t move in memory instead, the top of the stack moved (pointed to by A7) New contents: $D4,6D (A7) 113

114 Frequent Stack Pointer Operations Add Item Adding an item to a stack consists of subtracting sufficient from the stack pointer to make room at the top of the stack for the item: (1:byte, 2:word, 4:longword, etc.) moving the item to the location now pointed to by the stack pointer New addressing mode: Address Register Indirect with Pre- Decrement Look like: -(An) 114

115 Frequent Stack Pointer Operations Pop Item Popping an item from a stack consists of moving the item from the location pointed to by the stack pointer adding sufficient to the stack pointer to take up the space at the top of the stack formerly occupied by the item: (1:byte, 2:word, 4:longword, etc.) New addressing mode: Address Register Indirect with Post- Increment Look like: (An)+ 115

116 Subroutines Calling When a subroutine is called, the address of the next instruction (the return address ) is pushed onto the stack 1040 moveq #0,d jsr foo 1046 $001010fe 11 $001010fc $FABB (SP) $001010fa 6578 $001010f8 $???? $001010f6 $???? 116

117 Subroutine Exiting D0 D1 D6 D7 PC SR A0 A1 A A7 $001010f6 $001010fe 11 $001010fc $FABB $001010fa 6578 $001010f (SP) $001010f6 0 When the subroutine finishes, it executes the RTS instruction, which pops a longword from the stack into the PC 117

118 Program Context While a program is running, it has access to memory locations, registers, peripherals, etc. The set of all these with their contents, is called the program s context. A running program could be characterised at any instant by its context and its program code. 118

119 Processes and Threads A saved context and program code is almost like a freezedried program just add water a processor, and the process comes to life. The combination of context and code is sometimes called a process. [I m not really talking about Unix processes here.] A process can be running or stopped. Part of the job of an operating system is to schedule processes to give them time on a processor. 119

120 Well Behaved Subroutines Subroutines run in the same context as their callers same register values, memory locations etc. Thus, subroutines are part of the caller s process.they are not independent of the caller. Care must be taken to ensure that subroutines do not damage the context of their callers. In a kind of shorthand, use of subroutines must be, eh, ecological with respect to the environment. 120

121 Ecological Subroutines Easy To Use Subroutines should be easy to understand! Ideally, subroutines are like building blocks, each just implementing one functionality. Subroutines should do exactly and only what is specified and absolutely no more. It is a serious error for a subroutine to do more than specified. Extra features frequently have unintended consequences. The scheme for passing parameters should be simple and neat. 121

122 Ecological Subroutines Register Use If a subroutine uses a register for something, there s a chance it s already in use by the caller, so its contents may be important. Therefore, its contents must be saved before use, and then restored afterwards. In that way, the register s contents are preserved for the caller. Can be a bit costly! 122

123 Ecological Subroutines Suggested Rules Use registers to pass parameters to and from a subroutine, where possible. Use parameter blocks where possible. Use the stack if necessary. Save register contents to the stack before using the registers: That way, you can restore their original contents before returning to the caller. If a subroutine needs memory space, take it from the stack, if possible. Make sure all uses of the stack are balanced, i.e. pushes=pops. 123

124 Ecological Subroutines Memory Use Imagine a computer with two processes, both calling the same subroutine at the same time. if the subroutine is written to always use the same memory locations to save private data, then Both copies of the subroutine could write their own private data to the same memory locations at the same time, causing severe problems. Such a subroutine would not be re-entrant Therefore, a subroutine should avoid using fixed memory locations for anything. 124

125 Simple Example Let s take a simple example of implementing a C-type function called max: int max(int a,int b) { /* result, a and b are parameters, use stack */ int r = a; /* r is a local variable, allocate on stack */ if (a<b) r = b; return r; } 125

126 (a7) Space for Result Value of a Value of b Return Address Saved Register Saved Register Local Variable r' Stack Frame for the call to max This depicts the stack when the subroutine is running, after it has saved two registers and defined a longword local variable r 126

127 Stack Frames A stack frame corresponds to a separate copy, or instance of a function. When the function is called, its stack frame is allocated space on the stack, and the function instance s local variables come into existence. When the function exits, the frame is deallocated, and the local function instance, along with its local variables, goes out of existence. The lifetime of variables in the stack frame corresponds to the variable scoping rules of a high level language like C. (C++ is a little smarter) 127

128 Linking Stack Frames A function instance has its own stack frame. Its caller also has a stack frame In turn the caller s caller has a stack frame It is generally necessary to link the stack frames so that a function instance can locate its caller s local variables (or its caller s caller s local variables. etc.) To make this easy, the has a LINK and UNLK instructions. LINK is also very useful for accessing stack variables. 128

129 Tutorial 4 Write a subroutine to read and evaluate simple expressions involving unsigned word integers and the usual arithmetic operators (+, -, * and /). The expressions are stored as NULterminated ASCII character sequences of the form: [integer] [operator] [integer] [end] For example: 651 * 70 There may be white space characters between the components. 129

130 Practical 3 Search TCD go Microprocessor Systems 1 (CS3D1) Department of Computer Science Practical 3 Translation to Binary 3% Last week, you were asked to translate from signed binary to NUL-terminated ASCII. In class, we also looked at translating in the other direction -- ASCII to binary. This week, the assignment is to write a complete, well-behaved subroutine to translate from ASCII to binary: Write a subroutine to translate a sequence of ASCII characters, meant to represent a signed decimal number, to a signed binary longword in D0. A0 should contain the address of the first revelant character of the ASCII character string. D0 should return the signed binary longword. Home Learning Outcomes Course Topics Assessment Podcast Tutorials Practicals 1: Familiarisation 2: Integer-to-ASCII 3: Subroutines 4: Eratosthenes Results Recommended Texts Online Resources Write a main program to call and test the subroutine with a few sample character strings. One way of solving this problem requires multiplication by 10, but there is a complication. The complication is that the doesn't have longword multiplication. Of course, you could use a long multiplication routine. But it there a better [simpler/faster] way? Here is a hint: shifting a bit pattern by 1 bit position to the left, (see ASL, LSL), is the same as multiplying it by 2. Show your work to the demonstrator, who will award you a mark out of 10. The value of this practical is 3% of your year-end mark. Note Always be sure your attendance is noted. Mike Brady Contact, College Green, Dublin 2, Ireland. Tel:

131 Instruction Encoding You need to understand the scheme by which how instructions are encoded to understand how to select the fastest or most compact instructions. We ll look at encoding schemes We ll look at approximate speed calculations We ll look at what an assembler does 131

132 Instruction Encoding Everything all the instructions, operands and addressing modes is encoded in binary code. In RISCs, every instruction should be exactly the same length in machine code, typically 32 bits. This makes looking ahead at upcoming instructions simpler. In the 68000, instructions are of variable length. A one-word operation word Zero or more extension words 132

133 Instruction Execution Overview Fetch the operation word Decode the operation word* Fetch the rest of the instruction the extension words Fetch any off-processor operands Perform the operation itself (usually zero!)* Time to put away results to off-processor locations 133

134 Makeup of a Instruction op-word zero or more extension words (max: four) (PC) The operation word contains: the operation and size, e.g. MOVE.W, MULU, BNE the types of addressing mode(s) used to reference the operand(s) [with one exception] the registers used quick immediate operands 134

135 Extension Words Used to hold the components of operands that won t fit into the operation word: Addresses -- for absolute memory long and short Immediate values -- bytes, word, longwords (not Quick Immediates -- they are stored in the operation word). Offsets -- for the addressing mode Address Register Indirect with Offset Index Register and Offset -- for the addressing mode Address Register Indirect with Index Register and Offset 135

136 Extension Words -- Details Mode Size Extension Words byte 1 word Immediate word 1 word longword 2 words Absolute short long 1 word 2 words Address Register Indirect (and PC-Relative) With [16-bit signed] Offset With Index Register and [8-bit signed] Offset 1 word 1 word All Other Modes 0 words 136

137 Instruction Execution Timing Get a good estimate by calculating the number of bus transactions required to: Fetch the instruction and its extension words Fetch the off-processor operands Put away the off-processor results. The bus can transfer one word (or part) in each transaction (a bus cycle). On the 8MHz 68000, a transaction takes 0.5μS. 137

138 Extra Details These estimates assume that bus transactions always take a fixed amount of time. However: an instruction cache could shorten bus transactions fetching an instruction; a data cache could do the same for fetching or putting away data. So, these would be worst-case estimates for a machine with a cache. The doesn t have a cache. 138

139 Extra Details The has a one-instruction look-ahead facility: While the current instruction is being executed, the operation word of the next one is being fetched. Any operation that takes less than one bus transaction is invisible and doesn t add any overall time to instruction execution (as per our assumption). A branch requires the pre-fetched operation word to be discarded penalty: one half of a bus transaction Multiply and divide instructions take way in excess on one transaction. 139

140 Using Instruction Timings With your knowledge of instruction timing, you can work out: How long a sequence of instructions will take to execute What are the best instructions and addressing modes to use 140

141 Input/Output How can we make the connection between the world in which we have started to program let s call it the Von Neumann world to things in the outside world, things we might need to control or simply to know about? This is what Input/Output is about getting a computer program to know and respond to events in the outside world. 141

142 Interfaces Whatever aspects of the outside world we are interested in knowing or changing have to be made into an accessible form inside the Von Neumann world. This is the function of interfaces. An interface mediates logically and physically between part of the outside world and the world on the computer. 142

143 Input Interfaces An input interface would physically translate some aspect of the outside world into a binary digital signal. For instance: The opening and closing of a switch could become a 0 or a 1. An audio signal could be sampled at intervals and the magnitude of each sample converted by an analog-to-digital converter to a 16-bit number, e.g. CD-quality stereo, where 16-bit samples are taken of left and right channels at the rate of 44,100 times per second. 143

144 Output Interfaces An output interface converts a binary code into something that has an effect in the outside world. For instance: A bit set to 1 physically causes a display to light. A bit set to 1 physically closes an electrical circuit to turn on a motor. A sequence of 16-bit patterns sent to a digital-to-analog converter physically generates an electrical signal to drive an audio amplifer to reconstruct a sound. 144

145 Wait there s more So, interfaces physically mediate data into and out of the computer system. But, two other aspects of interfaces need to be considered: Timing/Synchronisation The interfaces must logically fit into the Von Neumann world. 145

146 Timing/Synchronisation Data becomes available at a particular time (think of typing on a keyboard). A program must be able to determine the timeliness of input. Similarly, output can only occur when the output device is ready i.e. capable of receiving commands and data. A program must be able to determine when data can be sent. 146

147 Interface Data We can account for three kinds of data flowing through an interface: Data Inwards Data Outwards Timing/Synchronisation Information 147

148 More Interface Data: Status Status information: This is information about the state of the interface itself, and often includes timing or error information about the data coming in or going out. 148

149 More Interface Data: Control Control information: This is data that affects the configuration and overall operation of the interface. Many interfaces have different modes of operation, and have extra optional facilities, etc. Typically, an interface is set up, or initialised when the computer starts up, and is configured using appropriate command codes. 149

150 Making Interfaces Visible Interfaces must fit in to the Von Neumann world, logically and physically. In general, there are two ways: Put the interface on the bus, and make it respond to memory locations. That is, instead of having RAM/ROM chips responding to addresses, why not make interfaces respond to addresses on the bus? Since the interfaces occupy parts of the memory address space, this is called Memory Mapped Input Output. Regular instructions can be used to access the interface, since it occupies memory. 150

151 Example 16 Key Keypad A B C * 0 # D 151

152 Tutorial 5 Search TCD go Microprocessor Systems 1 (CS3D1) Department of Computer Science Tutorial 5 Polled Input/Output Imagine you have a 16-key keypad, interfaced to your computer at location $F05204, providing a 2-of-8 code for each key. You have to write a subroutine to read a character from it into D0. The problem is that the switches suffer from "bounce" -- when they change state (from open to closed or from closed to open), the springiness and inertia of the moving parts combine to make the contacts open and close rapidly and irregularly for a short period, usually less than 5 milliseconds before finally settling into their new state. Write a subroutine that reliably and consistently returns the ASCII code of a key when it is pressed. Home Learning Outcomes Course Topics Assessment Podcast Tutorials Tutorial 2 Tutorial 3 Tutorial 4 Tutorial 5 Practicals Results Recommended Texts Online Resources Mike Brady Contact 152

153 Practical 5 Microprocessor Systems 1 (CS3D1) Department of Computer Science Practical 4 Watching the Sieve of Eratosthenes 3% This practical can be done in two stages implementing the sieve and then implementing the display. The Sieve of Eratosthenes is a classic algorithm for discovering prime numbers. Basically, each number in the range you want to search is included in the set of possible primes. Then, a procedure is followed to remove all the multiples of every number except 1 (i.e. non-primes or 'composite' numbers) from the set. What you have left in the set must be the primes in that range. Find out how to the algorithm works, devise a suitable data structure for the sieve and write a complete program implementing the Sieve of Eratosthenes for numbers up to about 20,000. Home Learning O Course To Assessme Podcast Tutorials Practicals 1: Familia 2: Intege 3: Subrou 4: Erato Results Recomme Online Res The Development Systems have a considerable number of peripheral interfaces. Perhaps the simplest of these is a write-only interface at $ Each bit written to this location controls a red Light-Emitting Diode (LED). (There's a wiring bug in the design see if you can figure out what it is.) Modify the sieve program to make a walking light on the 8-led display, that is, each time a new prime is discovered, a LED should come on for a while. When the next prime is discovered, the currently-lit LED it should go off and the LED beside it should come on for a while, etc. When the lighted LED is at the end of the row of LEDs, the next LED to light should be at the far end of the row. 153 A hyothesis is that the interval between changes in the display lengthens as the interval between primes rises. It it true?

154 Block Diagram of a [hypothetical] UART Rx Tx Rx: Serial to Parallel Tx: Parallel to Serial Status Control DataIn DataOut BUS 154

155 Polling Easy to understand; Relatively easy to program for simple situations; Almost unmanageable for moderately complex situations Very difficult for easy-to-foresee situations, e.g. when peripherals are added or removed from a system; Can be very wasteful. 155

156 Central Issue Problem is, IMHO, that polling puts the responsibility on the processor for finding out if I/O is needed. Processor devotes most or all of its attention to one or a few peripherals. 156

157 Solution Interrupts One solution is to remove the polling requirement completely. This can be done by making the interface notify the processor when it needs attention this is called an interrupt request. The processor can then attend to the interrupt using a program called an interrupt handler, and can resume whatever it was doing before when finished. 157

158 Interrupts Exceptions Actually, the classifies interrupts as a kind of exception. We should look at exceptions and exception handling first So, we ll park discussion of I/O until later. 158

159 Exceptions Normally, the executes instructions, as we ve been seeing. However, it has extra hardware to recognise and to deal with exceptional situations, such as: Errors Hardware notifications Elective exceptions 159

160 Exceptions At the start of every exception, the following steps are performed by the hardware. 160

161 Exception Handling Initials Steps If exception is not RESET make internal copy of the SR. Turn off T bit, turn on S bit. (If exception is RESET, then set I 2I1I0 of SR to 111. External interrupts are handled slightly differently see later.) If exception is not RESET, save current PC and internal copy of SR on stack. 161

162 Exception Handling Initials Steps From the source of the exception, and possibly other information, determine the exception s vector number. Take the longword at the address equal to 4*Exception Vector Number, and use it as the address of the exception handler - i.e. jump to the address given by this longword. (In the case of a RESET exception, two longwords are used: the first is loaded into A7 as the initial Stack Pointer value; the second longword is the start address of the reset exception handler.) 162

163 Kinds of Exceptions Internally generated: Elective E.g. TRAPs; TRACE; Error detection exceptions, e.g. Divide by Zero, CHK, Address Error, and others. External generated: E.g. RESET, HALT, Bus Error (BERR) External Interrupts. 163

164 Tutorial 6 Microprocessor Systems 1 (CS3D1) Department of Computer Science Tutorial 6 Simple Exception Handler In this tutorial, we will continue the example started in the last lecture, but let's extend it as follows: it should output a message like this: Trace exception. PC: $XXXXXXXX, SR: %BBBBBBBBBBBBBBBB. It should then allow the excepted program to resume operation. As in the lecture, assume TRAP #14 will output to the computer 'error console' the character whose ASCII code is in D0. Having written the exception handler (use an RTE to return to the excepted program), how does the computer 'know' it is actually an exception handler? What must be done to designate it as the Trace exception handler? Home Learning Outcomes Course Topics Assessment Podcast Tutorials Tutorial 2 Tutorial 3 Tutorial 4 Tutorial 5 Tutorial 6 Practicals Results Recommended Texts Online Resources Mike Brady Contact 164

165 Practical 5 Search TCD go Microprocessor Systems 1 (CS3D1) Department of Computer Science Practical 5 Exception Handlers -- 2% Write a Line 1010 Exception Handler to implement a three-operand unsigned longword multiply instruction. Your task is to devise an exception handler which does longword multiplication on two registers and puts the result in a third register pair. As you know, an instruction whose operation word begins with 1010 is unimplemented in the and will cause a Line 1010 exception. The remaining 12 bits in the operation word can be used for anything. (Historical note: in the old Macintosh Operating System, dating back to 1984, these bits were used to specify a particular call to the Mac OS; almost all calls to the OS were routed thorough the Line 1010 exception handler.) Home Learning Outcomes Course Topics Assessment Podcast Tutorials Practicals 1: Familiarisation 2: Integer-to-ASCII 3: Subroutines 4: Eratosthenes 5: Exception Handlers Results Recommended Texts Online Resources For this practical, the remaining 12 bits are to be used to specify the registers to be used: they are to be arranged as three groups of 4 bits, where each group specifies either an Address Register or a Data Register. The coding of each group should be as follows: If the MSB is clear, the remaining three bits specify a Data Register. If the MSB is set, the remaining three bits specify an Address Register. Thus, for example, the operation word % means 'multiply D7 and A2 and put the result in D0/D1'. Note Even if you don't complete the work, always be sure your attendance is noted. Mike Brady Contact, College Green, Dublin 2, Ireland. Tel:

166 External Interrupts Purpose: to allow outside-world events to be signalled to the processor, to generate exceptions. The resulting exception handlers (a.k.a. interrupt handlers) deal with the interrupt (i.e. service the interrupt). 166

167 External Interrupts Resources (1) Three bits in the SR: I 2I1I0. These represent the priority of the currently-running program. Three lines on the system bus (more of which later): IPL2, IPL1, IPL0. These three lines are used by peripherals to signal interrupt requests. To signal a request, a device impresses the interrupt priority number it has been assigned on the three Interrupt Request lines using the following code: 167

168 Interrupt Priority Request Coding Priority IPL2 IPL1 IPL Note: The Interrupt Request Lines are open collector/open drain active low lines; normally pulled high by [passive] resistors, they are pulled low to activate them 168

169 External Interrupts Resources (2) An Interrupt Acknowledge Cycle. This special bus cycle is used by the processor to get a vector number for the interrupt request. 169

170 External Interrupts Resources (3) Peripheral Devices need some facilities to permit interrupts: They must be able to generate interrupt requests, duh, They must be able to respond to an interrupt acknowledge cycle. If it can fully respond, great; if not, it must be able to signal that it can t fully respond. That s okay but probably slower. 170

171 1 1 1 How do Interrupts Work? IPL2' IPL1'IPL0' BUS P1 P2 P3 K P1, P2 and P3 are three Peripherals, with priorities of 2, 1 and has a process running, with priority K No interrupt request in place: IPL2, IPL2 and IPL0 are all at

172 Suppose P2 makes an interrupt request: IPL2' IPL1'IPL0' BUS P1 P2 P3 K Request of priority 1 placed on the interrupt request lines. 172

173 Recognising Interrupts If priority of request is greater than priority of process running (in the example, if 1 > K), or if the priority of the request is 7, then the request for an interrupt is recognised; otherwise the request is ignored, potentially for ever! 173

174 When an interrupt request is recognised The normal exception handling sequence is entered, with a couple of specialistions: 174

175 Interrupt Exception Handling Initials Steps If exception is not RESET m Make internal copy of the SR. Turn off T bit, turn on S bit. (If exception is RESET, then set I 2I1I0 of SR to 111. External interrupts are handled slightly differently see later.) If exception is not RESET, s Save current PC and internal copy of SR on stack. 175

176 Exception Handling Initials Steps From the source of the exception, and possibly other information, determine the exception s vector number. Take the longword at the address equal to 4*Exception Vector Number, and use it as the address of the exception handler - i.e. jump to the address given by this longword. (In the case of a RESET exception, two longwords are used: the first is loaded into A7 as the initial Stack Pointer value; the second longword is the start address of the reset exception handler.) 176

177 Interrupt Exception Initial Sequence Make internal copy of the SR. Turn off T bit, turn on S bit. Set priority equal to priority of interrupt being acknowledged. Save current PC and internal copy of SR on stack. Use an Interrupt Acknowledge Cycle to get the exception s vector number. Take the longword at the address equal to 4*Exception Vector Number, and use it as the address of the exception handler - i.e. jump to the address given by this longword. 177

178 Setting the priority Make the interrupt handler s priority equal to the interrupt to ensure another interrupt of equal or lower priority can not interrupt the handler. 178

179 Interrupt Acknowledge Cycle Using an Interrupt Acknowledge Cycle to allow the interrupting device to: supply an exception vector number, or to indicate that it is unable to do so -- in this case, an AutoVector is used instead. 179

180 Bus/Interrupt Issues Interrupt Handling on the needs external hardware support to avoid certain problems, e.g. phantom interrupt request priorities. They must be resolved in hardware. It s not our problem to fix such problems generally, rather we should be aware of the possibility of such hardware-related issues. 180

181 The Chip Pinout V CC (2) GND(2) CLK ADDRESS BUS A23 A1 DATA BUS D15 D0 AS PROCESSOR STATUS FC0 FC1 FC2 R/W UDS LDS DTACK ASYNCHRONOUS BUS CONTROL MC6800 PERIPHERAL CONTROL E VMA VPA BR BG BGACK BUS ARBITRATION CONTROL SYSTEM CONTROL BERR RESET HALT IPL0 IPL1 IPL2 INTERRUPT CONTROL 181

182 Tutorial 7 Search TCD go Microprocessor Systems 1 (CS3D1) Department of Computer Science Practical 5 Exception Handlers -- 2% Write a Line 1010 Exception Handler to implement a three-operand unsigned longword multiply instruction. Your task is to devise an exception handler which does longword multiplication on two registers and puts the result in a third register pair. As you know, an instruction whose operation word begins with 1010 is unimplemented in the and will cause a Line 1010 exception. The remaining 12 bits in the operation word can be used for anything. (Historical note: in the old Macintosh Operating System, dating back to 1984, these bits were used to specify a particular call to the Mac OS; almost all calls to the OS were routed thorough the Line 1010 exception handler.) Home Learning Outcomes Course Topics Assessment Podcast Tutorials Practicals 1: Familiarisation 2: Integer-to-ASCII 3: Subroutines 4: Eratosthenes 5: Exception Handlers Results Recommended Texts Online Resources For this practical, the remaining 12 bits are to be used to specify the registers to be used: they are to be arranged as three groups of 4 bits, where each group specifies either an Address Register or a Data Register. The coding of each group should be as follows: If the MSB is clear, the remaining three bits specify a Data Register. If the MSB is set, the remaining three bits specify an Address Register. Thus, for example, the operation word % means 'multiply D7 and A2 and put the result in D0/D1'. Note Even if you don't complete the work, always be sure your attendance is noted. Mike Brady Contact, College Green, Dublin 2, Ireland. Tel:

183 Practical 6 Search TCD go Microprocessor Systems 1 (CS3D1) Department of Computer Science Practical 6 Interrupt Handlers Value: 2% Write an assembly language program and an interrupt exception handler to implement an elapsed time clock i.e. hours, minutes and seconds (more if you like). The target computers have a high-precision clock, which can be programmed to generate interrupt requests at very precise intervals. The clock has two word-sized interface registers, PICR and PITR: PICR EQU $FFFFFA22 PITR EQU $FFFFFA24 These are used to set up the clock as required. The clock is controlled by a crystal whose frequency is Hz. The intervals between interrupts are generated by starting a counter at the value (1 255) written to the PITR+1 and decrementing it to zero. The counter is decemented either every 122µS (prescaling disabled) or 62.5mS (prescaling enabled). Prescaling is enabled/disabled by writing 1/0 to the PITR. E.g. the following would set the clock to interrupt every 125mS: Home Learning Outcomes Course Topics Assessment Podcast Tutorials Practicals 1: Familiarisation 2: Integer-to-ASCII 3: Subroutines 4: Eratosthenes 5: Exception Handlers 6: Interrupts Results Recommended Texts Online Resources move.w #$0102,PITR The interrupt level and vector number to use are specified in the upper and lower bytes of the PICR. The following sets the timer to generate a level 4 interrupt using vector $68: move.w #$0468,PICR The interrupt request is satisfied when the device takes part in an interrupt acknowledge cycle, so you don't need to explicitly 'satisfy' the request. Your main program need to initialise everything and then enter a loop where it displays the time on the LCD display. To send an NUL-terminated ASCII string to the LCD, place its address in A0 and call TRAP #7. Watch out for interrupts: as soon as you enable the machine to generate interrupts, you must assume that is will generate one right away -- make sure your code is ready for it. Hint. Bear in mind that the interrupt handler should be very fast. In particular, it hold not call TRAP #7, as that is (a) unnecessary and (b) likely to be very slow anyway. 183

184 68000 Signal Summary Signal Name Mnemonic Input/Output Active State On HALT On Bus Relinquish Address Bus A0 A23 Output High Yes Yes Data Bus D0 D15 Input/Output High Yes Yes Address Strobe AS Output Low No Yes Hi-Z Read/Write R/W Output Read-High Write-Low No Yes Data Strobe DS Output Low No Yes Upper and Lower Data Strobes UDS, LDS Output Low No Yes Data Transfer Acknowledge DTACK Input Low No No Bus Request BR Input Low No No Bus Grant BG Output Low No No Bus Grant Acknowledge BGACK Input Low No No Interrupt Priority Level IPL0, IPL1, IPL2 Input Low No No Bus Error BERR Input Low No No Mode MODE Input High Reset RESET Input/Output Low No* No* Halt HALT Input/Output Low No* No* Enable E Output High No No Valid Memory Address VMA Output Low No Yes Valid Peripheral Address VPA Input Low No No Function Code Output FC0, FC1, FC2 Output High No Yes Clock CLK Input High No No Power Input VCC Input Ground GND Input *Open drain. 184

185 Function Codes Function Code Output FC2 FC1 FC0 Address Space Type Low Low Low (Undefined, Reserved) Low Low High User Data Low High Low User Program Low High High (Undefined, Reserved) High Low Low (Undefined, Reserved) High Low High Supervisor Data High High Low Supervisor Program High High High CPU Space 185

186 Bus Cycles General Points The Address and Data Buses are concerned with words, not bytes. Address Strobe (AS ) validates the address bus and the function codes Upper Data Strobe (UDS ) validates the upper byte of the data bus D15 to D8. This is the even-addressed byte in the word addressed by the Address Bus. Lower Data Strobe (LDS ) validates the lower byte of the Data Bus D7 to D0. This is the odd-addressed byte in the word addressed by the Address Bus. 186

187 Tutorial 8 Search TCD go Microprocessor Systems 1 (CS3D1) Department of Computer Science Tutorial 8 Simple Threads and a Round Robin Scheduler Develop a system where you had a number of separate processes which we will call "threads*" with a "thread scheduler" for giving each thread some processor time. You need to think about how you should represent threads what you need to know and store about each thread so that you can suspend its execution and restart it later. You need to know think about how a scheduler could be implemented, and what policies it should adopt when deciding what thread to give processor time to. So, in this tutorial, you are designing the 'architecture' of something that would typically (but not necessarily) be part of an operating system. *In recent operating systems, there are typically "processes" and "threads." Processes have their own protected memory space, which is good, but it means that inter-process communication, by way of shared memory locations, is expensive, and that's bad. Threads are sometimes called "lightweight processes," because they are assumed to exist within a shared memory space, which makes inter-thread communication easy and cheap, which is good, but threads can damage each other's context, or interfere in other ways, which is bad. Very frequently, a process can be a host to a bunch of threads. Home Learning Outcomes Course Topics Assessment Podcast Tutorials Tutorial 2 Tutorial 3 Tutorial 4 Tutorial 5 Tutorial 6 Tutorial 7 Tutorial 8 Practicals Results Recommended Texts Online Resources Mike Brady Contact, College Green, Dublin 2, Ireland. Tel:

188 Practical 6 Revisited Search TCD go Microprocessor Systems 1 (CS3D1) Department of Computer Science Practical 6 Interrupt Handlers Value: 2% Write an assembly language program and an interrupt exception handler to implement an elapsed time clock i.e. hours, minutes and seconds (more if you like). The target computers have a high-precision clock, which can be programmed to generate interrupt requests at very precise intervals. The clock has two word-sized interface registers, PICR and PITR: PICR EQU $FFFFFA22 PITR EQU $FFFFFA24 These are used to set up the clock as required. The clock is controlled by a crystal whose frequency is Hz. The intervals between interrupts are generated by starting a counter at the value (1 255) written to the PITR+1 and decrementing it to zero. The counter is decemented either every 122µS (prescaling disabled) or 62.5mS (prescaling enabled). Prescaling is enabled/disabled by writing 1/0 to the PITR. E.g. the following would set the clock to interrupt every 125mS: Home Learning Outcomes Course Topics Assessment Podcast Tutorials Practicals 1: Familiarisation 2: Integer-to-ASCII 3: Subroutines 4: Eratosthenes 5: Exception Handlers 6: Interrupts Results Recommended Texts Online Resources move.w #$0102,PITR The interrupt level and vector number to use are specified in the upper and lower bytes of the PICR. The following sets the timer to generate a level 4 interrupt using vector $68: move.w #$0468,PICR The interrupt request is satisfied when the device takes part in an interrupt acknowledge cycle, so you don't need to explicitly 'satisfy' the request. Your main program need to initialise everything and then enter a loop where it displays the time on the LCD display. To send an NUL-terminated ASCII string to the LCD, place its address in A0 and call TRAP #7. Watch out for interrupts: as soon as you enable the machine to generate interrupts, you must assume that is will generate one right away -- make sure your code is ready for it. Hint. Bear in mind that the interrupt handler should be very fast. In particular, it hold not call TRAP #7, as that is (a) unnecessary and (b) likely to be very slow anyway. 188

189 Practical 7 Search TCD go Microprocessor Systems 1 (CS3D1) Department of Computer Science Practical 7 Threads Scheduler Value: 2% Design and implement a threads scheduler for, say, eight threads of execution. The scheduler should simply divide out the time equally to each thread. The emphasis in the project is on the scheduler and all the associated data structures. So, to keep things simple, let each thread have an index number j, and let it light up the j-th LED. If each thread is working properly, each of the eight LEDs should be repeatedly lit for very short intervals, and the intervals should merge so that all eight LEDs appear to be evenly lit. Experiment with different time-slices to see the effects on the display. Speculative question: suppose you had to minimise the power consumption of the system by minimising the number of instructions executed. What simple improvements could you suggest to the scheduler and/or the threads? Home Learning Outcomes Course Topics Assessment Podcast Tutorials Practicals 1: Familiarisation 2: Integer-to-ASCII 3: Subroutines 4: Eratosthenes 5: Exception Handlers 6: Interrupts 7: Threads Scheduler Results Recommended Texts Online Resources Show your work to the demonstrator, who will award you a mark out of 10. The value of this practical is 2% of your year-end mark. (Even if you don't complete the work, always be sure your attendance is noted.) Mike Brady Contact, College Green, Dublin 2, Ireland. Tel: