L10: Major/Minor FSMs, Lab 3, and RAM/ROM Instantiation

Transcription

1 L10: Major/Minor FSMs, Lab 3, and RAM/ROM Instantiation Acknowledgements: Rex Min 1

2 Toward FSM Modularity Consider the following abstract FSM: S 0 S 1 S S 3 S 4 S 5 S 6 S 7 S S 9 a 1 d 1 a d a 3 d 3 b 1 c 1 b c b 3 c 3 Suppose that each set of states a x...d x is a sub-fsm that produces exactly the same outputs. Can we simplify the FSM by removing equivalent states? No! The outputs may be the same, but the next-state transitions are not. This situation closely resembles a procedure call or function call in software...how can we apply this concept to FSMs?

3 The Major/Minor FSM Abstraction A A Minor FSM A RESET CLK Major FSM B B Minor FSM B RESET CLK Subtasks are encapsulated in minor FSMs with common reset and clock Simple communication abstraction: : tells the minor FSM to begin operation (the call) : tells the major FSM whether the minor is done (the return) The major/minor abstraction is great for... Modular designs (always a good thing) Tasks that occur often but in different contexts Tasks that require a variable/unknown period of time Event-driven systems 3

4 Inside the Major FSM... S 1 S S 3 S 4 1. Wait until the minor FSM is ready. Trigger the minor FSM (and make sure it s started) 3. Wait until the minor FSM is done Major FSM State S 1 S S S 3 S 3 S 3 S 4 CLK 4

5 Inside the Minor FSM 1. Wait for a trigger from the major FSM T 1 T T 3 T 4 3. Signal to the major FSM that work is done. Do some useful work Major FSM State CLK Minor FSM State S 1 S S S 3 S 3 S 3 S 4 T 1 T 1 T T 3 T 4 T 1 T 1 can we speed this up? 5

6 Optimizing the Minor FSM Good idea: de-assert one cycle early T 1 T T 3 T 4 Bad idea #1: T 4 may not immediately return to T 1 Bad idea #: never asserts! T 1 T T 3 T 4 T 1 T 6

7 A Four-FSM FSM Example TICK Major FSM A A B B C C Minor FSM A Minor FSM B Minor FSM C Operating Scenario: Major FSM is triggered by TICK Minors A and B are started simultaneously Minor C is started once both A and B complete TICKs arriving before the completion of C are ignored TICK IDLE Assume that A and B both rise before either minor FSM completes. Otherwise, we loop forever! TICK A + B ST AB A B A B A + B WT AB A B C WT C C ST C C C C 7

8 Four-FSM FSM Sample Waveform TICK A A Minor FSM A Major FSM B B Minor FSM B C C Minor FSM C state tick IDLE IDLE ST AB ST AB WT AB WT AB WT AB ST C ST C WT C WT C WT C IDLE IDLE ST AB A A B B C C

9 Lab3 Block Diagram A/D AD 670 RESET status control(ce, CS, R/W) Synchronizer MAJOR FSM MINOR FSM 1 CONTROL UNIT MINOR FSM... Must choose a shared bus for the A/D and DA A/D output in twos complement and ROM in sign/magnitude D/A AD 55 control (CE, CS) CLK Bidirectional I/O Q D/A Reg LD D LD A/D Reg D Q LE_DAC LE_DAC LE_ADC SRAM Bypass RAM Control and Address ALU ROM CONTROL Control and Address SW Impulse Response ROM Use on-chip SRAM and ROM Sample rate is fixed at 0kHz Must use a memory based approach to FIR, not tapped delay line (i.e., registers) Switches SW Arithmetic Unit (MAC) Must use Major/Minor FSM structure 9

10 Control Flow for Lab3 Wait for a fixed time interval. Reset Initialize Output what was computed on the last sample. Store the previous A/D sample into memory. Start the next A/D conversion. Sample Wait Output Computed Sample to DAC Store A/D Sample Sample Do the FIR filter algorithm which is a convolution. Go back for more... Initiate A/D Convolve 10

11 Use LPM to Create ROM/RAM Click on File MegaWizard Plug-In Manager This starts up a series of windows so that you can specify parameters of the LPM module. You can choose ROM RAM dp - Dual Ported dq - Separate Inputs and Outputs io - TriState Inputs and Outputs (like the 664) You choose the number of address bits and the word size. You should specify a file to set the values of the ROM. You can choose registered or unregistered inputs, outputs, and addresses. 11

12 ROM Contents Prepare a.dat file. You can type this in, write a computer program, get it from another application (speech or graphics, etc.) This has numbers separated by white space. The default base is HEX but you can use binary or decimal if you include the following statement (before the numbers). # BASE = BINARY; Insert, # SET_ADDRESS = 0; (specifies that data should start at address 0) Run datntl on Athena to format your.dat file into Intel HEX for details, after setup type man datntl datntl <filename>.dat <filename>.ntl romx.dat: # SET_ADDRESS = 0; datntl tool on athena address romx.ntl: : DC : FF 1 3 ROM See for.mif format (memory initialization format) data

13 romx.v (generated automatically) //============================================= // File Name: romx.v // Megafunction Name(s): // lpm_rom //============================================= module romx ( address, q); input [:0] address; output [7:0] q; Example: deep by bits wide 3 wire [7:0] sub_wire0; wire [7:0] q = sub_wire0[7:0]; endmodule lpm_rom lpm_rom_component ( defparam.address (address),.q (sub_wire0)); lpm_rom_component.lpm_width =, lpm_rom_component.lpm_widthad = 3, lpm_rom_component.lpm_address_control = "UNREGISTERED", lpm_rom_component.lpm_outdata = "UNREGISTERED", lpm_rom_component.lpm_file = romx.ntl"; Path to location of Rom data ROM delay 13

14 ram4x.v // megafunction wizard: %LPM_RAM_DQ% module ram4x ( address, we, data, q); input [1:0] address; input we; input [1:0] data; output [1:0] q; address data we RAM q wire [1:0] sub_wire0; wire [1:0] q = sub_wire0[1:0]; lpm_ram_dqlpm_ram_dq_component (.address (address),.data (data),.we (we),.q (sub_wire0)); defparam lpm_ram_dq_component.lpm_width =, lpm_ram_dq_component.lpm_widthad =, lpm_ram_dq_component.lpm_indata = "UNREGISTERED", lpm_ram_dq_component.lpm_address_control = "UNREGISTERED", lpm_ram_dq_component.lpm_outdata = "UNREGISTERED", lpm_ram_dq_component.lpm_hint = "USE_EAB=ON"; endmodule 14

15 Asynchronous RAM Simulation module ram4x ( address, we, data, q); input [1:0] address; input we; input [1:0] data; output [1:0] q; address data we RAM q endmodule Latch interface: Data must be setup and held around the falling edge of the clock. Address must be setup before rising edge and held after falling edge 15

16 SRAM with Registered Address and Data (Synchronous) Register interface: Address, data and we should be setup and held on the rising edge of clock If we=1 on the rising edge, a write operation takes place If we=0 on the rising edge, a read operation takes place 16