We will begin our study of computer architecture From this perspective. Machine Language Control Unit

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1 An Instruction Set View Introduction Have examined computer from several different views Observed programmer s view Focuses on instructions computer executes Collection of specific set of instructions for particular computer Called instruction set Includes instructions that Bring data in from outside world Output signals to external world Provide means to exchange data With memory subsystem Perform arithmetic operations Also known as assembly language for machine For new processor design Instructions selected and designed first These lead to or dictate architecture Such an architecture called Instruction Set Architecture - ISA We will begin our study of computer architecture From this perspective Generally when we write program Done in high level language C, C++ Rather than assembly language For the machine on which we re working High-Level Language Compiler Assembly Language Assembler Machine Language Control Unit Control Signals to the Hardware As we see in graphic when program compiled Compiler translates high-level language constructs Into assembly language instructions Assembly language instructions Translated into machine code By assembler Machine code reflects binary encoding Machine s instructions - 1 of 27 -

2 Machine code directly or indirectly Drives signals from control unit To affect execution of assembly language instruction On occasion we will write combination high-level and assembler Done when portions of programs Optimized for Speed Size When working with assembly language We work directly with computer s Various registers Consequently Must have knowledge of machine s hardware architecture Let s briefly review these ideas Control unit in computer repeatedly executes following steps Fetch instruction Retrieve instruction from memory Decode instruction Examine instruction Understand its meaning Execute instruction Perform necessary step(s) to affect intended operation Steps involve controlling underlying hardware According to sequence necessary to yield result Write back Write results of execute step back into memory Next Determine address in memory from which to retrieve Next instruction CPU contains number of registers Used as temporary storage for variables or other information Needed by programmer or system Called register set Special register in control unit Holds address of next instruction to be interpreted and executed Register called program counter PC - 2 of 27 -

3 Anatomy of a Machine Instruction Let s now look at basic structure of assembly instruction High Level Structure At highest level machine s instructions Contain following information Operation information Identifies the instruction to be performed Operation specified by binary code Referred to as operation code Shortened to op-code Operand information Operands are pieces of data the Processor is operating on Typical machines support instructions Involve One, two, or three operands Known as One, two, or three operand (or address) instructions Each such operand has an address Consequently also known as One, two, or three address instructions Operation distinguishes two kinds of operands Source operands Express inputs into operation Destination or result operands Express outputs from operation Instructions may direct machine To perform following types of operations on operands Store Transfer Compute Operands may be found in any of several different places Main or virtual memory Cache memory Register As a brief aside Fetching instruction from identified locations Requires different amounts of time - 3 of 27 -

4 Registers fastest Virtual memory slowest On some occasions Instruction fetch may require several memory accesses Generic Instruction Format Various machine architectures may have multiple formats For expressing required operations or instructions Accompanying figure captures Several generic basic formats Observe that we have one instruction With no apparent operand Such instructions support actions such as NOP no operation HALT stop executing START start executing May also have an implied operand Accumulator Top of stack Referred to as zero operand or address instructions OP-CODE OP-CODE Operand 1 OP-CODE Operand 1 Operand 2 OP-CODE Operand 1 Operand 2 Operand 3 Remaining instructions interpret operands as Sources of operand Destination of result ARM Instruction Format ARM architecture Supports five basic instruction formats Register R Immediate I Branch B Branch Conditional BC Data Transfer DT Two floating point Floating Register FR Floating Immediate FI These are expressed graphically in following figure Instructions are 32 bit words Fields vary based upon instruction range from 5 bits to 26 bits Shamt 6 bits Op-Code 6 to 11 bits Immediate 12 to 16 bits Address 21 to 26 bits - 4 of 27 -

5 OP-CODE OP-Code Bits [31:21] = 0A0-0BF address B - Branch OP-CODE OP-Code Bits [31:21] = 2A0-2A7, 5A0-5AF address CB Conditional Branch Rd OP-CODE Rm shamt Rn Rd OP-Code Bits [31:21] = , 4D6-558, , 69A-758 R - Register OP-CODE ALU Immediate Rn Rd OP-Code Bits [31:21] = , 4D6-558, , 69A-758 I - Immediate OP-CODE Data Transfer Address 00 Rn Rd OP-Code Bits [31:21] = 1C0-1C2, 7C0-7C2 D Data Transfer OP-CODE MOV_Immediate Rd OP-Code Bits [31:21] = , IW Mov Wide Immediate OP-CODE operation Rm First register source operand Rn Second register source operand Rd Register destination operand Shamt Shift amount Examine each in bit greater detail B-Type OP-CODE OP-Code Bits [31:21] = 0A0-0BF address B - Branch 0x05: B Top 4 bits of address come from current PC contents Link save following address to support return following jump Typical instruction of form B 30 // go to 120, PC 30 * 4 // addresses are word addresses words are 4 bytes long // jump of 30 words == 120 bytes - 5 of 27 -

6 I-Type OP-CODE ALU Immediate Rn Rd OP-Code Bits [31:21] = , 4D6-558, , 69A-758 0x244: ADDI 0x248: ANDI 0x164: ADDIS 0x168: ORRI 0x344: SUBI 0x348: EORI 0x2C4: SUBIS 0x2C8: ANDIS I - Immediate Used for operations with immediate constant operand D-Type ADDI X1, X2, 64 // X1 X OP-CODE Data Transfer Address 00 Rn Rd OP-Code Bits [31:21] = 1C0-1C2, 7C0-7C2 D Data Transfer 0x1C0: STURB 0x1C2: LDURB 0x7C0: STUR 0x7C2: LDUR Used to perform load or store types of operations R-Type LDUR X1, #12(X2) // X1 memory[x2 + #12] SDUR #12(X2), X1 // memory[x2 + #12] X OP-CODE Rm shamt Rn Rd OP-Code Bits [31:21] = , 4D6-558, , 69A-758 0x450: AND 0x458: ADD 0x4D6: SDIV, shamt=02 0x4D8: MUL, shamt=1f 0x550: ORR 0x558: ADDS 0x650: EOR 0x658: SUB 0x69A: LSR 0x69B: LSL 0x6B0: BR, rest all 0 s but Rd 0x750: ANDS 0x758: SUBS R - Register Used for 3 register ALU operations Typical 3 register instructions given as ADD X1, X2, X3 // X1 X2 + X3 LSL X1, X2, #16 // X1 = X2 << #16 bits - 6 of 27 -

7 Pseudo Instructions Complementing instruction set Implemented in hardware by machine Language supports what are called pseudoinstructions Treated by compiler as if instructions in own right Intended to simplify Assembly language programming Translation assembly code into machine code Not implemented in hardware Pseudo instruction instructions in Arm8 MOV X1, X2 // Move.. X1 X2 R[rd] R[rn] CMP X1, X2 // Flags = R[rn] - R[rm] CMPI X1, #12 // Flags = R[rn] ALUImm LDA X1, X2 // R[rd] R[rn]+ DTAdx Instructions in the Real World Have taken first step into instruction sets Looked at generic instruction format Supporting 1, 2, or 3 operands ARM format Structure of five types of instructions Express specific implementation of generic format Supports 1, 2, or 3 operands Now step back briefly Look first at higher-level language instruction Might be expressed as compositions of Instruction set instructions Following table gives simple examples of different types of C type One, two, or three address instructions Code Fragment Operand 1 (Source 1) Operand 2 (Source 2) Result (Destination) Type int a = 10; int b = 20; a b c 3 address int c; c = a + b; int a = 10; int b = 20; a b a 2 address b = a + b; a = ~a a 1 address - 7 of 27 -

8 As noted earlier Operand field identifies location of operand To support full address of operand Operand fields of instruction must necessarily be very large For 32 bit machine Support for 3 addresses for three operands would necessitate 96 bits for address op-code bits While certainly feasible Alternate schemes possible Driven by need for speed Flexibility Interpretation of address at compile time vs. runtime Alternate interpretation for bits in operand fields Provides for speed and flexibility Several such interpretations Let operand be part of instruction Let CPU registers temporarily hold Operands Address of operand Let operand field identify the register Holding actual operand In both cases Operand available very quickly At the end of the day Must be able to compile user programs Typically written in high level language To be able to support different formats Need to be able to convey information to compiler When formulating instruction set Need to consider things that one needs to do Talk to user Utilizing C as representative example of higher level programming language Need to support such basic operations as Algebraic addition of a constant x = x + 3 Mathematical operations on variables and pointers to variables x = x + y z = x + y z = x + *y - 8 of 27 -

9 Operations on array type containers x[3] = y y = x[3] Branching and Looping operations if (x == 3) repeat body until(x ==3) Procedure and function calls f(x) How do we begin to support such operations With basic instructions identified Move back into world of instruction sets Examine what will be necessary Instruction Format and Addressing Modes If assume operands or addresses of operands Held in registers Can define following formats Collection represents operations Commonly found or supported In most instruction sets Once again specific format will vary with instruction set Generic format presented intended to express concept Immediate Algebraic addition of a constant Operand is part of instruction LOADI R1, #FACEh; // put hex constant FACE into register R1 Direct Mathematical operations on variables Operand contains address of operand ADD R1, *opr; // add contents of R1 to contents of what opr is // pointing at and put result into R1 Indirect Mathematical operations on pointers to variables Operand contains address of address of operand ADD R1, **opr; // add contents of R1 to contents of what opr is // pointing at is pointing at and put result into R1-9 of 27 -

10 Register direct Mathematical operations on variables Named registers contain operand ADD R1, R2; // add contents of R1 to contents of R2 and put result // into R! Register indirect Mathematical operations on pointers to variables Named register contains address of operand ADD R1, *R2; // add contents of R1 to contents of what R2 is // pointing at and put result into R1 Indexed Operations on array type containers Address computed as sum of Base address Contents of indexing register ADD R1, 1800(R2); // add contents of R1 to contents of memory location // contents of R2 and put result into R! PC relative Branching and Looping operations Signed offset added to program counter Becomes address of next instruction BR -10; // add 10 to contents of PC go to that location Procedure call Procedure and function calls Call: Address of procedure or function body Goes into program counter call f; // address of body of f into PC go to that location Return: Address of return location Goes into program counter return; // address of return location into PC go to that location - 10 of 27 -

11 Different computer architecture designs Support different forms of addressing in different ways Techniques such as those illustrated Called addressing modes Because once again application program must be compiled Addressing information Must be conveyed from compiler to assembler Enables assembler to translate High-level language instruction Into machine s instructions Machine s instructions Must ultimately contain sufficient information To invoke control signals to execute instruction Many ways to support conveyance of such information One approach Modified instruction format to qualify each operand field With address mode information Incorporating address mode field Above have identified 8 different addressing modes Immediate Direct Indirect Register Register indirect Index PC relative Procedure Can encode different modes with 4 bits Use 1 bit to distinguish between Direct and indirect Use 3 bits to distinguish major modes Can incorporate information into instruction Add address mode field to each operand field Modified format given in following diagram ARM architecture Supports such variations through Different instruction formats and op-codes - 11 of 27 -

12 OP-CODE Adx OP-CODE Mode Operand 1 Adx Adx OP-CODE Mode Operand 1 Operand 2 Mode Adx Adx OP-CODE Mode Operand 1 Operand 2 Mode Adx Mode Operand 3 Types of Operations Number of different operations varies with machine Correspondingly so does number of op-codes Often have different op-codes for related operations Addition If machine supports 2 and 3 operand add May have ADD2 and ADD3 op-codes MIPS supports 4 variants on the ADD operation ADD ADD unsigned ADD immediate ADD immediate unsigned 2 and 3 operand adds Supported by operands that appear in source and destination fields ARM supports 4 basic variants on the ADD operation ADD ADDS set flags ADDI immediate ADDIS immediate and set flags 2 and 3 operand adds Supported by operands that appear in source and destination fields In general find same classes of operations on most machines Arithmetic Logical / Bit Manipulation / Shift Data movement Input / Output Flow of control System control Conversion - 12 of 27 -

13 Expanding Op-Codes In discussion above We ve assumed op-code field fixed No reason for this to be the case Consider high-level strategy Similar to encoding data for transmission Make most frequently sent the simplest Hoffman encoding At outset of design Designers examine necessary capabilities for system Entails identifying What kinds of instructions to support How many of each kind Recall our earlier discussion How many of each operand type May need only few 1 address instructions Many 2 address versions Somewhat fewer 3 address implementations Forcing all op-code fields to be same width Wasteful Consider logically subdividing op-code field into subfields Devote portion to encoding intended operation Let remainder distinguish amongst types Now consider how we might interpret such a field One possibility Assume we need a large number of 2 address instructions Let MSB distinguish between Two address (operand) instruction Not two address instruction Second MSB or two MSBs Distinguish amongst remaining types Now we can specify If two address instruction Most significant m bits express op-code If not two address instruction Most significant k bits express op-code As designers We have perfect knowledge What bits represent How to interpret them - 13 of 27 -

14 Machine Instructions in Action Will now examine portions of instruction sets from two architectures Intel and ARM To learn how instruction set requirements Reflected in structure and content Of assembly language statements Will first look at Instructions to move data Between registers Between registers and memory Then Instructions to manage flow of control within program Data Movement Before looking at movement through program our code Briefly look at how to handle data Movement of data within program High Level View Have 4 basic ways want to move data within program Between Registers Data copied From source register To destination register Making no assumption as to data type Could be interpreted as operand Could be interpreted as operand address To memory Data copied from From source register To destination location in memory Source will be register name Destination will be address in memory Address will be held in register Such an address called pointer From Memory Data copied from From source location in memory To destination register Source will be address in memory Destination will be register name Address will be held in register - 14 of 27 -

15 From memory to memory Data copied from From source location in memory To destination location in memory Source and destination will be address in memory Addresses will be held in registers Data Movement to and from Memory Let s look first at data movements in high level language like C Each variable that is defined has a storage place Somewhere in memory or register Further it has value in that location Independent of whether variable is Initialized or assigned to That place has an address To simplify current discussion Assume 16 bit words Both data and address A00 5A01 CD00 CD01 mydata0 mydata1 mydata2 mydata3 As each of program s variables stored System memory will begin to look like accompanying figure When one works with data one can Read their values Modify their values Ask where they are stored We have learned that variables hold different types of values integers, floats, chars, etc. In C the type of variable can be memory address as well An address is just another variable with a value Consider the standard C expression unsigned int mydata0 = 0x3; In response to such a declaration compiler Allocates appropriate number of bits of memory To hold the variable mydata0 This is both a declaration and a definition Variable introduced into namespace Memory allocated to hold variable - 15 of 27 -

16 Places value 3 (0x3) into those bits Associates an address such as 0x3000 In memory where the data is stored For the variable mydata0. Subsequently when we write mydata0 Actually referring to the data at location 0x3000 Which is all compiler cares about Name irrelevant If we wish to know where data is stored.at which address in memory Simply ask use the address of operator & Compiler responds with the appropriate information If we write &mydata0; // read address of mydata0) Compiler returns 0x3000 As the place where data is stored If we write int *mydata0ptr = &mydata0; The following occurs Compiler Allocates appropriate number of bits of memory To hold the (pointer type) variable mydata0ptr Finds the address of mydata0 (which is 0x3000) Places that value into the 16 bits at that address We use the symbol * to tell the compiler Variable is a pointer type We use a distinguishing name such as mydata0ptr To identify that this variable is a pointer This is good coding style A00 5A01 0x3 mydata1 mydata2 mydata0 When we are dealing with pointers and pointer declarations Knowing how to read them Helps to make their role a little more clear CD00 CD01 0x3000 mydata3 mydata0ptr Starting with the declaration and assignment int *mydata0ptr = &mydata0; - 16 of 27 -

17 Code fragment on the left of the assignment operator Read in several steps from right to left: 1. mydata0ptr the first part 2. is a pointer * the second part 3. to an integer int the third part 4. mydata0ptr is a pointer to an integer If we assume compiler put pointer variable At memory address 0xCD00 Now have picture in memory Can retrieve the value that mydata0ptr refers to Using the dereference operator, * Preceding the pointer variable If we write int mydata1 = *mydata0ptr ; Value 0x3 assigned to mydata1 using the following steps: 1. Get value contained in pointer variable mydata0ptr, 0x Go to address (0x3000) referred to by that value 3. Get value of variable, mydata0, at memory address 0x A00 5A01 3 0x3 4 0x3 mydata2 mydata0 mydata1 This will be the value 0x3 4. Assign that value (0x3) to variable mydata1. 2 CD00 mydata1 = *mydata0ptr CD01 0x3000 mydata3 1 mydata0ptr Similarly if we write mydata3 = 0x4; *mydataptr = mydata3; Value 0x4 is assigned to the memory location Referred to by the pointer variable mydataptr Using the following steps: 1. Assign value 0x4 to variable mydata3. 2. Get value contained in variable mydata3 0x4. 3. Get value of pointer variable mydataptr, 0x Go to address (0x3000) specified by that value. 5. Assign value contained in variable mydata3 to variable at memory address 0x3000 mydata1 This will be value 0x4-17 of 27 -

18 Implementation Let s now look at the assembly language level For each data movement construct To see how machine informed of Desired data movement operations We ll illustrate with Assembly from Intel microprocessor ARM assembly Your assembly may vary mydata3 = 0x4; *mydata0ptr = mydata3; A00 5A01 CD00 CD01 5 0x4 0x3 mydata2 0x3000 0x4 3 mydata0 mydata1 mydata0ptr mydata3 Data Movement Between Registers C Code a = 10; b = 20; b = a; Intel ARM mov bx, 10 mov dx, 20 mov bx. dx MOV X1, #10 MOV X2, #20 MOV X2. X1 // load 10 into a temp register, bx // load 20 into a temp register, dx // b a // load 10 into a temp register, X1 // load 20 into a temp register, X2 // b a // MOV is pseudoinstruction To Memory C Code int myvar = 5; int* myptr; myptr = &myvar; *myptr = 10; // declare myvar as int // declare myptr as pointer to int // assume myvar declared as int // write to variable myvar Intel // myvar stored by compiler in data segment of memory // bp-2 identifies location // word ptr is assembler operator that turns value into location // into pointer to word mov word ptr [bp-2],5 // myvar 5 myvar is in memory lea ax,word ptr [bp-2] // get address of myvar mov si,ax // move address into index register mov word ptr [si],10 // put the value 10 into myvar - 18 of 27 -

19 ARM // value of myvar written to location in memory // let myvar be placed into register X9 // assume X5 contains memory adx where myvar is to be written MOV X9, #10 // load value 10 into X9 STUR X2, [X5, #0] // Memory[X5 + #0] 10 From Memory C Code int myvar0 = 5; int myvar1 = 7; int* myptr; myptr = &myvar1; myvar0 = *myptr; // declare myvar0 as int // declare myvar1 as int // declare myptr as pointer to int // point to myvar1 // write from memory to variable myvar0 Intel // puts word into memory in local context mov word ptr [bp-2],5 // myvar0 5 myvar0 is in memory mov word ptr [bp-4],7 // myvar1 7 myvar1 is in memory lea ax,word ptr [bp-4] // get address of myvar1 mov si,ax // move address into index register mov ax,word ptr [si] // get value of myvar1 mov word ptr [bp-2],ax // put the value of myvar1 into myvar0 // myvar0 7 ARM // value of myvar1 read from location in memory // let address of myvar1 be placed into register X9 // assume X5 is register containing myvar0 LDUR X5, [X9, #0] // X5 = Memory[X9 + #0] From memory to memory C Code int myvar0 = 5; // declare myvar0 as int int myvar1 = 7; // declare myvar1 as int int* myptr0; // declare myptr0 as pointer to int int* myptr1; // declare myptr1 as pointer to int myptr0= &myvar0; // point to myvar0 myptr1= &myvar1; // point to myvar1 *myptr1 = *myptr0; // copy from myvar0 to myvar1 Intel // puts word into memory in local context mov word ptr [bp-2],5 // myvar0 5 myvar0 is in memory mov word ptr [bp-4],7 // myvar1 7 myvar1 is in memory lea ax,word ptr [bp-2] // get address of myvar0 mov si,ax // move address into index register lea ax,word ptr [bp-4] // get address of myvar0 mov di,ax // move address into index register mov ax,word ptr [si] // put the value of myvar0 into register mov word ptr [di],ax // put register contents into myvar1 // myvar of 27 -

20 ARM // value of myvar1 read from memory location and written to memory location // let address of myvar1 be placed into register X9 // let value of myvar1 be 10 // value of myvar1 be written to memory location containing myvar0 // let address of myvar0 be placed into register X2 LDUR X6, [X9, #0] // X6 Memory[X9 + #0] STUR X6, [X2, #0] // Memory[X2 + #0] X6 Flow of Control We can now how we can use various addressing schemes To alter the flow of control through program Let s look at alternatives at high level first High Level View We have 4 basic ways we can proceed through program Sequential Each instruction executed in sequence Branch Select one of several branches based upon condition Graphically Type of construct seen in if else switch or case Loop Repeatedly execute set of instructions Forever Until some condition met Can make decision Before Code may not be executed After loop Code executed at least once Type of construct seen in do or repeat while for Decision Point Decision Point Code Decision Point - 20 of 27 -

21 Procedure or Function Call Leave current context Execute set of instructions Return to context Type of construct seen for Procedure or subroutine call Interrupt handler Co-routine Code i Procedure Call Code i+1 Procedure Implementation Let s now look at the assembly language level For each flow of control construct We ll illustrate with Assembly from Intel microprocessor ARM assembly Your assembly may vary Sequential C Code a = 10; b = 20; c = a + b; Intel mov word ptr [bp-2],10 // load a into memory mov word ptr [bp-4],20 // load b into memory mov ax,word ptr [bp-2] // load a into a temp register add ax,word ptr [bp-4] // temp a + b mov word ptr [bp-6],ax // load c into memory ARM MOV X1, #10 // X1 a load 10 into a temp register, X1 MOV X2, #20 // X2 b into a temp register, X2 ADD X3, X1, X2 // c a + b Conditional Branch C Code if - else construct int a = 10; int b = 15; int c; int d = 20; int e = 25; if (a == b) c = d + e; else c = d - e; - 21 of 27 -

22 Intel mov word ptr [bp-2],10 // load a into memory mov word ptr [bp-4],15 // load b into memory mov dx,20 // load d into a temp register mov bx,25 // load e into a temp register mov ax,word ptr [bp-2] // load a into a temp register cmp ax,word ptr [bp-4] // compare a and b jne // if they are not equal branch to // mov ax,dx // copy d into a temp register add ax,bx // add d to e d d + e jmp // d is not lost go mov ax,dx // copy d into a temp register sub ax,bx // sub d from e d d - mov word ptr [bp-6],ax // load c into memory ARM Assume a.. e in registers X0..X4 CMP X0, X1 B.NE LABEL0 ADD X2, X3, X4 B LABEL1 LABEL0: SUB X2, X3, X4 LABEL1: // test if a == b set flags // if a!= b branch to LABEL0 // X2 X3 + X4 c = d + e // jump over next code // X2 X3 - X4 c = d - e Loop C Code int i = 2; int a = 0; while (a < 10) { i = i + 2; a++; } Intel mov bx,2 // set i to 2 in register xor dx,dx // set a to 0 jmp // go to start of lea ax,word ptr [bx+2] // temp reg i + 2 mov bx,ax // i temp reg inc dx // increment cmp dx,10 // compare a with 10 jl // if less than 10 // jump to of 27 -

23 ARM Assume a is in X0 i is in X2 MOV X0, #0 MOV X2, #2 // loop exit value to X0 // i to X2 LABEL0: ADDI X2, X2, #2 // X2 X2 + 2 i = i +2 ADDI X0, X0, #1 // X0 X0 + 1 a++ CMP X0, #10 // check exit value B.LT LABEL0 // if a < 10 // return to top of loop // else // exit Procedure Call Most complex of flow of control constructs Not more difficult More involved Will include Procedures Subroutines Co-routines Process We ll consider from high level Program loaded at address 3000 Code executed until address 3053 Procedure encountered 1. Save return address Several important things to note Address saved is 3057 Stack gets Return address Parameters 2. Address of procedure 5000 put into PC 3. Instruction at 5000 begins executing 4. Execution continues until Return encountered Action similar to call Stack gets Return values Stack looses Return address 6. Return Address put into PC 7. Execution continues at Code 3053 Procedure Call F More Code 5000 F1 Procedure Code 5053 Return - 23 of 27 -

24 Had procedure call been encountered in procedure F1 Identical process repeated Can be repeated multiple times Must be aware that stack can overflow If too much pushed on Begin to loose information Particularly return address Representative code fragment given first in C As might exist in main() Then assembler For one possible implementation of function call. Procedure Call C Code int myvar0 = 30; int myvar1 = 40; myvar1 = myfunc(myvar0); // define and initialize working variables // call procedure The C code in the function body appears as shown int myfunc(int avar) { int localvar = 15; localvar = localvar + avar; return localvar; } Intel mov word ptr [bp-2],30 // load myvar0 into memory init to 30 mov word ptr [bp-4],40 // load myvar1 into memory init to 40 push word ptr [bp-2] // push myvar0 onto stack // to pass to function call near // call the function pop cx // pop myvar0 off the stack mov word ptr [bp-4],ax // avar1 returned value Procedure proc near push bp // save context mov bp,sp // bp stack pointer mov dx,15 // localvar into dx register mov ax,dx // copy localvar into ax register add ax,word ptr [bp+4] // ax localvar + avar0 mov dx,ax // copy result into dx register // localvar = localvar + avar pop bp endp // retrieve old context // return - 24 of 27 -

25 ARM Passing by Register Procedure call MOV X1, #30 MOV X2, #40 // myvar0 // myvar1 BL myfunc // call the function // copy return adx into LR register // BL instruction writes the address of // sequentially following instruction for the return // to general-purpose register, LR (X30) MOV X2, X0 // get the return value myvar1 45 myfunct: MOV X3, #15 // localvar 15 ADD X0, X1, X3 // compute sum X0 X1 + X3 X BR LR // return to calling context Stack Stack data structure Occupies an area in memory Has finite size and several operations Push Puts something onto top of stack Top of stack is special value Saved for ongoing operations Push operation Writes something to memory Increments address of top of stack Ready for next push Stack can be implemented to increase from Lower memory addresses to higher memory addresses or Higher memory addresses to lower memory addresses ARM does the latter Pop Takes something off the top of stack Pop operation Removes something from top of stack by Decrementing top of stack Returning previous top of stack Peek Looks at something on the top of stack Peek operation Returns something from top of stack by Does not decrement top of stack - 25 of 27 -

26 ARM Passing via the Stack Procedure call MOV X1, #30 MOV X2, #40 SUBI SP, SP, #8 STUR X1, [SP, #0] // myvar0 // myvar1 // make room on stack for myvar0 // SP SP 8 // put (push) X1 onto top of stack BL myfunc // call the function // copy return adx into LR register // BL instruction writes sequentially following // adx for return to register, LR (X30) LDUR X2, [SP, #0] // get (pop) the return value myvar1 45 ADDI SP, SP, #8 // restore stack pointer or myfunct: MOV X3, #15 LDUR X0, [SP, #0] ADD X0, X0, X3 STUR X0, [SP, #0] BR LR // localvar 15 // get (peek) value from top of stack // compute sum X0 X0 + X3 // put (push) X0 onto stack // return to calling context myfunct: LDUR X0, [SP, #0] // get (peek) value from top of stack ADDI X0, X0, #15 // compute sum X0 X STUR X0, [SP, #0] // put (push) X0 onto stack BR LR // return to calling context Stack Frame Item being pushed onto or popped from stack Data structure called stack frame Special area set aside in memory for such purpose Some implementations support peek Value of item on top of stack returned without popping item Will not go into details at moment of Implementation Handling Sufficient to say Contains Return address From calling context Register values Local variables Passed parameters From return context Values to be returned - 26 of 27 -

27 Management Created when procedure called Pointer To stack frame returned Pointer placed on stack Summary Have introduced Instruction Set Architecture Major classes of instructions Intel machine ARM machine Let s now continue moving down to the register level To see how instructions are executed Examine registers and various forms they may take - 27 of 27 -