# Today s topics. MIPS operations and operands. MIPS arithmetic. CS/COE1541: Introduction to Computer Architecture. A Review of MIPS ISA.

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1 Today s topics CS/COE1541: Introduction to Computer Architecture MIPS operations and operands MIPS registers Memory view Instruction encoding A Review of MIPS ISA Sangyeun Cho Arithmetic operations Logic operations Memory access operations Computer Science Department MIPS operations and operands MIPS arithmetic Operation specifies what function to perform by the instruction Operand specifies with what a specific function is to be performed by the instruction MIPS operations Arithmetic (integer/floating-point) Logical Shift Compare Load/store Branch/jump System control and coprocessor MIPS operands Registers Fixed registers (e.g., HI/LO) Memory location Immediate value <op> <r target > <r source1 > <r source2 > All arithmetic instructions have 3 operands Operand order in notation is fixed; target first Two source registers and one target or destination register Examples add r1, r2, r3 sub r4, r5, r6 # r1 r2 + r3 # r4 r5 r6

2 MIPS registers General-purpose registers (GPRs) \$zero \$at \$v \$v1 \$a \$a1 \$a2 \$a3 \$t \$t1 \$t2 \$t3 \$t4 \$t5 \$t6 \$t7 32 bits 32 bits 32 bits r r1 r2 r3 r4 r5 r6 r7 r8 r9 r1 r11 r12 r13 r14 r15 r16 r17 r18 r19 r2 r21 r22 r23 r24 r25 r26 r27 r28 r29 r3 r31 General-Purpose Registers \$s \$s1 \$s2 \$s3 \$s4 \$s5 \$s6 \$s7 \$t8 \$t9 \$k \$k1 \$gp \$sp \$fp \$ra HI LO PC Special-Purpose Registers The name GPR implies that all these registers can be used as operands in instructions Still, conventions and limitations exist to keep GPRs from being used arbitrarily r, termed \$zero, always has a value of r31, termed \$ra (return address), is reserved for storing the return address for subroutine call/return Register usage and related software conventions are typically summarized in application binary interface (ABI) important when writing system software such as an assembler or a compiler 32 GPRs in MIPS Are they sufficient? Special-purpose registers Instruction encoding HI/LO registers are used for storing result from multiplication operations PC (program counter) Always keeps the pointer to the current program execution point; instruction fetching occurs at the address in PC Not directly visible and manipulated by programmers in MIPS Other architectures May not have HI/LO; use GPRs to store the result of multiplication May allow storing to PC to make a jump Instructions are encoded in binary numbers Assembler translates assembly programs into binary numbers Machine (processor) decodes binary numbers to figure out what the original instruction is MIPS has a fixed, 32-bit instruction encoding Encoding should be done in a way that decoding is easy MIPS instruction formats R-format: arithmetic instructions I-format: data transfer/arithmetic/jump instructions J-format: jump instruction format (FI-/FR-format: floating-point instruction format)

3 MIPS instruction formats Instruction encoding example Instruction Format op rs rt rd shamt funct address Field Size 6 bits 5 bits 5 bits 5 bits 5 bits 6 bits All MIPS instructions 32 bits add R reg reg reg 1 NA R-format op rs rt rd shamt funct Arithmetic/logic instruction format sub R reg reg reg 11 NA I-format op rs rt address/immediate Data transfer, branch, immediate format addi (add immediate) lw (load word) I 1 reg reg NA NA NA constant I 111 reg reg NA NA NA address J-format op target address Jump instruction format sw (store word) I 1111 reg reg NA NA NA address Logic instructions Dealing with immediate R-format op rs rt rd shamt funct Logic instruction format I-format op rs rt 16-bit immediate Transfer, branch, immediate format Bit-wise logic operations <op> <r target > <r source1 > <r source2 > Examples and r3, r2, r1 or r3, r2, r1 # r3 r2 & r1 # r3 r2 r1 nor r3, r2, r1 # r3 ~(r2 r1) xor r3, r2, r1 # r3 r2 ^ r1 Many operations involve small immediate value a = a + 1 b = b 4 c = d x4 Some frequently used arithmetic/logic instruction shave their immediate version addi r3, r2, 16 # r3 r andi r5, r4, xfffe # r5 r4 & b ori r4, r4, 4 # r4 r4 1b xori r7, r6, 16 # r7 r6 ^ 1b There is no subi ; why?

7 C program down to numbers Producing a binary swap: muli \$2, \$5, 4 add \$2, \$4, \$2 lw \$15, (\$2) lw \$16, 4(\$2) sw \$16, (\$2) sw \$15, 4(\$2) jr \$31 void swap(int v[], int k) { int temp; temp = v[k]; v[k] = v[k+1]; v[k+1] = temp; } source file.asm/.s source file.asm/.s source file.asm/.s assembler assembler assembler object file.obj/.o object file.obj/.o object file.obj/.o linker library.lib/.a executable.exe Wrapping up MIPS ISA Typical RISC style architecture 32 GPRs 32-bit instruction format 32-bit address space MIPS is the basis for our study throughout this semester; however, the concepts we study are not particularly tied with MIPS Operations & operands Arithmetic, logical, memory access, control instructions

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