MOS INTEGRATED CIRCUIT

Transcription

1 DATA SHEET MOS INTEGRATED CIRCIT µpd735 V5+ TM 6/8-BIT SINGLE-CHIP MICROCONTROLLER The µpd735 (V5+) is a single-chip microcontroller on which 6-bit CP, RAM, serial interface, timer, DMA controller, interrupt controller, etc. are all integrated. The µpd735 is software compatible with the 6/8-bit singlechip microcontroller µpd73 (V5 TM ). The V5+ greatly improves the DMA responsivity and transfer rate compared to the V5. FEATRES Software compatible with V5 Software compatible with µpd78/76 (in native mode) (some instructions added) Internal 6-bit architecture and external 8-bit data bus 3-stage pipeline method Minimum instruction cycle : 5 ns/8 MHz (external 6 MHz) : ns/ MHz (external MHz) Memory space Mbyte On-chip RAM : 56 words 8 bits Register bank (memory mapped method) : 8 banks Input port (port T) with comparator : 8 bits I/O lines (input port : 4 bits, input/output ports : bits) Serial interface : channels Internal dedicated baud rate generator Asynchronous mode and I/O interface mode Interrupt controller Programmable priority (8 levels) 3 types of interrupt response method Vectored interrupt function, register bank switching function, macro service function DRAM and pseudo SRAM refreshing function DMA controller : channels 4 types of DMA transfer mode Transfer rate Maximum 4 Mbytes/second (when stop control is not executed by DMARQ pin in demand release mode) Maximum Mbytes/second (when stop control is executed by DMARQ pin in demand release mode, or burst mode) Address pointer (linear) : bits Terminal counter : 6 bits 6-bit timer : channels Time base counter ( bits) : channel On-chip clock generator Programmable wait function Standby function (STOP, HALT) The information in this document is subject to change without notice. Document No. 85EJ7VDS (7th edition) Date Published November 997 N Printed in Japan The mark shows major revised points

2 µpd735 ORDERING INFORMATION Part Number Package External Clock (MHz) µpd735gj-8-5bg 94-pin plastic QFP ( mm) 6 µpd735gj--5bg 94-pin plastic QFP ( mm) µpd735l-8 84-pin plastic QFJ (5 5 mil) 6 µpd735l- 84-pin plastic QFJ (5 5 mil)

3 µpd735 Comparison between V5 and V5+ V5 V35 TM V5+ V35+ TM µpd73 µpd733 µpd735 µpd7335 Transfer processing method Depends on microprogram Depends on dedicated hardware Maximum transfer rate (8-MHz.6 Mbytes/second.8 Mbytes/second 4 Mbytes/second 5.3 Mbytes/second operation) Sampling timing of DMA request Between instruction execution cycles Between bus cycles DMA service channel In on-chip RAM area In special function register Specification method of transfer address Segment method Linear method DMA function Execution format in single-step mode DMA transfer/ instruction execution DMA transfer/ bus cycle Interrupt request during DMA transfer Accepts only NMI Not accepted (demand release mode) Number of necessary waits when Not necessary waits stop is controlled by DMARQ (demand release mode) Transfer processing units Byte/word Byte/word Byte Byte/word TC (terminal counter) setting value Number of times of DMA transfer (Number of times of DMA transfer) Generation timing of terminal counter TC = TC = FFFFH TC output low-level width Fixed Expanded by wait insertion Transmit clock output in Not available Available (SCK pin) asynchronous mode (channel ) Serial interface Serial error register Yes Serial status register Receive buffer full flag No In serial status register Transmit buffer empty flag No In serial status register All sent flag No In serial status register Interrupt function Interrupt source register No Yes External data bus 8 bits 6 bits 8 bits 6 bits Maximum operating frequency 8 MHz MHz 3

4 µpd735 PIN CONFIGRATION (Top View) 94-Pin Plastic QFP µpd735gj-8-5bg µpd735gj--5bg A NC A A9 A8 A7 A6 A5 A4 A3 A A A D7 D6 D5 D4 D3 D D D P7/CLKOT P6 A NC A3 A4 A5 A6 A7 A8 A9 RxD GND CTS TxD RxD CTS TxD P/DMARQ IC VDD VDD P/DMAAK NC P/TC P5 NC IC P4 P3 P P P EA MREQ IOSTB MSTB R/W REFRQ RESET VDD VDD X X GND GND NC NC VTH IC P3/DMARQ P4/DMAAK P5/TC P6/HLDAK P7/HLDRQ NMI (P) P/INTP P/INTP P3/INTP/INTAK P4/INT/POLL P5/TOT P6/SCK P7/READY PT PT PT PT3 PT4 PT5 NC PT6 PT7 IC Remarks. NC: Non-Connection. IC : Internally Connected Cautions. Fix IC pin individually to high level via a pull-up resistor externally.. Fix EA pin to low level. 4

5 µpd Pin Plastic QFJ µpd735l-8 µpd735l- P7/CLKOT 74 D 3 73 D 4 7 D 5 7 D3 6 7 D D D D7 66 A 65 A 64 A 3 63 A3 4 6 A4 5 6 A5 6 6 A A A A A 3 55 A 3 54 A A3 A4 A5 A6 A7 A8 A9 RxD GND CTS TxD RxD CTS TxD P/DMARQ IC VDD P/DMAAK P/TC IC P6 P5 IC P4 P3 P P P EA MREQ IOSTB MSTB R/W REFRQ RESET VDD X X GND VTH IC PT7 PT6 PT5 PT4 PT3 PT PT PT P7/READY P6/SCK P5/TOT P4/INT/POLL P3/INTP/INTAK P/INTP P/INTP NMI (P) P7/HLDRQ P6/HLDAK P5/TC P4/DMAAK P3/DMARQ Remark IC: Internally Connected Cautions. Fix IC pin individually to high level via a pull-up resistor externally. Fix EA pin to low level. 5

6 6 P/DMARQ P/DMAAK P/TC P3/DMARQ P4/DMAAK P5/TC TxD RxD P6/SCK CTS TxD RxD CTS PROGRAMMABLE DMA CONTROLLER SERIAL INTERFACE BAD RATE GENERATOR LC etc. PSW PC AL TA TB TC INTERNAL RAM 56 byte GR MACRO SERVICE CHANNEL STAGING LATCH STAGING LATCH ADM PFP INTERNAL ROM Note 8 Kbyte (reserved) INC BS CONTROL LOGIC A to A9 RESET HLDAK/P6 HLDRQ/P7 READY/P7 MREQ MSTB R/W IOSTB INTERNAL BLOCK DIAGRAM NMI (P) P/INTP P/INTP P3/INTP/INTAK P4/INT/POLL PROGRAMMABLE INTERRPT CONTROLLER INSTRCTION DECODER MICRO SEQENSER MICRO ROM QEE (6 byte) POLL/INT/P4 EA D to D7 6-BIT TIMER TIME BASE CONTER PORT PORT with COMPARATOR CG X X VDD TOT/P5 REFRQ CLKOT/P7 P P P PT to 7 VTH GND Note The internal ROM of 8 Kbytes is reserved for specific use such as testing and not user-accessible. µpd735

7 µpd735 CONTENTS. PIN FNCTIONS...8. Port Pins Non-port Pins INSTRCTION SETS.... Comparison between µpd78 and Instruction Set Operation....3 Instruction Set Table Number of Clocks Table ELECTRICAL SPECIFICATIONS PACKAGE DRAWINGS RECOMMENDED SOLDERING CONDITIONS

8 µpd735. PIN FNCTIONS. Port Pins Pin Name Input/Output Port Function Control Function P to P6 Input & output 8-bit input/output ports, each to P7/CLKOT Input & output/output be specified bit-by-bit System clock output NMI (P) Input sed as non-maskable interrupt request input (input port) P/INTP sed as both external interrupt P/INTP request input and input port P3/INTP/INTAK Input/input/output INT acknowledge signal output P4/POLL/INT Input & output/input/input sed as both specifiable input/ External interrupt request input output port and POLL input P5/TOT Input & output/output Input/output port specifiable Timer output P6/SCK bit-by-bit Serial clock output P7/READY Input & output/input READY input P/DMARQ Input & output/input 8-bit input/output port specifiable DMA request input (CH) P/DMAAK Input & output/input bit-by-bit DMA acknowledge output (CH) P/TC DMA end output (CH) P3/DMARQ Input & output/input DMA request input (CH) P4/DMAAK Input & output/output DMA acknowledge output (CH) P5/TC DMA end output (CH) P6/HLDAK Input & output/output HOLD acknowledge output P7/HLDRQ Input & output/input HOLD input PT to PT7 Input 8-bit input port with comparator Remark All port pins become input ports after reset is released. When using P3/INTP/INTAK as a INTAK pin, be sure to pull up the pin to avoid a malfunction of external interrupt controller after reset is released. 8

9 µpd735. Non-port Pins Pin Name Input/Output Function TxD Output Serial data output TxD RxD Input Serial data input RxD CTS Input & output CTS input in asynchronous mode, receive clock input/output in I/O interface mode CTS Input CTS input REFRQ Output DRAM refresh pulse output VTH Input Comparator reference voltage input RESET EA X X Reset signal input Fix to low level sed to connect crystal resonator for oscillating system clock. External clock is entered by entering reverse phase clock to both X and X pins. D to D7 Input & output 8-bit data bus A to A9 Output -bit address output MREQ MSTB R/W IOSTB VDD GND IC Output used to indicate that memory bus cycle has been started Memory read/memory write strobe output Read cycle/write cycle ID signal output I/O read/i/o write strobe output Positive power supply pins (all pins should be connected) GND pins (all pins should be connected) Internally connected (fix to high level via a pull-up resistor externally) 9

10 µpd735. INSTRCTION SETS The µpd735 instruction sets are compatible with those of µpd73.. Comparison between µpd78 and 76 The µpd735 instruction sets are upward-compatible with those of µpd78/76 in native mode. The following instructions are newly added to the µpd78/76. () Conditional branch instruction BTCLR Bit test instruction used for special function registers If, when this BTCLR is executed, the target special function register bit status is, the bit is reset () and the program is branched to short-label described in the operand. If the target bit status is, the program is moved to the next instruction. PSW is not changed in this instruction. (Descriptive format) Operand Mnemonic Special Function Special Function Register Address Register Bit Branch Address BTCLR sfr imm3 short-label () Interrupt instructions RETRBI Return instruction used for register banks This instruction is used to return the program from the interrupt service routine in which the register bank switching function is used. It cannot be used for returning from vectored interrupt servicing. (Descriptive format) Mnemonic Operand RETRBI None FINT This instruction is used to report the interrupt controller that interrupt servicing has ended. If an interrupt other than NMI, INT, and software interrupt is used, this instruction must be executed prior to the instruction for returning from interrupt servicing. It should not be used for NMI, INT and software interrupts. (Descriptive format) Mnemonic FINT Operand None (3) CP instruction STOP Instruction for transition to STOP state (Descriptive format) Mnemonic STOP Operand None

11 µpd735 (4) Register bank switch instructions BRKCS sed to switch register banks A register bank is switched to the register bank indicated by the lower 3 bits in the 6-bit register described in the operand. The program is also branched with this instruction to the address obtained from the PS stored in advance in the new register bank and the vector PC. The RETRBI instruction is used to return the program from the new register bank. (Descriptive format) Mnemonic BRKCS Operand reg6 TSKSW sed to switch register banks Just like the BRKCS instruction, this instruction is also executed to select a register bank. The program is branched to the address obtained from the PS stored in advance in the new register bank and the address obtained from the PC save area. (Descriptive format) Mnemonic TSKSW Operand reg6 (5) Data transfer instructions MOVSPA sed to transfer SS and SP values This instruction is executed to transfer both SS and SP values before the register bank is switched to SS and SP of the current (post-switching) register bank. (Descriptive format) Mnemonic MOVSPA Operand None MOVSPB sed to transfer SS and SP values This instruction is executed to transfer the SS and SP values of the current (pre-switching) register bank to the SS and SP of the new register bank indicated by the lower 3 bits in the 6- bit register described in the operand. (Descriptive format) Mnemonic MOVSPB Operand reg6 Some µpd78/76 instructions should be much cared as shown below when used for the µpd735. I/O instruction, primitive I/O instruction If PSW IBRK flag is reset (), an interrupt is generated without executing this instruction. Be sure to set () the IBRK flag when using the I/O instruction. FPO instruction An interrupt is generated without executing this instruction.

12 µpd735. Instruction Set Operation Table -. Operand Identifier Identifier reg, reg reg8, reg8 reg6, reg6 dmem mem mem8 mem6 mem3 sfr imm 8-/6-bit general register 8-bit general register 6-bit general register 8-/6-bit memory location 8-/6-bit memory location 8-bit memory location 6-bit memory location 3-bit memory location 8-bit special function register location Constant within to FFFFH Description imm3 Constant within to 7 imm4 imm8 imm6 acc sreg src-table src-block dst-block near-proc far-proc near-label short-label far-label memptr6 memptr3 regptr6 pop-value fp-op R Constant within to FH Constant within to FFH Constant within to FFFFH Register AW or AL Segment register 56-byte conversion table name Register IX-addressed block name Register IY-addressed block name Procedure in the current program segment Procedure in another program segment Label in the current program segment Label within end of instruction to 8 to +7 bytes Label in another program segment Word including location offset in the current program segment to which control is to be passed Double-word including location offset in another program segment to which control is to be passed and segment base address 6-bit general register including location offset in another program segment to which control is to be passed Number of bytes to be abandoned from stack ( to 64K, normally even number) Immediate value to judge instruction code of external floating point operation chip Register set

13 µpd735 Table -. Operation Code Identifier Identifier Description W Byte/word specification bit (: byte, : word). However, when s =, the sign extended byte data should be 6-bit operand even when W is. reg, reg Register field ( to ) mem Memory field ( to ) mod Mode field ( to ) s Sign extension specification bit (: Sign is not extended, : Sign is extended) X, XXX, YYY, ZZZ Data used to judge instruction code of external floating-point operation chip Table -3. Operation Identifier (/) AW AH AL BW CW CL DW SP PC PSW IX IY PS DS DS SS AC CY P S Z DIR IE V BRK Identifier Accumulator (6 bits) Accumulator (upper byte) Accumulator (lower byte) Register BW (6 bits) Register CW (6 bits) Register CW (lower byte) Register DW (6 bits) Stack pointer (6 bits) Program counter (6 bits) Program status word (6 bits) Index register (source) (6 bits) Index register (destination) (6 bits) Program segment register (6 bits) Data segment register (6 bits) Data segment register (6 bits) Stack segment register (6 bits) Auxiliary carry flag Carry flag Parity flag Sign flag Zero flag Direction flag Interrupt enable flag Overflow flag Break flag Description ( ) Contents in memory shown in ( ) disp ext-disp8 Displacement (8/6 bits) 6 bits obtained by extending sign of 8-bit displacement 3

14 µpd735 Table -3. Operation Identifier (/) Identifier temp Temporary register (8/6/3 bits) tmpcy Temporary carry flag ( bit) seg Immediate segment data (6 bits) offset Immediate offset data (6 bits) Transfer direction + Addition Subtraction Multiplication Division % Modulo H H AND OR Exclusive OR -digit hexadecimal number 4-digit hexadecimal number Description Table -4. Flag Operation Identifier Identifier (Blank) No change Cleared to Set to Set or cleared according to the result Not defined R The previously saved value is restored. Description Table -5. Memory Addressing mem mod BW + IX BW + IX + disp 8 BW + IX + disp 6 BW + IY BW + IY + disp 8 BW + IY + disp 6 BP + IX BP + IX + disp 8 BP + IX + disp 6 BP + IY BP + IY + disp 8 BP + IY + disp 6 IX IX + disp 8 IX + disp 6 IY IY + disp 8 IY + disp 6 DIRECT ADDRESS BP + disp 8 BP + disp 6 BW BW + disp 8 BW + disp 6 4

15 µpd735 Table -6. 8/6-Bit General Register Selection reg, reg W = W = AL AW CL CW DL DW BL BW AH SP CH BP DH IX BH IY Table -7. Segment Register Selection sreg DS PS SS DS 5

16 6 Group Mnemonic Operand Data transfer MOV reg,reg mem,reg reg,mem mem,imm reg,imm Operation Code W reg reg W mod reg mem W mod reg mem W mod mem W reg Bytes to 4 to 4 3 to 6 to 3 reg reg (mem) reg reg (mem) (mem) imm reg imm Operation Flags AC CY V P S Z.3 Instruction Set Table acc,dmem dmem,acc W W 3 3 When W =, AL (dmem) When W =, AH (dmem + ), AL (dmem) When W =, (dmem) AL When W =, (dmem + ) AH, (dmem) AL sreg,reg6 sreg reg sreg reg6 sreg : SS, DS, DS sreg,mem6 mod sreg mem to 4 sreg (mem6) sreg : SS, DS, DS reg6,sreg sreg reg reg6 sreg mem6,sreg mod sreg mem to 4 (mem6) sreg DS,reg6, mem3 DS,reg6, mem3 mod reg mem mod reg mem to 4 to 4 reg6 (mem3) DS (mem3 + ) reg6 (mem3) DS (mem3 + ) AH,PSW AH S, Z, F, AC, F, P, IBRK, CY PSW,AH S, Z, F, AC, F, P, IBRK, CY AH LDEA reg6,mem6 mod reg mem to 4 reg6 mem6 TRANS src-table AL (BW + AL) XCH reg,reg W reg reg reg reg mem,reg reg,mem AW,reg6 reg6,aw W reg mod reg mem to 4 (mem) reg AW reg6 MOVSPA Note New register bank SS and SP old register bank SS and SP MOVSPB Note reg6 reg Note These instructions are newly added to the µ PD78/76. 3 SS and SP of reg6-indicated new register bank old register bank SS and SP µpd735

17 Group Mnemonic Operand Repeat prefix REPC REPNC Operation Code Bytes Operation Executes the primitive block transfer instruction in the continued byte while CW, and decrements CW by one. If any interruption is held at this time, it is processed. The program exits the loop when CY. Same as above. The program exits the loop when CY. Flags AC CY V P S Z REP REPE REPZ Executes the primitive block transfer instruction in the continued byte while CW, and decrements CW by one. If any interruption is held at this time, it is processed. The program exits the loop when the primitive block transfer instruction is CMPBK or CMPM, and when Z. REPNE REPNZ Same as above. The program exits the loop when Z. Primitive block transfer MOVBK CMPBK CMPM LDM STM dst-block, src-block src-block, dst-block dst-block src-block dst-block W W W W W When W =, (IY) (IX) DIR = : IX IX +, IY IY + DIR = : IX IX, IY IY When W =, (IY +, IY) (IX +, IX) DIR = : IX IX +, IY IY + DIR = : IX IX, IY IY When W =, (IX) (IY) DIR = : IX IX +, IY IY + DIR = : IX IX, IY IY When W =, (IX +, IX) (IY +, IY) DIR = : IX IX +, IY IY + DIR = : IX IX, IY IY When W =, AL (IY) DIR = : IY IY + ; DIR = : IY IY When W =, AW (IY +, IY) DIR = : IY IY + ; DIR = : IY IY When W =, AL (IX) DIR = : IX IX + ; DIR = : IX IX When W =, AW (IX +, IX) DIR = : IX + ; DIR = : IX IX When W =, (IY) AL DIR = : IY IY + ; DIR = : IY IY When W =, (IY +, IY) AW DIR = : IY IY + ; DIR = : IY IY µpd735 7

18 8 Group Mnemonic Operand Operation Code Bytes Operation Flags AC CY V P S Z Bit field operation INS reg8,reg8 reg reg 3 6-bit field AW reg8,imm4 4 6-bit field AW reg EXT reg8,reg8 3 AW 6-bit field reg reg reg8,imm4 4 AW 6-bit field reg I/O Primitive I/O IN OT INM OTM Note Note Note Note acc,imm8 acc,dw imm8,acc DW,acc dst-block,dw DW,src-block W W W W W W When W =, AL (imm8) When W =, AH (imm8 + ), AL (imm8) When W =, AL (DW) When W =, AH (DW + ), AL (DW) When W =, (imm8) AL When W =, (imm8 + ) AH, (imm8) AL When W =, (DW) AL When W =, (DW + ) AH, (DW) AL When W =, (IY) (DW) DIR = : IY IY + ; DIR = : IY IY When W =, (IY +, IY) (DW +, DW) DIR = : IY IY + ; DIR = : IY IY When W =, (DW) (IX) DIR = : IX IX + ; DIR = : IX IX When W =, (DW +, DW) (IX +, IX) DIR = : IX IX + ; DIR = : IX IX Note When IBRK =, a software interrupt is generated automatically and the instruction is not executed. µpd735

19 Group Mnemonic Operand Operation Code Bytes Operation Flags AC CY V P S Z Addition/ subtraction ADD reg,reg mem,reg W W reg reg mod reg mem to 4 reg reg + reg (mem) (mem) + reg reg,mem W mod reg mem to 4 reg reg + (mem) reg,imm s W reg 3 to 4 reg reg + imm mem,imm s W mod mem 3 to 6 (mem) (mem) + imm acc,imm W to 3 When W =, AL AL + imm When W =, AW AW + imm ADDC reg,reg W reg reg reg reg + reg + CY mem,reg W mod reg mem to 4 (mem) (mem) + reg + CY reg,mem W mod reg mem to 4 reg reg + (mem) + CY reg,imm s W reg 3 to 4 reg reg + imm + CY mem,imm s W mod mem 3 to 6 (mem) (mem) + imm + CY acc,imm W to 3 When W =, AL AL + imm + CY When W =, AW AW + imm + CY SB reg,reg W reg reg reg reg reg mem,reg W mod reg mem to 4 (mem) (mem) reg reg,mem W mod reg mem to 4 reg reg (mem) reg,imm s W reg 3 to 4 reg reg imm mem,imm s W mod mem 3 to 6 (mem) (mem) imm acc,imm W to 3 When W =, AL AL imm When W =, AW AW imm SBC reg,reg W reg reg reg reg reg CY mem,reg W mod reg mem to 4 (mem) (mem) reg CY 9 reg,mem reg,imm mem,imm acc,imm W s W s W W mod reg mem reg mod mem to 4 3 to 4 3 to 6 to 3 reg reg (mem) CY reg reg imm CY (mem) (mem) imm CY When W =, AL AL imm CY When W =, AW AW imm CY µpd735

20 Group Mnemonic Operand Operation Code Bytes Operation Flags AC CY V P S Z BCD operation ADD4S SB4S dst BCD string dst BCD string + src BCD string dst BCD string dst BCD string src BCD string Note Note CMP4S dst BCD string src BCD string Note ROL4 reg8 reg 3 ALL pper Byte reg Lower Byte mem8 mod mem 3 to 5 ALL pper Byte mem Lower Byte ROR4 reg8 reg 3 ALL pper Byte reg Lower Byte mem8 mod mem 3 to 5 ALL pper Byte mem Lower Byte Increment/ decrement INC reg8 mem W reg mod mem to 4 reg8 reg8 + (mem) (mem) + reg6 reg reg6 reg6 + DEC reg8 reg reg8 reg8 mem W mod mem to 4 (mem) (mem) reg6 reg reg6 reg6 Note The number of BCD digits is given in the CL register. The value can be set within to 54. µpd735

21 Group Mnemonic Operand Operation Code Bytes Operation Flags AC CY V P S Z Multiplication ML reg8 reg AW AL reg8 AH = : CY, V AH : CY, V mem8 mod mem to 4 AW AL (mem8) AH = : CY, V AH : CY, V reg6 reg DW, AW AW reg6 DW = : CY, V DW = : CY, V mem6 mod mem to 4 DW, AW AW (mem6) DW = : CY, V DW = : CY, V ML reg8 reg AW AL reg8 Extension of AH = AL sign: CY, V Extension of AH AL sign: CY, V mem8 mod mem to 4 AW AL (mem8) Extension of AH = AL sign: CY, V Extension of AH AL sign: CY, V reg6 reg DW, AW AW reg6 Extension of DW = AW sign: CY, V Extension of DW AW sign: CY, V mem6 mod mem to 4 DW, AW AW (mem6) Extension of DW = AW sign: CY, V Extension of DW AW sign: CY, V reg6, (reg6,) Note imm8 reg reg 3 reg6 reg6 imm8 Product 6 bits: CY, V Product > 6 bits: CY, V reg6, mem6, imm8 mod reg mem 3 to 5 reg6 (mem6) imm8 Product 6 bits: CY, V Product > 6 bits: CY, V reg6, (reg6,) Note imm6 reg6, mem6, imm6 reg reg mod reg mem 4 4 to 6 Note The nd operand is omissible. If omitted, the st operand is assumed. reg6 reg6 imm6 Product 6 bits: CY, V Product > 6 bits: CY, V reg6 (mem6) imm6 Product 6 bits: CY, V Product > 6 bits: CY, V µpd735

22 Group Mnemonic Operand Operation Code Bytes Operation Flags AC CY V P S Z nsigned division DIV reg8 reg temp AW When temp reg8 FFH AH temp%reg8, AL temp reg8 When temp reg8 > FFH (SP, SP ) PSW, (SP 3, SP 4) PS (SP 5, SP 6) PC, SP SP 6 IE, BRK, PS (3, ), PC (, ) mem8 mod mem to 4 temp AW When temp (mem8) FFH AH temp%(mem8), AL temp (mem8) When temp (mem8) > FFH (SP, SP ) PSW, (SP 3, SP 4) PS (SP 5, SP 6) PC, SP SP 6 IE, BRK, PS (3, ), PC (, ) reg6 reg temp DW, AW When temp reg6 FFFFH DW temp%reg6, AW temp reg6 When temp reg6 > FFFFH (SP, SP ) PSW, (SP 3, SP 4) PS (SP 5, SP 6) PC, SP SP 6 IE, BRK, PS (3, ), PC (, ) mem6 mod mem to 4 temp DW, AW When temp (mem6) FFFFH DW temp%(mem6), AW temp (mem6) When temp (mem6) > FFFFH (SP, SP ) PSW, (SP 3, SP 4) PS (SP 5, SP 6) PC, SP SP 6 IE, BRK, PS (3, ), PC (, ) µpd735

23 Group Mnemonic Operand Operation Code Bytes Operation Flags AC CY V P S Z Signed division DIV reg8 reg temp AW When temp reg8 > and temp reg8 7FH or temp reg8 < and temp reg8 > 7FH AH temp%reg8, AL temp reg8 When temp reg8 > and temp reg8 > 7FH or temp reg8 > and temp reg8 < 7FH (SP, SP ) PSW, (SP 3, SP 4) PS (SP 5, SP 6) PC, SP SP 6 IE, BRK, PS (3, ), PC (, ) mem8 mod mem to 4 temp AW When temp (mem8) > and temp (mem8) 7FH or temp (mem8) < and temp (mem8) > 7FH AH temp%(mem8), AL temp (mem8) When temp (mem8) > and temp (mem8) > 7FH or temp (mem8) > and temp (mem8) < 7FH (SP, SP ) PSW, (SP 3, SP 4) PS (SP 5, SP 6) PC, SP SP 6 IE, BRK, PS (3, ), PC (, ) reg6 reg temp DW, AW When temp reg6 > and temp reg6 7FFFH or temp reg6 < and temp reg6 > 7FFFH DW temp%reg6, AW temp reg6 When temp reg6 > and temp reg6 > 7FFFH or temp reg6 > and temp reg6 < 7FFFH (SP, SP ) PSW, (SP 3, SP 4) PS (SP 5, SP 6) PC, SP SP 6 IE, BRK, PS (3, ), PC (, ) mem6 mod mem to 4 temp DW, AW When temp (mem6) > and temp (mem6) 7FFFH or temp (mem6) < and temp (mem6) > 7FFFH DW temp%(mem6), AW temp (mem6) When temp (mem6) > and temp (mem6) > 7FFFH or temp (mem6) > and temp (mem6) < 7FFFH (SP, SP ) PSW, (SP 3, SP 4) PS (SP 5, SP 6) PC, SP SP 6 IE, BRK, PS (3, ), PC (, ) µpd735 3

24 4 Group Mnemonic Operand BCD adjustment ADJBA ADJ4A Operation Code Bytes Operation When AL FH > 9 or AC =, AL AL + 6 AH AH +, AC, CY AC, AL AL FH When AL FH > 9 or AC =, AL AL + 6, AC When AL > 9FH or CY =, AL AL + 6H, CY Flags AC CY V P S Z ADJBS When AL FH > 9 or AC =, AL AL 6, AH AH, AC CY AC, AL AL FH ADJ4S When AL FH > 9 or AC =, AL AL 6, AC When AL > 9FH or CY =, AL AL 6H, CY Data conversion CVTBD CVTDB AH AL AH, AL AL%AH AL AH AH + AL, AH CVTBW When AL < 8H, AH. In other cases, AH FFH. CVTWL When AW < 8H, DW. In other cases, DW FFFFH. Compare CMP reg,reg W reg reg reg reg mem,reg W mod reg mem to 4 (mem) reg reg,mem W mod reg mem to 4 reg (mem) reg,imm s W reg 3 to 4 reg imm mem,imm s W mod mem 3 to 6 (mem) imm acc,imm W to 3 When W =, AL imm When W =, AW imm Complement operation NOT reg mem W W reg mod mem to 4 reg reg (mem) (mem) NEG reg W reg reg reg + mem W mod mem to 4 (mem) (mem) + µpd735

25 Group Mnemonic Operand Operation Code Bytes Operation Flags AC CY V P S Z Logical operation TEST reg,reg mem,reg reg,mem W W reg reg mod reg mem to 4 reg reg (mem) reg reg,imm W reg 3 to 4 reg imm mem,imm W mod mem 3 to 6 (mem) imm acc,imm W to 3 When W =, AL imm8 When W =, AW imm6 AND reg,reg W reg reg reg reg reg mem,reg W mod reg mem to 4 (mem) (mem) reg reg,mem W mod reg mem to 4 reg reg (mem) reg,imm W reg 3 to 4 reg reg imm mem,imm W mod mem 3 to 6 (mem) (mem) imm acc,imm W to 3 When W =, AL AL imm8 When W =, AW AW imm6 OR reg,reg W reg reg reg reg reg mem,reg W mod reg mem to 4 (mem) (mem) reg reg,mem W mod reg mem to 4 reg reg (mem) reg,imm W reg 3 to 4 reg reg imm mem,imm W mod mem 3 to 6 (mem) (mem) imm acc,imm W to 3 When W =, AL AL imm8 When W =, AW AW imm6 XOR reg,reg W reg reg reg reg reg mem,reg W mod reg mem to 4 (mem) (mem) reg reg,mem W mod reg mem to 4 reg reg (mem) 5 reg,imm mem,imm acc,imm W W W reg mod mem 3 to 4 3 to 6 to 3 reg reg imm (mem) (mem) imm When W =, AL AL imm8 When W =, AW AW imm6 µpd735

26 6 Group Mnemonic Operand Bit manipulation TEST reg8,cl mem8,cl reg6,cl mem6,cl reg8,imm3 mem8,imm3 reg6,imm4 mem6,imm4 Operation Code reg mod mem reg mod mem reg mod mem reg mod mem Bytes 3 3 to to to to 6 reg8 bit No. CL = : Z reg8 bit No. CL = : Z (mem8) bit No. CL = : Z (mem8) bit No. CL = : Z reg6 bit No. CL = : Z reg6 bit No. CL = : Z (mem6) bit No. CL = : Z (mem6) bit No. CL = : Z reg8 bit No. imm3 = : Z reg8 bit No. imm3 = : Z (mem8) bit No. imm3 = : Z (mem8) bit No. imm3 = : Z reg6 bit No. imm4 = : Z reg6 bit No. imm4 = : Z (mem6) bit No. imm4 = : Z (mem6) bit No. imm4 = : Z Operation Flags AC CY V P S Z NOT reg8,cl reg 3 reg8 bit No. CL reg8 bit No. CL mem8,cl mod mem 3 to 5 (mem8) bit No. CL (mem8) bit No. CL reg6,cl reg 3 reg6 bit No. CL reg6 bit No. CL mem6,cl mod mem 3 to 5 (mem6) bit No. CL (mem6) bit No. CL reg8,imm3 reg 4 reg8 bit No. imm3 reg8 bit No. imm3 mem8,imm3 mod mem 4 to 6 (mem8) bit No. imm3 (mem8) bit No. imm3 reg6,imm4 reg 4 reg6 bit No. imm4 reg6 bit No. imm4 mem6,imm4 mod mem 4 to 6 (mem6) bit No. imm4 (mem6) bit No. imm4 nd byte Note 3rd byte Note Note st byte = FH NOT CY CY CY µpd735

27 Group Mnemonic Operand Operation Code Bytes Operation Flags AC CY V P S Z Bit manipulation CLR reg8,cl mem8,cl reg mod mem 3 3 to 5 reg8 bit No. CL (mem8) bit No. CL reg6,cl reg 3 reg6 bit No. CL mem6,cl mod mem 3 to 5 (mem6) bit No. CL reg8,imm3 reg 4 reg8 bit No. imm3 mem8,imm3 mod mem 4 to 6 (mem8) bit No. imm3 reg6,imm4 reg 4 reg6 bit No. imm4 mem6,imm4 mod mem 4 to 6 (mem6) bit No. imm4 SET reg8,cl reg 3 reg8 bit No. CL mem8,cl mod mem 3 to 5 (mem8) bit No. CL reg6,cl reg 3 reg6 bit No. CL mem6,cl mod mem 3 to 5 (mem6) bit No. CL reg8,imm3 reg 4 reg8 bit No. imm3 mem8,imm3 mod mem 4 to 6 (mem8) bit No. imm3 reg6,imm4 reg 4 reg6 bit No. imm4 mem6,imm4 mod mem 4 to 6 (mem6) bit No. imm4 nd byte Note 3rd byte Note Note st byte = FH CLR CY CY DIR DIR 7 SET CY DIR CY DIR µpd735

28 8 Group Mnemonic Operand Operation Code Bytes Operation Flags AC CY V P S Z Shift SHL reg, W reg CY reg MSB, reg reg When reg MSB CY, V When reg MSB = CY, V mem, W mod mem to 4 CY (mem) MSB, (mem) (mem) When (mem) MSB CY, V When (mem) MSB = CY, V reg,cl mem,cl reg,imm8 mem,imm8 W W W W reg mod mem reg mod mem to to 5 The following operations are repeated while temp CL and temp. CY reg MSB, reg reg temp temp The following operations are repeated while temp CL and temp. CY (mem) MSB, (mem) (mem) temp temp The following operations are repeated while temp imm8 and temp. CY reg MSB, reg reg temp temp The following operations are repeated while temp imm8 and temp. CY (mem) MSB, (mem) (mem) temp temp µpd735

29 Group Mnemonic Operand Operation Code Bytes Operation Flags AC CY V P S Z Shift SHR reg, W reg CY reg LSB, reg reg reg MSB bit following reg MSB: V reg MSB = bit following reg MSB: V mem, W mod mem to 4 CY (mem) LSB, (mem) (mem) (mem) MSB bit following (mem) MSB: V (mem) MSB = bit following (mem) MSB: V 9 SHRA reg,cl mem,cl reg,imm8 mem,imm8 reg, mem, reg,cl mem,cl reg,imm8 mem,imm8 W W W W W W W W W W reg mod mem reg mod mem reg mod mem reg mod mem reg mod mem to to 5 to 4 to to 5 The following operations are repeated while temp CL and temp. CY reg LSB, reg reg temp temp The following operations are repeated while temp CL and temp. CY (mem) LSB, (mem) (mem) temp temp The following operations are repeated while temp imm8 and temp. CY reg LSB, reg reg temp temp The following operations are repeated while temp imm8 and temp. CY (mem) LSB, (mem) (mem) temp temp CY reg LSB, reg reg, V The operand MSB remains the same status. CY (mem) LSB, (mem) (mem), V The operand MSB remains the same status. The following operations are repeated while temp CL and temp. CY reg LSB, reg reg temp temp The operand MSB remains the same status. The following operations are repeated while temp CL and temp. CY (mem) LSB, (mem) (mem) temp temp The operand MSB remains the same status. The following operations are repeated while temp imm8 and temp. CY reg LSB, reg reg temp temp The operand MSB remains the same status. The following operations are repeated while temp imm8 and temp. CY (mem) LSB, (mem) (mem) temp temp The operand MSB remains the same status. µpd735

30 3 Group Mnemonic Operand Operation Code Bytes Operation Flags AC CY V P S Z Rotate ROL reg, W reg CY reg MSB, reg reg + CY reg MSB CY: V reg MSB = CY: V mem, W mod mem to 4 CY (mem) MSB, (mem) (mem) + CY (mem) MSB CY: V (mem) MSB = CY: V ROR reg,cl mem,cl reg,imm8 mem,imm8 reg, mem, reg,cl mem,cl reg,imm8 mem,imm8 W W W W W W W W W W reg mod mem reg mod mem reg mod mem reg mod mem reg mod mem to to 5 to 4 to to 5 The following operations are repeated while temp CL and temp. CY reg MSB, reg reg + CY temp temp The following operations are repeated while temp CL and temp. CY (mem) MSB, (mem) (mem) + CY temp temp The following operations are repeated while temp imm8 and temp. CY reg MSB, reg reg + CY temp temp The following operations are repeated while temp imm8 and temp. CY (mem) MSB, (mem) (mem) + CY temp temp CY reg LSB, reg reg reg MSB CY reg MSB bit following reg MSB: V reg MSB = bit following reg MSB: V CY (mem) LSB, (mem) (mem) (mem) MSB CY (mem) MSB bit following (mem) MSB: V (mem) MSB = bit following (mem) MSB: V The following operations are repeated while temp CL and temp. CY reg LSB, reg reg reg MSB CY temp temp The following operations are repeated while temp CL and temp. CY (mem) LSB, (mem) (mem) (mem) MSB CY temp temp The following operations are repeated while temp imm8 and temp. CY reg LSB, reg reg reg MSB CY temp temp The following operations are repeated while temp imm8 and temp. CY (mem) LSB, (mem) (mem) (mem) MSB CY temp temp µpd735

31 Group Mnemonic Operand Rotate ROLC reg, mem, reg,cl mem,cl Operation Code W reg W mod mem W reg W mod mem Bytes to 4 to 4 Operation tmpcy CY, CY reg MSB reg reg + tmpcy reg MSB CY: V reg MSB = CY: V tmpcy CY, CY (mem) MSB (mem) (mem) + tmpcy (mem) MSB CY: V (mem) MSB = CY: V The following operations are repeated while temp CL and temp. tmpcy CY, CY reg MSB reg reg + tmpcy temp temp The following operations are repeated while temp CL and temp. tmpcy CY, CY (mem) MSB (mem) (mem) + tmpcy temp temp Flags AC CY V P S Z reg,imm8 W reg 3 The following operations are repeated while temp imm8 and temp. tmpcy CY, CY reg MSB reg reg + tmpcy temp temp mem,imm8 W mod mem 3 to 5 The following operations are repeated while temp imm8 and temp. tmpcy CY, CY (mem) MSB (mem) (mem) + tmpcy temp temp µpd735 3

32 3 Group Mnemonic Operand Operation Code Bytes Operation Flags AC CY V P S Z Rotate RORC reg, W reg tmpcy CY, CY reg LSB reg reg reg MSB tmpcy reg MSB bit following reg MSB: V reg MSB = bit following reg MSB: V mem, W mod mem to 4 tmpcy CY, CY (mem) LSB (mem) (mem) (mem) MSB tmpcy (mem) MSB bit following (mem) MSB: V (mem) MSB = bit following (mem) MSB: V reg,cl W reg The following operations are repeated while temp CL and temp. tmpcy CY, CY reg LSB reg reg reg MSB tmpcy temp temp mem,cl W mod mem to 4 The following operations are repeated while temp CL and temp. tmpcy CY, CY (mem) LSB (mem) (mem) (mem) MSB tmpcy temp temp reg,imm8 mem,imm8 W W reg mod mem 3 3 to 5 The following operations are repeated while temp imm8 and temp. tmpcy CY, CY reg LSB reg reg reg MSB tmpcy temp temp The following operations are repeated while temp imm8 and temp. tmpcy CY, CY (mem) LSB (mem) (mem) (mem) MSB tmpcy temp temp µpd735

33 Group Mnemonic Operand Subroutine control CALL near-proc regptr6 memptr6 Operation Code reg mod mem Bytes 3 to 4 Operation (SP, SP ) PC, SP SP PC PC + disp (SP, SP ) PC, PC regptr6 SP SP (SP, SP ) PC, SP SP PC (memptr6) Flags AC CY V P S Z far-proc 5 (SP, SP ) PS, (SP 3, SP 4) PC SP SP 4 PS seg, PC offset memptr3 mod mem to 4 (SP, SP ) PS, (SP 3, SP 4) PC SP SP 4 PS (memptr3 + ), PC (memptr3) RET pop-value 3 PC (SP +, SP) SP SP + PC (SP +, SP) SP SP +, SP SP + pop-value PC (SP +, SP) PS (SP + 3, SP + ) SP SP + 4 pop-value 3 PC (SP +, SP) PS (SP + 3, SP + ) SP SP + 4, SP SP + pop-value µpd735 33

34 34 Group Mnemonic Operand Stack manipulation PSH mem6 reg6 sreg PSW Operation Code mod mem reg sreg Bytes to 4 (SP, SP ) (mem6) SP SP (SP, SP ) reg6 SP SP (SP, SP ) sreg SP SP (SP, SP ) PSW SP SP Operation Flags AC CY V P S Z R Push registers on the stack POP imm8 imm6 mem6 reg6 sreg PSW reg sreg mod mem 3 to 4 (SP, SP ) imm8 sign extension SP SP (SP, SP ) imm6 SP SP (mem6) (SP +, SP) SP SP + reg6 (SP +, SP) SP SP + sreg (SP +, SP) SP SP + PSW (SP +, SP) SP SP + sreg: SS, DS, DS R R R R R R R Pop registers from the stack PREPARE imm6,imm8 4 Prepare New Stack Frame DISPOSE Dispose of Stack Frame Branch BR near-label 3 PC PC + disp short-label PC PC + ext-disp8 regptr6 reg PC regptr6 memptr6 mod mem to 4 PC (memptr6) far-label memptr3 mod mem 5 to 4 PS seg PC offset PS (memptr3 + ) PC (memptr3) µpd735

35 Group Mnemonic Operand Operation Code Bytes Operation Flags AC CY V P S Z Conditional branch BV BNV short-label short-label if V = if V = PC PC + ext-disp8 PC PC + ext-disp8 BC BL BNC BNL BE BZ BNE BNZ short-label short-label short-label short-label if CY = if CY = if Z = if Z = PC PC + ext-disp8 PC PC + ext-disp8 PC PC + ext-disp8 PC PC + ext-disp8 BNH short-label if CY Z = PC PC + ext-disp8 BH short-label if CY Z = PC PC + ext-disp8 BN short-label if S = PC PC + ext-disp8 BP short-label if S = PC PC + ext-disp8 BPE short-label if P = PC PC + ext-disp8 BPO short-label if P = PC PC + ext-disp8 BLT short-label if S V = PC PC + ext-disp8 BGE short-label if S V = PC PC + ext-disp8 BLE short-label if (S V) Z = PC PC + ext-disp8 BGT short-label if (S V) Z = PC PC + ext-disp8 DBNZNE DBNZE DBNZ short-label short-label short-label CW = CW if Z = and CW CW = CW if Z = and CW CW = CW if CW PC PC + ext-disp8 PC PC + ext-disp8 PC PC + ext-disp8 BCWZ short-label if CW = PC PC + ext-disp8 35 BTCLR Note sfr, imm3, short-label Note This instruction is newly added to the µ PD78/76. 5 When (sfr) bit No. imm3 =, PC PC + ext-disp8 and (sfr) bit No. imm3. µpd735

36 36 Group Mnemonic Operand Interrupt BRK 3 imm8 ( 3) Operation Code Bytes Operation (SP, SP ) PSW, (SP 3, SP 4) PS, (SP 5, SP 6) PC, SP SP 6 IE, BRK PS (5, 4), PC (3, ) (SP, SP ) PSW, (SP 3, SP 4) PS, (SP 5, SP 6) PC, SP SP 6 IE, BRK PS (n 4 + 3, n 4 + ), PC (n 4 +, n 4) n = imm8 Flags AC CY V P S Z BRKV When V =, (SP, SP ) PSW, (SP 3, SP 4) PS, (SP 5, SP 6) PC, SP SP 6 IE, BRK PS (9, 8), PC (7, 6) RETI PC (SP +, SP), PS (SP + 3, SP + ), PSW (SP + 5, SP + 4), SP SP + 6 R R R R R R RETRBI Note PC Save PC, PSW Save PSW R R R R R R FINT Note Reports the CP internal interrupt controller that interrupt service routine operation has ended. CHKIND reg6,mem3 mod reg mem to 4 When (mem3) > reg6 or (mem3 + ) < reg6, (SP, SP ) PSW, (SP 3, SP 4) PS, (SP 5, SP 6) PC, SP SP 6 IE, BRK PS (3, ), PC (, ) Register bank switch BRKCS Note reg6 reg 3 RB lower 3 bits of reg6, IE, BRK Save PSW PSW, Save PC PC, PC Vector PC TSKSW Note reg6 reg 3 RB lower 3 bits of reg6, Old register bank Save PSW and Save PC PSW and PC, PSW and PC New register bank Save PSW and Save PC Note These instructions are newly added to the µ PD78/76. µpd735

37 Group Mnemonic Operand Operation Code Bytes Operation Flags AC CY V P S Z CP control HALT STOP Note CP Halt CP Stop POLL Poll and wait DI IE EI IE BSLOCK Bus Lock Prefix FPO fp-op X X X Y Y Y Z Z Z No Operation Note 3 fp-op,mem X X X mod Y Y Y mem to 4 data bus (mem) FPO fp-op X Y Y Y Z Z Z No Operation Note 3 fp-op,mem X mod Y Y Y mem to 4 data bus (mem) NOP No Operation Note sreg Segment override prefix Notes. DS:, DS:, PS: and SS:. This instruction is newly added to the µ PD78/ In the µ PD73, an interrupt is generated without executing these instructions. µpd735 37

38 µpd735.4 Number of Clocks Table () Legend The number of clocks, for memory operand, differs among addressing modes. So, use the following values for EA items shown in Table -9 Number of Clocks. Table -8. Number of Clocks for Each Memory Addressing mod mem Clocks Clocks Clocks BW + IX 3 BW + IX + disp8 3 BW + IX + disp6 4 BW + IY 3 BW + IY + disp8 3 BW + IY + disp6 4 BP + IX 3 BP + IX + disp8 3 BP + IX + disp6 4 BP + IY 3 BP + IY + disp8 3 BP + IY + disp6 4 IX 3 IX + disp8 3 IX + disp6 4 IY 3 IY + disp8 3 IY + disp6 4 Direct address 3 BP + disp8 3 BP + disp6 4 BW 3 BW + disp8 3 BW + disp6 4 T indicates the number of wait states. se any number of waits starting at (no wait). 38

39 µpd735 () Number of clocks Table -9. Number of Clocks (/) Group Mnemonic Operands Number of Clocks Byte Processing Word Processing On-chip RAM On-chip RAM On-chip RAM On-chip RAM Access Enable Access Disable Access Enable Access Disable Data MOV reg, reg transfer mem, reg EA T EA + EA T EA + reg, mem EA T EA T EA T EA T mem, imm EA T EA T EA T EA T reg, imm acc, dmem 9 + T 9 + T + T + T dmem, acc 7 + T T 5 sreg, reg6 4 4 sreg, mem6 EA + + T EA + + T reg6, sreg 3 3 mem6, sreg EA T EA + 3 DS, reg6, EA T EA T mem3 DS, reg6, EA T EA T mem3 AH, PSW PSW, AH 3 3 LDEA reg6, mem6 EA + EA + TRANS src-table + T + T XCH reg, reg mem, reg/ EA + + T EA T EA T EA + + T reg, mem AW, reg6/ 4 4 reg6, AW MOVSPA 6 6 MOVSPB reg6 Repeat REPC prefix REPNC REP/REPE/ REPZ REPNE/ REPNZ Primitive MOVKB Note dst-block, + T 6 + T T + T block Note src-block 6 + (6 + T) n 6 + ( + T) n 6 + ( + 4 T) n 6 + ( + T) n transfer CMPKB Note dst-block, 3 + T 9 + T T + 4 T Note src-block 6 + ( + T) n 6 + ( + T) n 6 + (5 + 4 T) n 6 + (5 + T) n Notes. Not repeated. Repeated, n: number of transfer times (n ) 39

40 µpd735 Table -9. Number of Clocks (/) Number of Clocks Group Mnemonic Operands Byte Processing Word Processing On-chip RAM On-chip RAM On-chip RAM On-chip RAM Access Enable Access Disable Access Enable Access Disable Primitive CMPM Note dst-block 7 + T 7 + T 9 + T 9 + T block Note src-block 6 + (5 + T) n 6 + (5 + T) n 6 + (7 + T) n 6 + (7 + T) n transfer LDM Note src-block + T + T 4 + T 4 + T Note 6 + ( + T) n 6 + ( + T) n 6 + ( + T) n 6 + ( + T) n STM Note dst-block + T 4 + T Note 6 + (8 + T) n 6 + (6 + T) n 6 + ( + T) n 6 + (6 + T) n Bit field INS reg8, reg8 63 to 55 (The processing differs among bit lengths.) manipula- reg8, imm4 64 to 56 (The processing differs among bit lengths.) tion EXT reg8, reg8 4 to (The processing differs among bit lengths.) reg8, imm4 4 to (The processing differs among bit lengths.) I/O IN acc, imm8 4 + T 4 + T 6 + T 6 + T Note 3 acc, DW 3 + T 3 + T 5 + T 5 + T OT imm8, acc + T + T + T + T Note 3 DW, acc 9 + T 9 + T 9 + T 9 + T Primitive INM dst-block, DW 9 + T 7 + T + 4 T T I/O Note (3 + T) n 8 + ( + T) n 8 + (5 + 4 T) n 8 + ( + 4 T) n OTM DW, src-block 9 + T 7 + T + 4 T T Note (3 + T) n 8 + ( + T) n 8 + (5 + 4 T) n 8 + ( + 4 T) n Addition/ ADD reg, reg subtraction mem, reg EA T EA T EA T EA T reg, mem EA T EA T EA T EA T reg, imm mem, imm EA T EA T EA T EA T acc, imm ADDC reg, reg mem, reg EA T EA T EA T EA T reg, mem EA T EA T EA T EA T reg, imm mem, imm EA T EA T EA T EA T acc, imm Notes. Not repeated. Repeated, n: number of transfer times (n ) 3. When IBRK = 4

41 µpd735 Table -9. Number of Clocks (3/) Number of Clocks Group Mnemonic Operands Byte Processing Word Processing On-chip RAM On-chip RAM On-chip RAM On-chip RAM Access Enable Access Disable Access Enable Access Disable Addition/ SB reg, reg subtraction mem, reg EA T EA T EA T EA T reg, mem EA T EA T EA T EA T reg, imm mem, imm EA T EA T EA T EA T acc, imm SBC reg, reg mem, reg EA T EA T EA T EA T reg, mem EA T EA T EA T EA T reg, imm mem, imm EA T EA T EA T EA T acc, imm BCD ADD4S Note + (7 + 3 T) n + (5 + 3 T) n operation SB4S Note + (7 + 3 T) n + (5 + 3 T) n CMP4S Note + (3 + 3 T) n + (3 + 3 T) n ROL4 reg8 7 7 mem8 EA T EA T ROR4 reg8 mem8 EA T EA + + T Increment / INC reg8 5 5 decrement mem8 EA + + T EA T EA T EA T reg6 DEC reg8 5 5 mem8 EA + + T EA T EA T EA T reg6 Multiplica- ML reg8 4 4 tion mem8 EA T EA T reg6 3 3 mem6 EA T EA T Note n: / of the number of BCD digits 4

42 µpd735 Table -9. Number of Clocks (4/) Number of Clocks Group Mnemonic Operands Byte Processing Word Processing On-chip RAM On-chip RAM On-chip RAM On-chip RAM Access Enable Access Disable Access Enable Access Disable Multiplica- ML reg8 3 to 4 3 to 4 tion mem8 EA T to EA T to EA T EA T reg6 39 to to 48 mem6 EA T to EA T to EA T EA T reg6, (reg6,) 39 to to 49 imm8 reg6, mem6, EA T to EA T to imm8 EA T EA T reg6, (reg6,) 4 to 5 4 to 5 imm6 reg6, mem6, EA T to EA T to imm6 EA T EA T nsigned DIV reg8 3 3 division mem8 EA T EA T reg mem6 EA T EA T Signed DIV reg8 46 to to 56 division mem8 EA T to EA T to EA T EA T reg6 54 to to 64 mem6 EA T to EA T to EA T EA T BCD ADJBA 7 7 adjustment ADJ4A 9 9 ADJBS 7 7 ADJ4S 9 9 Data CVTBD 9 9 conversion CVTDB CVTBW 3 3 CVTWL 8 8 Compare CMP reg, reg mem, reg EA T EA T EA T EA T reg, mem EA T EA T EA T EA T reg, imm mem, imm EA T EA T EA + + T EA + + T acc, imm

43 µpd735 Table -9. Number of Clocks (5/) Number of Clocks Group Mnemonic Operands Byte Processing Word Processing On-chip RAM On-chip RAM On-chip RAM On-chip RAM Access Enable Access Disable Access Enable Access Disable Comple NOT reg ment mem EA + + T EA T EA T EA + + T operation NEG reg mem EA + + T EA T EA T EA + + T Logical TEST reg, reg operation mem, reg/ EA T EA T EA + + T EA + + T reg, mem reg, imm mem, imm EA + + T EA + + T EA + + T EA + + T acc, imm AND reg, reg mem, reg EA T EA T EA T EA T reg, mem EA T EA T EA T EA T reg, imm mem, imm EA T EA T EA T EA T acc, imm OR reg, reg mem, reg EA T EA T EA T EA T reg, mem EA T EA T EA T EA T reg, imm mem, imm EA T EA T EA T EA T acc, imm XOR reg, reg mem, reg EA T EA T EA T EA T reg, mem EA T EA T EA T EA T reg, imm mem, imm EA T EA T EA T EA T acc, imm Bit TEST reg8, CL 7 7 manipula- mem8, CL EA + + T EA + + T tion reg6, CL 7 7 mem6, CL EA T EA T reg8, imm3 6 6 mem8, imm3 EA T EA T reg6, imm4 6 6 mem6, imm4 EA + + T EA + + T NOT reg8, CL 7 7 mem8, CL EA T EA + + T reg6, CL

44 µpd735 Table -9. Number of Clocks (6/) Number of Clocks Group Mnemonic Operands Byte Processing Word Processing On-chip RAM On-chip RAM On-chip RAM On-chip RAM Access Enable Access Disable Access Enable Access Disable Bit NOT mem6, CL EA T EA T manipula- reg8, imm3 6 6 tion mem8, imm3 EA + + T EA T reg6, imm4 6 6 mem6, imm4 EA T EA + + T NOT CY Bit CLR reg8, CL 8 8 manipula- mem8, CL EA T EA + + T tion reg6, CL 8 8 mem6, CL EA T EA T reg8, imm3 7 7 mem8, imm3 EA + + T EA T reg6, imm4 7 7 mem6, imm4 EA T EA + + T SET reg8, CL 7 7 mem8, CL EA T EA + + T reg6, CL 7 7 mem6, CL EA T EA T reg8, imm3 6 6 mem8, imm3 EA + + T EA T reg6, imm4 6 6 mem6, imm4 EA T EA + + T CLR CY DIR SET CY DIR Shift SHL reg, mem, EA T EA + + T EA T EA T reg, CL + n + n + n + n mem, CL EA T + n EA T + n EA T + n EA T + n Note reg, imm8 9 + n 9 + n 9 + n 9 + n mem, imm8 EA T + n EA + + T + n EA T + n EA T + n SHR reg, mem, EA T EA + + T EA T EA T Note n: Shift count 44

45 µpd735 Table -9. Number of Clocks (7/) Group Mnemonic Operands Number of Clocks Byte Processing Word Processing On-chip RAM On-chip RAM On-chip RAM On-chip RAM Access Enable Access Disable Access Enable Access Disable Shift SHR reg, CL + n + n + n + n Note mem, CL EA T + n EA T + n EA T + n EA T + n reg, imm8 9 + n 9 + n 9 + n 9 + n mem, imm8 EA T + n EA + + T + n EA T + n EA T + n SHRA reg, mem, EA T EA + + T EA T EA T reg, CL + n + n + n + n Note mem, CL EA T + n EA T + n EA T + n EA T + n reg, imm8 9 + n 9 + n 9 + n 9 + n mem, imm8 EA T + n EA + + T + n EA T + n EA T + n Rotate ROL reg, mem, EA T EA + + T EA T EA T reg, CL + n + n + n + n Note mem, CL EA T + n EA T + n EA T + n EA T + n reg, imm8 9 + n 9 + n 9 + n 9 + n mem, imm8 EA T + n EA + + T + n EA T + n EA T + n ROR reg, mem, EA T EA + + T EA T EA T reg, CL + n + n + n + n Note mem, CL EA T + n EA T + n EA T + n EA T + n reg, imm8 9 + n 9 + n 9 + n 9 + n mem, imm8 EA T + n EA + + T + n EA T + n EA T + n ROLC reg, mem, EA T EA + + T EA T EA T reg, CL + n + n + n + n Note mem, CL EA T + n EA T + n EA T + n EA T + n reg, imm8 9 + n 9 + n 9 + n 9 + n mem, imm8 EA T + n EA + + T + n EA T + n EA T + n RORC reg, mem, EA T EA + + T EA T EA T Note n: Shift count 45

46 µpd735 Table -9. Number of Clocks (8/) Number of Clocks Group Mnemonic Operands Byte Processing Word Processing On-chip RAM On-chip RAM On-chip RAM On-chip RAM Access Enable Access Disable Access Enable Access Disable Rotate RORC reg, CL + n + n + n + n mem, CL EA T + n EA T + n EA T + n EA T + n reg, imm8 9 + n 9 + n 9 + n 9 + n mem, imm8 EA T + n EA + + T + n EA T + n EA T + n Subroutine CALL near-proc + T 8 + T control regptr6 + T 8 + T memptr6 EA T EA T far-proc T T memptr3 EA T EA T RET + T + T pop-value + T + T T T pop-value T T Stack PSH mem6 EA T EA T manipula- reg6 + T 6 tion Note sreg + T 7 PSW + T 6 R T 5 imm8 3 + T 9 imm6 4 + T POP mem6 EA T EA + + T reg6 + T + T sreg 3 + T 3 + T PSW 4 + T 4 + T R T 58 PREPARE imm6, imm8 When imm8 =, 7 + T When imm8 =, T Note When imm8 = n, n >, (n ) + 4 T DISPOSE + T + T Notes. n: Shift count. Depth of procedure block (lexical level) 46

47 µpd735 Table -9. Number of Clocks (9/) Number of Clocks Group Mnemonic Operands Byte Processing Word Processing On-chip RAM On-chip RAM On-chip RAM On-chip RAM Access Enable Access Disable Access Enable Access Disable Branch BR near-label short-label regptr6 3 3 memptr6 EA T EA T far-label 5 5 memptr3 EA T EA T Conditional BV short-label 5/8 5/8 branch Note BNV short-label 5/8 5/8 BC/BL short-label 5/8 5/8 BNC/BNL short-label 5/8 5/8 BE/BZ short-label 5/8 5/8 BNE/BNZ short-label 5/8 5/8 BNH short-label 5/8 5/8 BH short-label 5/8 5/8 BN short-label 5/8 5/8 BP short-label 5/8 5/8 BPE short-label 5/8 5/8 BPO short-label 5/8 5/8 BLT short-label 5/8 5/8 BGE short-label 5/8 5/8 BLE short-label 5/8 5/8 BGT short-label 5/8 5/8 DBNZNE short-label 7/8 7/8 DBNZE short-label 7/8 7/8 DBNZ short-label 7/8 7/8 BCWZ short-label 5/8 5/8 BTCLR sfr, imm3, 9/ 9/ short-label Interrupt BRK T 43 + T imm8 ( 3) 56 + T 44 + T BRKV 55 + T 43 + T RETI T 37 + T RETRBI FINT CHKIND reg6, mem3 EA T EA T Note In the number of clocks, the value on the left side of / indicates the number of clocks when the condition is true, and the value on the right side indicates the number of clocks when the condition is false. 47