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1 CS6C Virtual Wrap-Up Processor Datapath Lecture pril 9, 999 Dave Patterson (http.cs.berkeley.edu/~patterson) www-inst.eecs.berkeley.edu/~cs6c/schedule.html Outline Review Virtual Introduce Datapath Top-Down asic Components and HW uilding locks dministrivia, Computers in the News Designing an rithmetic Logic Unit (LU) -bit LU 3-bit LU Conclusion cs 6C L datapath. cs 6C L datapath. Review / Virtual allows protected sharing of memory between processes with less swapping to disk, less fragmentation than always swap or base/bound 3 Problems: ) Not enough memory: Spatial Locality means small Working Set of pages OK ) TL to reduce performance cost of VM 3) Need more compact representation to reduce memory size cost of simple -level page table, especially for 64-bit address (See CS 6) cs 6C L datapath.3 Review /: Paging/Virtual User : Virtual Stack Heap Static Code cs 6C L datapath.4 Physical 64 M Table Table User : Virtual Stack Heap Static Code

2 Reduce Table Space: Multilevel Table Super No. Number Offset bits bits bits Super s map bytes (4 M) Each Super Table Entry in Super Table points to a separate (normal) Table which maps 4M into 4 4K ( ) pages 64 M -level Table Physical (Normal) Tables Super Table Virtual Stack Heap Static Save space by avoiding normal Table when no entry in Super Table cs 6C L datapath.5 cs 6C L datapath.6 Code natomy: 5 components of any Computer Lectures - Lectures 7-9 Computer Processor (active) Control ( brain ) Datapath ( brawn ) (passive) (where programs, data live when running) Devices Input Output Keyboard, Mouse Disk (where programs, data live when not running) Display, Printer Deriving the Datapath for a MIPS Processor Start with instruction subset in 3 instruction classes to derive datapath -reference: lw, sw rithmetic-logical: add, sub, and, or ranch: beq This subset illustrates shows most of the difficult steps in executing instructions cs 6C L datapath.7 cs 6C L datapath.8

3 Up to 5 Steps in Executing MIPS Subset ll instructions have common first two steps: ) Fetch Instruction and Increment PC ([PC]; PC = PC 4) ) Read or Registers (lw reads reg) Up to 5 Steps in Executing MIPS Subset 3rd step depends on instruction class 3) for -reference: Calculate ddress (ddress = Reg[rs]Imm) 3) for rithmetic-logical: Calculate Result (Result = Reg[rs] op Reg[rt], op is,-,&, ) 3) for ranch: Compare (equal = (Reg[rs] == Reg[rt])) cs 6C L datapath.9 cs 6C L datapath. Up to 5 Steps in Executing MIPS Subset 4th step depends on instruction class 4 ) for lw: Fetch Data in (Data = [ddress]) 4 ) for sw: [ddress] = Reg[rt] 4 ) for rithmetic-logical: Write Result (Reg[rd] = Result) 4) for ranch: Compare (if (Equal) PC = PC Imm) 5th step only for lw; rest are done What is needed for Datapath from 5 steps PC 3 Registers Unit to perform,-, &, Called an rithmetic-logic Unit, or LU for Instructions, Data Some miscellaneous registers to hold results between steps: ddress, Data, Equal 5) for lw: Write Result (Reg[rt] = Data) cs 6C L datapath. cs 6C L datapath.

4 Putting Together a Datapath for MIPS ddress Data In Data Out Data Out Instruction PC Registers LU ddress Data Out Data In How can have separate Instruction and Data? Data Step Step Step 3 (Step 4) Separate Caches for Instructions and for Data dministrivia Project 5: Due 4/4: design and implement a cache (in software) and plug into instruction simulator Next Readings: 5. (skip logic, clocking), 5., 4.5 (pages 3-36), 4.6 (pages 5-53, 64; skim 54-57), 4.7 (pages 65-68, 73; skim 69-7) How many lectures to cover:? 9th homework: Due Friday 4/6 7PM Exercises 7.35, 4.4 cs 6C L datapath.3 cs 6C L datapath.4 dministrivia: Courses for Telebears Take courses from great teachers! Top Faculty / Course (may teach soon) CS 5 logic design Katz 6. F9 CS 5 computer HW Patterson 6.7 S95 CS 64 compilers Rowe 6. S98 CS 69 SW engin. rewer 6. S98 CS 74 combinatorics Sinclair 6. F97 CS 86 data bases Wang 6. S98 EE 3 IC Devices Hu 6. S97 EE4 Digital IC Design Rabaey 6.3 S97 Computer (Technology) in the News Milestone on the Road to Ultrafast Computers, N.Y. Times, pril 6, 999 tunneling magnetic junction random access memory (tmj-ram) by IM researchers new kind of memory that could fundamentally alter computer design early in the next century... combine the best features of computer disks... and memory chips... (No hierarchy: fast as cache, dense as disk) a crucial step toward new class of materials and microelectronics-- "spintronics --based on ability to detect and control spins of electrons in ferromagnetic materials hkn.eecs/toplevel/coursesurveys.html cs 6C L datapath.5 cs 6C L datapath.6

5 Contructing the Datapath Components Instruction and Data are just caches, as seen before PC, 3 Registers built from hardware called registers which each store word Leaves LU for MIPS subset (For full MIPS instruction set, need multiply, divide: do that later) First describe Hardware uilding locks Hardware uilding locks (for LU) ND Gate Symbol Definition C C Inverter Symbol Definition C C OR Gate Symbol Definition C C Multiplexor Symbol Definition D D C C cs 6C L datapath.7 cs 6C L datapath.8 rithmetic Logic Unit (LU) What about ddition? MIPS LU is 3 bits wide Start with -bit LU, then connect 3 -bit LUs to form a 3-bit LU Since hardware building block includes an ND gate and an OR gate, and since ND and OR are two of the operations of the -bit LU, start here: C Definition C and or Example inary ddition: a: Carries b: Sum: Thus for any bit of addition: The inputs are a i, b i, i The outputs are Sum i, CarryOut i Note: i = CarryOut i cs 6C L datapath.9 cs 6C L datapath.

6 -it dder Symbol CarryOut Sum Full dder Definition CarryOut Sum Constructing Hardware to Match Definition Given any table of binary inputs for a binary output, programs can automatically connect a minimal number of ND gates, OR gates, and Inverters to produce the desired function Such programs generically called Computer ided Design, or CD cs 6C L datapath. cs 6C L datapath.3 Example: HW gates for CarryOut dd -bit dder to -bit LU Values of Inputs when CarryOut is : Gates for Sum left as exercise to Reader Gates for CarryOut signal: CarryOut CarryOut Definition C and or Now connect 3 -bit LUs together C cs 6C L datapath.4 cs 6C L datapath.5

7 3-bit LU Connect CarryOut i to i Connect 3 -bit LUs together Connect to all 3 bits of LU Does 3-bit nd, Or, dd cs 6C L datapath What about subtract?... C C C3 s comp. shortcut: Negation (Lecture 7) Invert every to and every to, then add to the result Sum of number and its inverted rep. ( one s complement ) must be... two... two = - ten Let x mean the inverted representation of x Then x x = - x x = x = -x Example: -4 to 4 to -4 x : two x : two : two () : two : two cs 6C L datapath.7 How Do Subtract? Suppose added input to -bit LU that gave the one s complement of What happens if set to in 3- bit LU? Sum = Then if select inverted (), Sum is = ( ) = (-) = - Therefore can do subtract as well as nd, Or, dd if modify -bit LU cs 6C L datapath.8 -bit LU with Subtract Support invert cs 6C L datapath.9 CarryOut C Definition invert C and and or or

8 3-bit LU 3-bit LU made from ND gates, OR gates, Inverters, Multiplexors Performs 3- bit ND, OR, ddition, Subtract ( s complement) cs 6C L datapath invert C C C3 nd in Conclusion.. / Virtual shares physical memory between several processes via paging Datapath components visible in the instruction set: PC, Registers,, LU Hardware building blocks: nd gate, Or gate, Inverter, Multiplexor uild dder via bstraction: decompose into -bit LUs Seen how a computers adds, subtracts Next: How a computer Multiplies, Divides cs 6C L datapath.3

CS61C : Machine Structures

CS 61C L path (1) insteecsberkeleyedu/~cs61c/su6 CS61C : Machine Structures Lecture # path natomy: 5 components of any Computer Personal Computer -7-25 This week Computer Processor ( brain ) path ( brawn