DFT for Regular Structures
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1 DFT for Regular Structures Regular Structure Fault Models RAM BIST Architectures ROM & PLA BIST Architectures Bypassing During BIST Benefits & Limitations C. Stroud 11/06 BIST for Regular Structures 1
2 Testing Regular Structures General model for a regular structure: two-dimensional array of identical cells densely packed cells surrounded by dedicated I/O blocks Functional operations: Read/Write: RAM, FIFO, Register file, CAM, multi-port RAMs Read only: ROM, PLA Regular structures require very specific test algorithms close pack cells sustain non-standard (non-classical) fault models D E C O D E Input Reg Cell Array Output Reg C. Stroud 11/06 BIST for Regular Structures 2
3 Classical & Non-Classical Faults Classical Faults: Stuck fault: cell contents sa0 or sa1 test each cell with both logic values Addressing fault: address decoder selects wrong address test all addresses with unique data Non-Classical Faults Transition fault: cell doesn t undergo 0 1 or 1 0 transition test both transitions Retention fault: cell looses its logic value after a certain time read data after a period of no activity (read or write) Destructive read: read operation changes the contents of a cell perform back-to-back reads of same cells Pattern-sensitivity: contents of cell affected by contents of other cells surround cell with opposite logic values in adjacent cells C. Stroud 11/06 BIST for Regular Structures 3
4 Example: Pattern Sensitive Faults in RAMs Test by surrounding cell with opposite logic values in adjacent cells cell adjacency dependent on physical layout and not addressing space Checker board pattern typically used 0 1 doesn t detect diagonally adjacency real checker board at cell & subcell level depends on physical layout Bit-bar i-1 Bit i-1 Bit i Bit-bar i Bit-bar i+1 Bit- i+1 Bit i-1 Bit-bar i-1 Bit i Bit-bar i Bit i+1 Bit-bar i+1 Example seen in RAMs at Bell Labs (1985) 0 in Cell i lets Cell i+1 to function normally 1 in Cell i forces Cell i+1 to 1 (or to 0) / C. Stroud 11/06 BIST for Regular Structures 4 1 0
5 Example RAM Test Algorithms C. Stroud 11/06 BIST for Regular Structures 5
6 Example RAM Test Algorithms Fault detection capabilities vary with test algorithm Longer test times for higher fault detection New algorithms developed for new faults/defects Trade-off test time with fault detection capabilities C. Stroud 11/06 BIST for Regular Structures 6
7 March LR Test for RAMs Detects neighborhood pattern sensitivity faults intra-word coupling faults bridging faults Notation = address downward = address upward = address either way w0 = write 0 r1 = read 1 Length of test = 16N N = number of address locations Word-oriented memories need Background Data Sequences (BDS) March Y w/o BDS March LR w/o BDS March LR with BDS Number of BDS = log 2 (K)+1, where K = data width March Y is simpler algorithm Length of test = 8N (w0); (r0, w1,r1); (r1,w0,r0); (r0); (w0); (r0, w1); (r1,w0,r0,r0, w1); (r1,w0); (r0,w1,r1,r1,w0); (r0); (w00); (r00, w11); (r11,w00,r00,r00, w11); (r11,w00); (r00,w11,r11,r11,w00); (r00,w01,w10,r10); (r10,w01,r01); (r01); C. Stroud 11/06 BIST for Regular Structures 7
8 BIST for Regular Structures Close packed cells prevent additional DFT logic in core area & performance penalties too great! different physical layouts require different test sequences Use parameterized generators for regular structures all structures then have same basic layout test development effort determines test algorithms test algorithms reusable for all structures produced by generator reusable solutions are cheaper design & test development cost shared by several projects implement BIST in I/O dedicated blocks preferably produced by generator implement full scan in I/O dedicated blocks allows independent test of embedded structure and general logic C. Stroud 11/06 BIST for Regular Structures 8
9 Example: BIST for RAMs From Lucent Technologies Incorporated in RAM generator Parameters: M address bits W words N bits/word BIST interface: BIST = start self-test BC = BIST complete BIST BFC BC BF BIST Control Address TPG BF = BIST flag (pass/fail) ORA BFC = BIST flag check comparator initiate test to check that BF is not stuck at 0 can be controlled by boundary scan using BRIC System Address Write Data Mux Mux RAM Data TPG System Data Out Mux C. Stroud 11/06 BIST for Regular Structures 9
10 Example: BIST for RAMs (cont) Lucent s Test Algorithm: 100% fault coverage for all faults considered 13N march test N = # address locations 1. W0 2. (R0, W1, W0, W1) 3. (R1, W0, R0, W1) 4. (R1, W0, W1, W0) 5. (R0, W1, R1, W0) 6. (W0,R0 ) 7. (W1,R1 ) Notation: W0 = Write 0 W1 = Write 1 R0 = Read 0 R1 = Read 1 W0 = write walking 0 W1 = write walking 1 R0 = read walking 0 R1 = read walking 1 N = number of words = access addresses 0 N = access addresses N 0 = access one address C. Stroud 11/06 BIST for Regular Structures 10
11 Example: BIST for RAMs (cont) Area overhead vs size for static RAM with BIST logic 13N march test 3N data retention test N = number of words Area Overhead (%) RAM Size (Kbytes) C. Stroud 11/06 BIST for Regular Structures 11
12 BIST for ROMs and PLAs Subset of test for RAMs ROMs/PLAs are read only Test time = 2N Reverse the direction of addressing to reduce fault masking in MISR C. Stroud 11/06 BIST for Regular Structures 12
13 Bypassing Regular Structures Embedded regular structure can be bypassed during BIST of general sequential logic Random type vectors for logic BIST to not test regular structures Regular structure tend to filter the random type vectors of logic BIST Two types of bypass techniques similar to test points C. Stroud 11/06 BIST for Regular Structures 13
14 Regular Structure BIST Summary Specific algorithms needed to detect non-classical faults associated with regular structures TPG for these algorithms typically implemented as FSM Benefits Good fault coverage without need for fault simulation Eliminates the problem of testing embedded structures Vertical testability for device through system-level testing Implementation can be (and has been) automated in payout generator for regular structure Limitations Extra area overhead Extra BIST functions to control Extra test sessions C. Stroud 11/06 BIST for Regular Structures 14
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