EE382M.20: System-on-Chip (SoC) Design

Transcription

1 EE82M.20: SystemonChip (SoC) Design Lecture 1 Resource Allocation and Binding Source: G. De Micheli, Integrated Systems Center, EPFL Synthesis and Optimization of Digital Circuits, McGraw Hill, Andreas Gerstlauer Electrical and Computer Engineering University of Texas at Austin gerstl@ece.utexas.edu Lecture 1: Outline Allocation, binding and sharing Problem formulation Functional unit sharing Flat graphs Hierarchical graphs Register sharing Multiport register files/memories Bus sharing Extensions Module selection Datapath and control synthesis EE82M.20: SoC Design, Lecture 1 G. De Micheli A. Gerstlauer 1

2 Allocation and Binding Allocation Number of resources available Binding Mapping of operations onto resources Sharing Manytoone relation Selection Type to implement each operation EE82M.20: SoC Design, Lecture 1 G. De Micheli Binding Limiting cases Dedicated resources One resource per operation No sharing One multitask resource ALU One resource per type Closely related to scheduling Optimum binding/sharing Minimize the resource usage Scheduled sequencing graphs Operation concurrency well defined Consider operation types independently Problem decomposition» Perform analysis for each resource type EE82M.20: SoC Design, Lecture 1 G. De Micheli 2018 A. Gerstlauer 2

3 ILP Formulation of Binding Boolean variable b ir Operation i bound to resource r r b ir = 1 for all operations i Boolean variables x il Operation i scheduled to start at step l i b ir m=ldi1..l x im 1 for all steps l and resources r EE82M.20: SoC Design, Lecture 1 G. De Micheli Compatibly and Conflicts Operation compatibility: Same type Non concurrent t1 x=ab y=cd 1 2 t2 s=xy t=xy t z=at Compatibility graph: Vertices: operations Edges: compatibility relation Conflict graph: Complement of compatibility graph Compatibility graph 1 2 Conflict graph 1 2 EE82M.20: SoC Design, Lecture 1 G. De Micheli A. Gerstlauer

4 Compatibility and Conflicts Compatibility graph clique partitioning Partition the graph into a minimum number of cliques Find clique cover number k ( G ) Conflict graph coloring Color the vertices by a minimum number of colors. Find chromatic number х ( G_ ) NPcomplete problems Heuristic algorithms EE82M.20: SoC Design, Lecture 1 G. De Micheli 7 Compatibility and Conflict Example t1 x=ab y=cd 1 2 t2 s=xy t=xy t z=at Conflict 1 2 Compatibility 1 2 Coloring Partitioning ALU1: 1,, ALU2: 2, EE82M.20: SoC Design, Lecture 1 G. De Micheli A. Gerstlauer

5 Perfect Graphs Comparability graph Graph G (V, E ) has an orientation G ( V, F ) with the transitive property (v i, v j ) є F and (v j, v k ) є F (v i, v k ) є F Interval graph Vertices correspond to intervals Edges correspond to interval intersection Subset of chordal graphs Every loop with more than three edges has a chord (edge that is not part of the cycle but connects two nodes in the loop) EE82M.20: SoC Design, Lecture 1 G. De Micheli 9 Data Flow Graphs (DFGs) The compatibility/conflict graphs have special properties Compatibility Comparability graph Conflict Interval graph Polynomial time solutions Golumbic s algorithm for partitioning of compatibility graphs Leftedge algorithm for coloring of interval graphs EE82M.20: SoC Design, Lecture 1 G. De Micheli A. Gerstlauer

6 DFG Example: Comparability Graphs NOP0 TIME TIME < TIME 7 8 TIME 9 n NOP EE82M.20: SoC Design, Lecture 1 G. De Micheli 11 DFG Example: Interval Graphs NOP0 TIME TIME < 6 11 TIME TIME n 9 9 NOP EE82M.20: SoC Design, Lecture 1 G. De Micheli A. Gerstlauer 6

7 LeftEdge Algorithm Input: Set of intervals with left and right edge A set of colors (initially one color) Rationale Sort intervals in a list by left edge Assign non overlapping intervals to first color using the list When possible intervals are exhausted, increase color counter and repeat EE82M.20: SoC Design, Lecture 1 G. De Micheli 1 LeftEdge Algorithm LEFT_EDGE(I) { Sort elements of I in a list L in ascending order of l i ; c = 0; while (some interval has not been colored) do { S = Ø; r = 0; while ( exists s є L such that l s > r) do { s = First element in the list L with l s > r; S = S U {s}; r = r s ; Delete s from L; } c = c 1; Label elements of S with color c; } } EE82M.20: SoC Design, Lecture 1 G. De Micheli A. Gerstlauer 7

8 LeftEdge Example Conflict graph Intervals Colored conflict graph Coloring EE82M.20: SoC Design, Lecture 1 G. De Micheli 1 Lecture 17: Outline Allocation, binding and sharing Problem formulation Functional unit sharing Flat graphs Hierarchical graphs Register sharing Multiport register files/memories Bus sharing Extensions Module selection Datapath and control synthesis EE82M.20: SoC Design, Lecture 1 G. De Micheli A. Gerstlauer 8

9 Hierarchical Sequencing Graphs (CDFGs) Hierarchical conflict/compatibility graphs Easy to compute Prevent sharing across hierarchy Flatten hierarchy Bigger graphs Destroy nice properties EE82M.20: SoC Design, Lecture 1 G. De Micheli 17 Hierarchical Graph Example Calls of submodels a TIME 1 TIME 2 TIME TIME TIME TIME 6 TIME 7 a a 2 a a a 2 a 2 Sequencing Graph Execution intervals Conflict graph Not perfect graphs any more Intractable, use of heuristics EE82M.20: SoC Design, Lecture 1 G. De Micheli A. Gerstlauer 9

10 Hierarchical Graph Example Branching constructs TIME 1 a NOP NOP a a TIME 2 BR c d c d c d TIME TIME b NOP NOP b b Sequencing Graph Execution intervals Conflict graph Not perfect graphs any more Intractable, use of heuristics EE82M.20: SoC Design, Lecture 1 G. De Micheli 19 Lecture 17: Outline Allocation, binding and sharing Problem formulation Functional unit sharing Flat graphs Hierarchical graphs Register sharing Multiport register files/memories Bus sharing Extensions Module selection Datapath and control synthesis EE82M.20: SoC Design, Lecture 1 G. De Micheli A. Gerstlauer 10

11 Storage Elements Registers Hold data across cycles Data: value of a variable Variable lifetime in scheduled graph Can be reused (shared) across variables Memory blocks, register files Limited number of read/write ports EE82M.20: SoC Design, Lecture 1 R. Gupta G. De Micheli 21 Register Binding Problem Given a schedule Lifetime intervals for variables Lifetime overlaps Conflict graph (interval graph) Vertices variables Edges overlaps Interval graph Compatibility graph (comparability graph) Complement of conflict graph EE82M.20: SoC Design, Lecture 1 G. De Micheli A. Gerstlauer 11

12 Register Sharing Given Variable lifetime conflict graph Find Minimum number of registers storing all the variables Key point Interval graph Leftedge algorithm (polynomialtime complexity) EE82M.20: SoC Design, Lecture 1 G. De Micheli 2 Register Sharing Example TIME 1 TIME 2 TIME TIME z1 1 2 z z2 z z z6 7 6 z1 z z z2 z z6 z1 z z z2 z z6 Sequencing graph Variable lifetimes Conflict graph EE82M.20: SoC Design, Lecture 1 G. De Micheli A. Gerstlauer 12

13 Register Sharing in Loops Iterative conflicts through loopcarried dependencies Preserve values across iterations Circulararc conflict graph Coloring is intractable Hierarchical graphs General conflict graphs Coloring is intractable Heuristic algorithms EE82M.20: SoC Design, Lecture 1 G. De Micheli 2 Loop Example u x u dx u y x y u dx x dx x TIME TIME 2 TIME TIME z1 z z z2 z z6 6 dx 7 y z7 8 9 < c a 11 z1 z z z2 z z6 u z7 u y y x u y Sequencing graph Variable lifetimes EE82M.20: SoC Design, Lecture 1 G. De Micheli A. Gerstlauer 1

14 Loop Variable Lifetimes z1 z2 u x 1 z1 z2 u y 2 z z x z z y z7 z6 z z z7 z6 Variable lifetimes Circulararc conflict graph EE82M.20: SoC Design, Lecture 1 G. De Micheli 27 MultiPort Memory Binding Find minimum number of ports to access the required number of variables Variables use the same port Port compatibility/conflict Similar to resource binding Variables can use any port Decision variable x il id TRUE when variable i is accessed is step l Optimum: max 1 l λ 1 ( i=1..nvar x il ) EE82M.20: SoC Design, Lecture 1 G. De Micheli A. Gerstlauer 1

15 Dual MultiportMemory Binding Problem Find max number of variables to be stored through a fixed number of ports a Boolean variables { b i, i = 1, 2,, n var }: Variable i with b i =1 will be stored in register file maximize i=1..nvar b i such that i=1..nvar b i x il a l = 1,2,,λ 1 EE82M.20: SoC Design, Lecture 1 G. De Micheli 29 MultiPort Memory Binding Example Time step 1 : r = r 1 r 2 ; r 12 = r 1 Time step 2 : r = r r ; r 7 = r r 6 ; r 1 = r Time step : r 8 = r r ; r 9 = r 1 r 7 ; r 11 = r 10 / r Time step : r 1 = r 11 & r 8 ; r 1 = r 12 r 9 Time step : r 1 = r 11 ; r 2 = r 1 1 max i=1 b i such that b 1 b 2 b b 12 a b b b b 6 b 7 b 1 a b 1 b b b 7 b 8 b 9 b 10 b 11 a b 8 b 9 b 11 b 12 b 1 b 1 a b 1 b 2 b 1 b 1 a One port a = 1: { b 2, b, b 8 } nonzero variables stored: v 2, v, v 8 Two ports a = 2: 6 variables stored: v 2, v, v, v 10, v 12, v 1 Three ports a = : 9 variables stored: v 1, v 2, v, v 6, v 8, v 10, v 12, v 1 EE82M.20: SoC Design, Lecture 1 G. De Micheli A. Gerstlauer 1

16 Lecture 17: Outline Allocation, binding and sharing Problem formulation Functional unit sharing Flat graphs Hierarchical graphs Register sharing Multiport register files/memories Bus sharing Extensions Module selection Datapath and control synthesis EE82M.20: SoC Design, Lecture 1 G. De Micheli 1 Bus Sharing and Binding Find the minimum number of busses to accommodate all data transfer Find the maximum number of data transfers for a fixed number of busses Similar to memory binding problem ILP formulation or heuristic algorithms EE82M.20: SoC Design, Lecture 1 G. De Micheli A. Gerstlauer 16

17 Bus Sharing Example TIME 1 TIME 2 TIME TIME z1 1 2 z z2 z z z6 7 6 z1 z z z2 z z6 z1 z z z2 z z6 Sequencing graph Connection usage Conflict graph One bus: variables can be transferred Two busses: All variables can be transferred EE82M.20: SoC Design, Lecture 1 G. De Micheli Lecture 17: Outline Allocation, binding and sharing Problem formulation Functional unit sharing Flat graphs Hierarchical graphs Register sharing Multiport register files/memories Bus sharing Extensions Module selection Datapath and control synthesis EE82M.20: SoC Design, Lecture 1 G. De Micheli 2018 A. Gerstlauer 17

18 Module Selection Problem Extension of resource sharing Library of resources More than one resource per type Example Ripplecarry adder Carry lookahead adder Resource modeling Resource subtypes with ( area, delay ) parameters EE82M.20: SoC Design, Lecture 1 G. De Micheli Module Selection Solutions ILP formulation Decision variables Select resource subtype Determine ( area, delay ) Heuristic algorithm Determine minimum latency with fastest resource subtypes Recover area by using slower resources on noncritical paths EE82M.20: SoC Design, Lecture 1 G. De Micheli A. Gerstlauer 18

19 Module Selection Example TIME 1 (1,1) 1 NOP 0 (1,2) 6 (2,1) Slow multipliers save area TIME TIME 8 11 < TIME 7 TIME (2,2) 9 n NOP Multipliers with ( Area, delay ) = (,1 ) and ( 2,2 ) Latency bound of EE82M.20: SoC Design, Lecture 1 G. De Micheli 7 Module Selection Example 2 NOP 0 TIME 1 (1,1) 1 2 (1,2) (2,1) 10 TIME < TIME 7 8 TIME (2,2) 9 n NOP Latency bound of Fast multipliers for { v 1, v 2, v } Slower multiplier can be used elsewhere Less sharing Minimumlatency design uses fast multipliers only Impossible to use slow multipliers EE82M.20: SoC Design, Lecture 1 G. De Micheli A. Gerstlauer 19

20 Lecture 17: Outline Allocation, binding and sharing Problem formulation Functional unit sharing Flat graphs Hierarchical graphs Register sharing Multiport register files/memories Bus sharing Extensions Module selection Datapath and control synthesis EE82M.20: SoC Design, Lecture 1 G. De Micheli 9 Data Path Synthesis Applied after resource binding Connectivity synthesis Connection of resources to multiplexers, busses and registers Control unit interface I/O ports Physical data path synthesis Specific techniques for regular datapath design Regularity extraction EE82M.20: SoC Design, Lecture 1 G. De Micheli A. Gerstlauer 20

21 Data Path Synthesis Example REGISTERS a dx x y u r1 r2 enable Mux control ALU ALU control (,,<) c DATAPATH CONTROLUNIT EE82M.20: SoC Design, Lecture 1 G. De Micheli 1 Control Synthesis Synthesis of the control unit Sequencer Logic model Synchronous FSM Physical implementation Hardwired or distributed FSM Microcode EE82M.20: SoC Design, Lecture 1 G. De Micheli A. Gerstlauer 21

22 Control Synthesis Example NOP 0 TIME TIME 2 TIME 7 9 < 11 TIME reset reset NOP n 1,2,6,8,10 reset,7,9,11 s 1 s 2 reset reset s reset s EE82M.20: SoC Design, Lecture 1 G. De Micheli Lecture 17: Summary Resource sharing is reducible to vertex coloring or to clique covering Simple for flat graphs Intractable, but still easy in practice, for other graphs Resource sharing has several extensions Module selection Data path design and control synthesis are conceptually simple but still important steps Generated data path is an interconnection of blocks Control is one or more finitestate machines EE82M.20: SoC Design, Lecture 1 G. De Micheli 2018 A. Gerstlauer 22