UNIVERSITY OF MANITOBA DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING. Term Test #2 Solution ECE 3610 MICROPROCESSING SYSTEMS

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1 ECE 3610 Test 2 Solution 1 of 7 PRINT LAST NAME: STUDENT NUMBER PRINT FIRST NAME: UNIVERSITY OF MANITOBA DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DATE: Feb. 28, 11; TIME: 6:00-8:00 P.M. Term Test #2 Solution ECE 3610 MICROPROCESSING SYSTEMS This is an open book test. You may bring the course book, and other notes. However, all material must be bound in one container; loose leaf is not allowed. Electronic communications devices are strictly prohibited. Calculators are not allowed. Answer all questions in the space provided.

2 ECE 3610 Test 2 Solution 2 of 7 1. The following program is a multiple precision unsigned addition program, much like the one you worked on in the lab. The program code and data are to be stored in the inclusive range $4000 to $4FFF. There are no other memory chips available. Analyze this program, and answer the following questions based on the given program: [1.1] Assemble the source code. Place the machine code in the Machine Code column, and fill out the Address column. In the Mode column, identify the addressing mode used by the instruction. Place the machine code starting at memory location 4100 (as indicated). [1.2] How many locations are available to store the first number? 7E = 7F = 127 [1.3] How many locations are available to store the second number? FB-7F + 1 = 7D = 125 [1.4] How many locations are available to store the result? FE-FC + 1 = 03 = 3 [1.5] What is the maximum precision this program can process? 2 [1.6] What is the purpose of location $40FF? Stores the precision Line Address Machine Code Assembly Language Mode 4000 Num1 MSB 407E 407F Num1 LSB Num2 MSB 40FB 40FC 40FD 40FE 40FF Num2 MSB Result MSB Result LSB precision C F6 40 FF LDAB $40FF EXT CE LDX #$4000 IMM A6 7E NEXT LDAA $7E,X IND,X A9 FB ADCA $FB,X IND,X 8 410B A7 FE STAA $FE,X IND,X D 09 DEX INH E 5A DECB INH F 26 F6 BNE NEXT REL ADCA #$00 IMM A7 FE STAA $FE,X IND,X FE HERE BRA HERE REL

3 ECE 3610 Test 2 Solution 3 of 7 [1.7] The objective of this next set of questions is to modify the above program to perform multiple precision signed addition. Use the following steps: [1.7.1] Perform the following addition of SIGNED numbers. Use three bytes to represent the result of each addition. 7FFE 7FFF FFFE 7FFF FFFF FFFF 0001 FFFF 00 7FFF 00 7FFE FFFFFD FF 7FFF

4 ECE 3610 Test 2 Solution 4 of 7 [1.7.2] Create a flow chart, which uses method 1, as discussed in class, and repeated here: If overflow is false, then sign extend the result. In more words, prepend $00 to the n-byte result if the n-byte result is positive; and prepend $FF to the n-byte result if the n-byte result is negative. If overflow is true, and the MSBit of the n-byte result is 1, then prepend $00 to the n-byte result. If overflow is true, and the MSBit of the n-byte result is 0, then prepend $FF to the n-byte result. Start A N V N 1 A FF 0 (FF,X) A End [1.7.3] Translate your flow chart to assembly language. Start your program at line 13. You may assume that instructions from lines 8-12, inclusive, do not affect the V-bits of the CCR. Line Assembly Language 1 CLC 2 3 LDAB $40FF 4 LDX #$ NEXT LDAA $7E,X 7 ADCA $FC,X 8 STAA $FF,X 9 10 DEX 11 DECB 12 BNE NEXT 13 START BVS V=1 V=0 BMI N=1 N=0 CLRA BRA WRITE N=1 LDAA #$FF BRA WRITE V=1 BMI N=1 N=0 LDAA #$FF BRA WRITE N=1 CLRA WRITE STAA $FF,X Line Assembly Language (Continued) DONE BRA DONE Note: I assumed that lines 8-12, inclusive, do not affect the N-bit of the CCR, as well.

5 ECE 3610 Test 2 Solution 5 of 7 2 Answer the following questions regarding the program given below. The program is to be stored in memory at location $4100. [2.1] In the space provided, list the contents of the stack and the value of the stack pointer after line 7 has run twice. [2.2] How many times does the Again loop run? 7E times = 126 times. [2.3] How many times does the s_main loop run? If your answer is not infinite times, then explain your answer. Once. The code replaces LDS #$4102 with JMP $4100, and ths make the program continually execute th new instruction JMP $4100. LINE REGISTER CONTENTS STACK ADDRESS 1 s_main LDS #$ LDAA #$7E 3 LDX #$ Again PSHX 5 PSHA 6 DECA 7 BNE Again 8 PULX 9 PULA 10 NOP BRA s_main 40F7 7B 40F F FA 7C 40FB 41 40FC 00 40FD 7D 40FE 41 40FF E CONTENTS

6 ECE 3610 Test 2 Solution 6 of 7 3 Complete the timing diagram for instruction PULA. You might not need four clock cycles OP_1 1.1 MAR PC -OP_3 3.1 MAR SP 1.2 PC PC DBUS = Mem(ABUS), MUX0 DBUS_MDR, MDR_WRITE, MUX1_OCR 1.4 OCR DBUS 3.3 DBUS = Mem(ABUS), MUX0 DBUS_MDR, MDR_WRITE, MUX1_MUX2&ALU, MUX2_MUX1_ACCA, ALU_PASS_B 3.4 CCR_LOAD, ACCA_LOAD -OP_ SP SP OP_ t

7 ECE 3610 Test 2 Solution 7 of 7 4 Write Verilog code and use the DE2 board to implement a digital data separator. A clock running at 50 MHz is available at pin called CLK_50. Every positive edge of CLK_50, 9-bit data will be delivered to the FPGA at pins called DD[8:0]. Your task is to separate the data on DD[7:0] based on the control input DD[8]. If DD[8] is a 1, then the byte on DD[7:0] shall be written to memory 1; If DD[8] is a 0, then the byte on DD[7:0] shall be written to memory 2; If DD[8] is a z, then the byte on DD[7:0] shall be dropped, i.e., ignored. The memories should have size 256x8. If a memory becomes full, then the first location should be reused, overwriting the previous contents. In other words, implement a circular memory. CLK_50 DD[8] Separator Memory 1 DD[7] DD[0] New data is presented each +ve edge of CLK_50. Memory 2 module TopLevelDesignEntity (input [8:0] DD, input CLK_50); reg [7:0] ram1 [255:0]; //My memory 1 declaration reg [7:0] ram2 [255:0]; //My memory 2 declaration reg [7:0] ram1address, ram2address; // memory addresses (posedge CLK_50) case (DD[8]) 1: begin ram1[ram1address] <= DD[7:0]; ram1address <= ram1address + 1; end 0: begin ram2[ram2address] <= DD[7:0]; ram2address <= ram2address + 1; end endcase endmodule