UNIVERSITY OF MANITOBA DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING. Term Test #1 ECE 3610 MICROPROCESSING SYSTEMS

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1 ECE 3610 Test 1 1 of 8 PRINT LAST NAME: STUDENT NUMBER PRINT FIRST NAME: UNIVERSITY OF MANITOBA DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DATE: Feb. 2015; TIME: 6:00-8:00 P.M. Term Test #1 ECE 3610 MICROPROCESSING SYSTEMS This is a closed book test. Electronic devices (includes calculators) are not allowed. Answer all questions in the space provided.

2 ECE 3610 Test 1 2 of 8 1. You are given a data processor shown in Fig. 1; the ALU function table given in Table 1; the DPUMUX control in Table 2, and the AGUMUX control in Table 3. This question asks you to design a sequence of micro-operations to implement the LSL EXT instruction. The purpose of this instruction is to shift the bits in a memory location by one position to the left, and store the result in the next memory location. For example, if the memory location 1110 has the value 0011, the result of the LSL 1110 instruction would be that the next location 1111 would contain Note: a design goal is to use the least number of micro-operations, and your solution will be graded accordingly. Note: one or more aspects of this problem may be incompletely specified, and, if so, then it is your responsibility to identify and clarify them. State your assumptions. 8 [1.1] Write down each micro-operation of your design in the following table. Describe each micro-operation in a clear English statement, and choose an abbreviation to name the microoperation. μ-operation Abbreviation Fetch Get_Address Load_B Shift and Store μ-operation Description Fetch the opcode of the instruction and place it into the OCR. This opcode is the first nibble of the instruction. Get the address of where to shift, and place it into the THR. This address is the second nibble of the instruction. Load register B with the data to be shifted, and use THR as the address. Increment THR in this cycle. Shift the data and store to the incremented address in the THR. 15 [1.2] Specify the control vector for each one of your micro-operations in the following table. μ-operation AMUX PC THR THR MAR MEM MEM Abbreviation S INC INC OE A B OCR S2 S1 S0 D_S1 D_S0 Fetch Get_Addr Load_B Shift_Store / Table 1: ALU function table for Q1. S2 S1 S0 ALU FUNCTION ZZZZ (High Impedance) ASIDE + BSIDE ASIDE - BSIDE PASS B PASS A SHIFT BSIDE BY ONE BIT TO THE LEFT

3 ECE 3610 Test 1 3 of 8 2 Mark 2 Mark Table 2: DPUMUX Control. D_S1 D_S0 In Out 1 1 x Hi-Z 0 1 RBUS DBUS 1 0 DBUS A 0 0 DBUS B D_S1 D_S0 DATA PATH UNIT A_ A B RBUS ADDRESS GENERATOR UNIT PC_INC INC AGUMUX AMUX_S PC THR WRT_CLK INC_CLK MAR INC THR_ MAR_ ABUS THR_INC ALU DPUMUX Table 3: AGUMUX Control. AMUX_S In Out 0 THR MAR 1 PC MAR B_ DBUS Fig. 1. A tiny data processor. [1.3] Encode the instruction ( shift the bits in memory location 1110 by one position to the left, and store the result in the next memory location ) in binary and write your answer in the memory shown above in Fig. 1. Use opcode [1.] What value should be in the PC prior to executing your instruction? 0000 [1.5] Determine the clock signal name that should be input to each of the devices in Fig. 1 that require a clock signal, and write your answers in the appropriate places in Fig. 1. S2 S1 S0 MEMORY (16X) HUMAN CONTROL UNIT AMUX_S D_S1 D_S0 A_ B_ S2 S1 THR_INC S0 OCR_ PC_INC MAR_ MEM_OE MEM_ THR_ OCR OE MEM_OE OCR_ MEM_ CBUS

4 ECE 3610 Test 1 of 8 16 [1.6] Complete the timing diagram below and show the following: (1) A name for each clock period that indicates the purpose of it; (2) What is transferred into the MAR and when; (3) When the program counter/thr is incremented; () The path data takes and when; and (5) when the destination register or memory latches the result. You may need more or less periods of the clock than given below. Fetch Get_Address Load_B Shift_Store μ-op_1 μ-op_2 μ-op_3 μ-op_ Data settling time Address settling time μ-op_1 1.1 MAR PC μ-op_3 3.1 MAR THR 1.2 PC PC THR THR DBUS = Mem(ABUS) 3.3 DPUMUX_DBUS_B 1. OCR DBUS 3. B DBUS μ-op_2 2.1 MAR PC μ-op_.1 MAR THR 2.2 PC PC DBUS = Mem(ABUS).3 DPUMUX_RBUS_DBUS, ALU_SHIFTB 2. THR DBUS. MEM(THR) DBUS

5 ECE 3610 Test 1 5 of This question asks you to write two generic Verilog modules for the TOC of Q1. (a) Write a generic Verilog module to describe the AGUMUX; and (b) Write a generic Verilog module to describe the THR. Write both modules generically. Do not instantiate the modules. Do not instantiate the modules. The Fig. 2 reproduces the diagrams for the AGUMUX and THR, for convenience. Note: one or more aspects of the given circuit may be incompletely specified, and, it is your responsibility to identify and clarify them. State your assumptions. Use opposite page if required. FPGA CHIP Table : AGUMUX Control. PC AMUX_S In Out AGUMUX THR 0 THR MAR 1 PC MAR MAR THR THR_ DBUS THR_WRITE_CLOCK AMUX_S (a) (b) INC THR_INC_CLOCK THR_INC Fig. 2. Circuit diagrams for Question Q2. (a) Write a generic Verilog module to describe the AGUMUX; and (b) Write a generic Verilog module to describe the THR. Note: these modules would be used in a description of the TOC of Q1. (a) Generic AGUMUX: module AGUmux (in1, in2, S, ou1); input [3:0] in1, in2; input S; output reg [3:0] ou1; (in1, in2, S) case (S) 0: ou1 = in1; 1: ou1 = in2; endcase endmodule (b) Generic -bit Register with increment: Acceptable design (or any variation) for the test: module reg_inc (D, Rn_W, INCn, I_CLK, W_CLK, Q); input [3:0] D; input Rn_W, INCn, W_CLK, I_CLK; output reg [3:0] Q; (negedge I_CLK or negedge W_CLK) begin if (I_CLK==0) if(incn==0) Q <= Q + 1; else Q <= Q; else if(rn_w==1) Q <= D; else Q = Q; end

6 ECE 3610 Test 1 6 of 8 endmodule Design that works with the Quartus compiler: module reg_inc (D, Rn_W, INCn, I_CLK, W_CLK, Q); input [3:0] D; input Rn_W, INCn, W_CLK, I_CLK; output reg [3:0] Q; wire clk; assign clk = I_CLK&~INCn W_CLK&Rn_W; (negedge clk) case ({INCn, Rn_W}) 2'b00: Q <= Q + 1; 2'b01: Q <= Q; 2'b10: Q <= Q; 2'b11: Q <= D; endcase endmodule

7 ECE 3610 Test 1 7 of The circuit of Fig. 3 shows an internal representation of an FPGA chip (I/O pins, switch matrix, and logic blocks). Show how the Boolean function F = x 1 x 2 + x 3 x 1 may be implemented in this FPGA ( x y means x XOR y). Label the I/O pins with the names of the inputs and outputs of the equation; connect the appropriate wires in the switch matrix by placing an x at the connection point; and specify the inputs, outputs, and values of the look-up-table (LUT) of each logic block. Give a truth table, that shows the inputs and the output, for each of your logic blocks. A constraint is that a logic block can have a maximum of two inputs and a maximum of one output. F x 1 X 2 X 1 F X 3 X 1 F x 2 F 1 F 2 F x 3 Fig. 3. Circuit for Q3.

8 ECE 3610 Test 1 8 of Answer the following questions with either TRUE or FALSE. These questions refer to the microprocessor shown in the animation software. [.1] The first byte of the LDAA EXT instruction is loaded into the THR LB on the negative edge of φ2. [.2] The second byte of the LDAA EXT instruction is loaded into the OCR on the negative edge of φ2. [.3] The third byte of the LDAA EXT instruction is loaded into the ACCA on the negative edge of φ2. [.] If an instruction requires 5 cycles to execute and 2 bytes to store, then the PC will increment 2 times during the execution of this instruction. [.5] The NZVC bits in the CCR are updated during the fetch micro-operation of an instruction, because this is when the CCU learns what operation is to be done. Place Answer in this column True [.6] Two different addresses may be placed on the ABUS at the same time, so that the μp can read two bytes from the memory at the same time. This would double its throughput. [.7] If the 8-bit number 1xxxxxxx is subtracted from 0xxxxxxx, then the hardware would make C=1. [.8] If the 8-bit number 1xxxxxxx is subtracted from 0xxxxxxx, and the ALU result is 1xxxxxxx, then the hardware would make V=1. [.9] If the 8-bit number 1xxxxxxx is added to 0xxxxxxx, then the hardware would make C=1 or C=0, depending on the actual values of the numbers being added. True True True [.10] If the 8-bit number 1xxxxxxx is added to 0xxxxxxx, then the hardware would make V=1 or V=0, depending on the actual values of the numbers being added.

UNIVERSITY OF MANITOBA DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING. Term Test #2 Solution ECE 3610 MICROPROCESSING SYSTEMS

ECE 3610 Test 2 Solution 1 of 7 PRINT LAST NAME: STUDENT NUMBER PRINT FIRST NAME: UNIVERSITY OF MANITOBA DEPARTMENT OF ELECTRICAL AND COMPUTER ENGINEERING DATE: Feb. 28, 11; TIME: 6:00-8:00 P.M. Term Test