CS 273 Machine Programming and Organization Lecture Notes

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1 CS 273 Machine Programming and Organization Lecture Notes Joe Song Department of Computer Science NMSU, Spring 2009 March 9, 2009 Each lecture lasts 75 minutes Lecture 1 Announcements 1 fee payment for the kit 2 go over the syllabus; Course materials Decimal numbers: Example: = Base: 10 Digits: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9 Decimal point: To the left: 10 raised to a positive number; To the right: 10 raised to a negative number; 1

2 Octal numbers: Generalization of base to 8: Digits: 0, 1, 2, 3, 4, 5, 6, 7 (NO 8, 9) Reading an octal number: 314 octal three hundred and fourteen Examples: = = = = = = 77 INVALID! = = Hexadecimal numbers: Generalization of base to 16: Digits: 0, 1, 2, 3, 4, 5, 6, 7, 8, 9, A, B, C, D, E, F Reading a hexadecimal number: 314 hexadecimal/hex three hundred and fourteen C35F C three five F Examples: = = C35F 16 = C F = = = = = Binary numbers: 2

3 Generalization of base to 2: Digits: 0, 1 Reading a binary number: 1011 one zero one one Examples: Binary-to-decimal conversion = = = = = = 4 10 Binary-to-octal conversion Binary-to-hexadecimal conversion = 1, 001, 101, 111 = = 10, 0110, 1111 = 25F 16 3

4 Lecture 2 Announcements: Quiz on next Tuesday 1/27 Readings: 11, 14, 15 Two s complement signed numbers a sign bit the left-most bit 0 positive; 1 negative a numerical value the rest bits size restriction: Only two s complement signed numbers with the same number of bits can be added Positive number examples Negative numbers = = How to negate a positive number? Step 1 Complement ALL the bits of the positive number, including the sign bit; Step 2 Add one to the result = = = 5 10 Verification: = = = = Verification = 0 The negation rule also applies to negative numbers = = = overflow 4

5 Two positive numbers add up to a negative number! Wrong! Two negative numbers add up to a positive number! Wrong! Two s complement overflow error positive zero = = = 0 10 most negative number = = most positive number = subtraction 1 perform an actual subtraction perform a negation of subtrahend and then an addition Sign extension 8-bit to 16 bit conversion: repeat the sign bit enough time to achieve the number of bits needed 5

6 = = = = Reason for the two s complement numbers: Hardware can treat the sign bits as regular bits and can add or subtract them! 6

7 Lecture 3 Announcements: HW#1: 1-1(a)(d)(e)(i), 1-2(b)(c)(g), 1-3(f)(i), 1-7, 1-9, 1-21, 1-22, 1-26 Due: September 7, 2006 (Thursday) Binary-coded decimal numbers binary code for decimal digits : 4 bits for each digit from 0 to 9 examples = BCD addition C = BCD Correction: add 6 to each digit greater than C AA

8 68HC11 Computer Operation The Programming Model is composed of microprocessor registers: A 0 7 B 0 8-bit accumulators A & B D 0 16-bit double accumulator D X 0 index register X Y 0 index register Y SP 0 Stack Pointer PC 0 Program Counter S X H I N Z V C Condition code register Memory model is composed of memory registers: 7 0 +===== C239 B C23A C C23B

9 FFFF 22 +=====+ Address 16-bits Content of each address 8 bits The total memory register occupies bits or 2 16 = 64K bytes, which can be addressed directly by the 68HC11 An instruction format C100 B6 <- Op code of LDAA C101 C <- Address of data C C <- Data number LDAA Load Accumulator A instruction B6 specifies the operation (LDAA) to be performed by the processor, called operation code or op code for short C200 address of the data 44 data in the memory register with at the address C200 After the instruction, the processor register accumulator A has the data 44 The microprocessor model: PC IR

10 A B Memory registers: Accumulators : a general-purpose register in a microprocessor that holds a data number It can hold the result of an instruction; It can also hold a number to be operated on by an instruction Program counter : Holds the address of the next instruction to be fetched from memory Instruction register : Contains the instruction fetched from memory register Usually not shown because the use of this register is internal to the processor 10

11 Lecture 4 Stored program processors A stored program processor is an instruction-controlled digital system with a memory Block diagram The clock : synchronize all memory elements When does change occurs The processor : ALU a combinatorial logic network in the processor ALU can add, subtract, complement bits, position bits, and so on Registers: hold data numbers operated or produced Signals from outside the processor control the operations of the processor The control unit : Sends control signals to the processor, memory and other parts of the system instruction controlled can recognize hundreds of instructions The memory : a collection of registers outside the processor Instruction code numbers Program: sequence of instruction code stored in the memory Software: the code numbers in the memory, which can be changed without modifying the physical hardware Data numbers: held in the memory to be used by processor Input/Output : transfer data between processor and hardware devices external to the stored program processor Instruction operation Several clock cycles are needed for each instruction One instruction has Fetch phase: the instruction code number is brought out of memory to the control unit Execute phase: The instruction code is carried out control unit coordinates other parts of the machine 11

12 Instruction set Instruction set: All the instruction code number that can be executed by the control unit General-purpose computer Arithmetic operations: arithmetic, add Logical operations: AND, OR, and COMPLEMENT Load and store operations: store and retrieve numbers Testing and branching: make decisions regarding instruction execution Test a number and respond to the result Input and output: communicate with outside world Computer architecture Princeton/von Neumann architecture Fig 1-18 Harvard architecture: separate data memory and instruction memory Fig 1-19 (I did Quiz 1 for the last 35 minutes of the class The quiz has five problems to convert various numbers to decimal numbers I could have used 20 minutes instead of 35 for the quiz) 12

13 Lecture 5 Reading: Chapter 3 Internal Computer Operations LDAA C100 ( = B6 C100) C100 -> B6 C101 -> C2 C102 -> 00 (LDAA) Fetch: First tick of the instruction operation PC = C100 -> microprocessor put address C100 to memory -> memory reads B6 at C100 -> B6 sent back to processor -> processor put B6 at IR IR = B6 -> add one to PC PC = C101 -> determine more is to be fetched -> if so continue fetch mode -> [if not, enter execution mode] Second tick of the instruction operation PC = C101 -> microprocessor put address C101 to memory -> memory reads C2 at C101 -> C2 sent back to processor -> processor put C2 at the second byte of IR IR = B6 C2 -> add one to PC PC = C102 -> determine more is to be fetched -> continue fetch mode -> [if not, enter execution mode] Third tick of the instruction operation PC = C102 -> microprocessor put address C102 to memory 13

14 Execution: -> memory reads 00 at C102 -> 00 sent back to processor -> processor put 00 at the second byte of IR IR = B6 C2 00 -> add one to PC PC = C103 -> determine that no more is to be fetched -> enter execution mode Fourth tick of the instruction operation IR = B6 C2 00 -> processor recognizes LDAA by op code B6 -> send C2 00 in IR to memory to read -> memory sends 44 to the processor -> processor puts 44 in accumulator A A = 44 The processor will enter fetch mode at next tick of clock Instruction operation notation ADDA: Add a number in a memory register to the number in the accumulator A; save the result in accumulator A A + M A Op code: BB Operand: hh ll Total bytes: 3 LDDA: LoaD (copy) a number from a memory register (address provided in the instruction) to accumulator A Load: M A Op code: B6 Operand: hh ll Total bytes: 3 STAA: STore (copy) the number in accumulator A to a memory register addressed by the instruction Store: A M 14

15 Op code: B7 Operand: hh ll Total bytes: 3 STOP: A special instruction to stop program execution in the trainer Op code: 3F Operand: (none) Total bytes: 1 Motorola Assembly Language testasm: * * Sample HC11 assembly program * * NOTES: anything after a * is a comment * * * Data * ORG $0000 * address of data begin testv RMB 1 * test variable result RMB 1 * result variable * * Program * ORG $f800 * address of program begin param1 FCB 5 * constant value param2 FCB 7 * constant value start LDAA #5 * A <- 5 LDAB param2 * B <- 7 STAB testv * store B into var testv ABA * A <- A+B LDAB param1 * B <- 5 ABA * A <- A+B STAA result * result <- A end JMP end * halt * * Jump table * ORG $fffe * address of reset jump 15

16 FDB start * begin at our program 16

17 Lecture 6 Reading: 22 Source Statement Content Numbers: Assembler translates all numbers into 16 bits 2 s complement binary numbers Decimal: Hexadecimal: $ $CF $DBCA Binary: % User symbols: A user symbol is a character string representing a memory address or a numerical value 1-6 alphanumeric characters Symbols TOTALCOMPENSATION and TOTALCOST are truncated to the same as TOTALC The 1st character must be alphabetic Symbol names A, B, X, Y are not allowed, since they represent microprocessor registers Symbol must be uniquely defined A symbol can not be defined twice to represent two memory addresses Reserved symbols: These are symbols to make each instruction easy to remember They are called mnemonics Eg, instead of using B6, LDAA is defined to load a number from a memory register to accumulator A User symbols should avoid using the same name with reserved symbols Expressions: An expression is a combination of symbols separated by the arithmetic operators +, -, *, / 17

18 Eg, COUTER+1 3+4*6 Source Statement Format Each source statement can have up to 4 fields [Label field] [Operation field] [Operand field] [Comment field] The fields are separated by spaces Label field Operation field Operand field Comment field Assembler Directives Memory allocation ORG: ORiGin Eg, ORG $00FF RMB: Reverse Memory Bytes Eg, U RMB 2 Number formation FCB: Form Constant Byte Eg, U FCB 3 U = 3 FDB: Form Double Bytes U FDB $A304 Symbol definition EQU: equates a symbol to a numerical value Eg U EQU 3*4 Assembler control 18

19 END: marks the end of source program It needs no label or expression No more source code lines will be read by the assembler STOP: control the target microcomputer END: control the assembler Asterisk * in column 1: indicates comment from the * to the end of the line Eg, * This is a comment line Dollar $: substitute the current address for the $ symbol Eg, ORG $C100 FIND EQU * LDAA SEARCH FIND will have the value $C100, which is the address of LDAA instruction 19

20 Lecture 7 Reading 22, 23, page Addressing mode: the manner in which the instruction informs the microprocessor the address of the data HC11 has six addressing mode Relative addressing Condition code register: 8 bit microprocessor register that holds test result Bit names: 7 - S : Stop disable 6 - X : X-interrupt 5 - H : Half carry from bit I : I-interrupt 3 - N : Negative 2 - Z : Zero 1 - V : Two s complement overflow error 0 - C : Carry from most significant bit S, X, I are hardware control bits We can ignore them when talking about branch instructions tests are performed automatically at the end of each instruction No commands or instructions are necessary for the tests meaning of the values of the bits in the condition code register depends on the instruction Eg, Add the number N 2 at the memory location M to the number N 1 in register A: ADDA M : A <- A + M <- A = N <- M = N <- A = sum S X H I N Z V C?? 1? (? = unknown) Condition code notation: 20

21 - : unaffected by the instruction 0 : bit is always clear to 0 by the instruction 1 : bit is always set to 1 by this instruction : bit is set or cleared depending on instruction Branch instruction format effective address = program counter + relative offset Eg, BEQ : branch on equal to zero, Op code=a6 Check Z-bit: Z=0, next instruction; Z=1, branch to a new location determined by the relative address A6 <- Op code 04 <- relative offset <- PC offset of 4 <- Relative offset is 8 bit signed two s complement number A positive offset generates a higher address and a negative offset generates a lower address Unconditional and long branches BRA always branch JMP branch to any location, use extended and indexed addressing, not relative addressing Long branches: 0010: BEQ $ : JMP $FF00 FF00: Invalid relative offsets: FF or -1: cause the program to branch to the offset part of the branch instruction 21

22 Infinite loop: FE or -2: cause the program to branch to the beginning of the branch instruction, an infinite loop is resulted The comparison branch instructions Compare two numbers and branch based on the comparison result Comparison branch must be preceded with an instruction of subtraction nature The subtraction instructions include the following: CBA: A-B, Compare B to A Subtract the number in accumulator B from A and throw the result away Content of either accumulator is unchanged Condition code register is affected CMPA: A-M, Compare accumulator to memory Subtract the content of a memory register from the accumulator A and discard the answer Content of accumulator A is unchanged Condition code is affected CMPB: B-M CPX: X-M, compare X to memory Subtract a double byte number in memory from the X index register and discard the answer Content of index register X is unchanged SBA: A = A - B Subtract B from A and put the result in A SUBA: A = A - M Subtract the content in the memory register from A and put the difference into the accumulator A SUBB: B = B - M Subtract the content in the memory register from B and put the difference into the accumulator B Comparison branches for signed numbers: BGE: Branch if Greater than or Equal to Cause a branch if minuend subtrahend Equivalently in the condition code bits: branch if (N is set AND V is set) OR (N is clear AND V is clear) BGT: Branch if Greater Than Cause a branch if minuend > subtrahend, 22

23 Equivalently in the condition code bits: branch if (Z is clear) AND [(N is set AND V is set) OR (N is clear AND V is clear)] BLE: Branch if Less than or Equal to Cause a branch if minuend subtrahend Equivalently in the condition code bits: branch if (Z is set) OR [(N is clear AND V is set) OR (N is set AND V is clear)] BLT: Branch if Less Than Cause a branch if minuend < subtrahend Equivalently in the condition code bits: branch if (N is clear AND V is set) OR (N is set AND V is clear) Comparison branches for unsigned numbers: BHS: Branch if Higher or Same Cause a branch if minuend (unsigned) subtrahend (unsigned) Equivalently: branch if (C is clear) BHI: Branch if HIgher Cause a branch if minuend (unsigned) > subtrahend (unsigned) Equivalently: branch if (C is clear) AND (Z is clear) BLS: Branch if Lower than or Same Cause a branch if minuend (unsigned) subtrahend (unsigned) Equivalently: branch if (C is set) OR (Z is set) BLO: Branch if LOwer Cause a branch if minuend (unsigned) < subtrahend (unsigned) Equivalently: branch if (C is set) 23

24 Lecture 8 Announcement: Quiz 2 will occur on 9/26/2006 Reading: 51, 52 Addressing modes Extended addressing Complete 16-bit address of the data is in the instruction code The address can range from 0000 to FFFF Eg, LDAA $C133 Direct addressing Use one byte to represent an address from 0000 to 00FF LDAA $10 (DIRECT): versus LDAA $0010 (EXTENDED): B The range is limited but the instructions are shorter and faster Inherent addressing The instruction uses only processor registers Eg, ABA Double-byte Data LDX: FE C2 34 C234: 56 C235: 78 24

25 Immediate addressing LDAA #$ LDX #$1234 CE Indexed addressing Add an offset and add to the number in an index register Eg, LDAA 02,X A6 02 C200: 22 <- X: C2 00 C201: 33 C202: 47 <----- offset 2 C203: B7 Indexing with Y register Introducing Y register and associated instructions blow up the 8-bit capacity of the HC11 microprocessor Double bytes are used for instructions associated with the Y index register prebyte + op code it takes one more clock cycle to load the instruction slower Prebytes: 25

26 18 1A CD The total number of instructions for 8 bit is The total number of instructions for 16 bit is = , when using a prebyte of three different values Only instructions are used XGDX, XGDY: Exchange the D accumulator with the X or Y index register Swap 16 bit numbers without affecting the condition code Purpose: operations on X or Y registers are limited Using the D register will allow more complex operations CPD: a double-byte instruction D - M: compare D to memory Bit and byte manipulation Shift operations: Rotate: ROL: rotate left memory byte ROLA: rotate left accumulator A ROLB: rotate left accumulator B Rotate left: bit 7 to C bit; C bit to 0 bit V C <- b7 <- b0 ROR: rotate right memory byte RORA: rotate right accumulator A RORB: rotate right accumulator B Rotate right: C-bit to bit 7 ; bit 0 to bit C V C -> b7 -> b0 26

27 Shift: Arithmetic or logic shift left: ASL (=LSL): Arithmetic or logic shift memory byte left ASLA (=LSLA): Arithmetic or logic shift A left ASLB (=LSLB): Arithmetic or logic shift B left ASLD (=LSLD): Arithmetic or logic shift D left C <- b7 b0 <- 0 Equivalent to multiplication of 2 Logical shift right: LSR, logic shift memory byte right LSRA, logic shift A right LSRB, logic shift B right LSRD, logic shift D right 0 -> b7 b0 -> C Equivalent to division by 2 for unsigned numbers 27

28 Lecture 9 Announcement: Quiz 2 next Tuesday Arithmetic shift right: ASR, arithmetic shift memory byte right ASRA, arithmetic shift A right ASRB, arithmetic shift B right ASRD, arithmetic shift D right > b7 b0 -> C Equivalent to floor division by 2 for two s complement numbers 10 /2 = 5 7 / 2 = 3 0 / 2 = 0 1 / 2 = 0-1 / 2 = -1-3 / 2 = -2 (NOT -1) Example: Binary Decimal Binary Decimal Logical operations: X Y AND(X, Y ) = X Y X Y OR(X, Y ) = X Y

29 X Y XOR(X, Y ) = X Y X COMPLEMENT(X) = X Bit picking: ANDA, ANDB: A A M affecting N, Z, V bits Examples: A ANDA M A B ANDB M B BITA, BITB: A M (Discard results) affecting N, Z, V bits Example: PB = Push Button IN1 PB1 PB2 (Memory)

30 Mask1 FCB % Mask2 FCB % LDAA IN1 BITA Mask1 BEQ NOT BITA Mask2 BEQ NOT BOTH NOT Bit packing: Force the known bit values into certain values without changing other bits ORAA, ORAB: Or memory byte to register A or B Packing: Use ORA to pack 1; Use AND to pack 0; B ANDB M

31 B Lecture 10 BITA, BITB: A M (Discard results) affecting N, Z, V bits Example: PB = Push Button (Memory) IN1 PB IN2 PB OUT LT Mask1 FCB % Mask2 FCB % Mask3 FCB % Mask4 FCB %

32 LDAA IN1 BITA Mask1 BEQ TURNOFF LDAA IN2 BITA Mask2 BEQ TURNOFF TURNON LDAA OUT ORAA Mask3 STAA OUT Turn on the light BRA NEXT TURNOFF LDAA OUT ANDA Mask4 STAA OUT Turn off the light NEXT Bit reversing : Exclusive OR: EOR EORA, EORB: Exclusive or memory byte to accumulator A or B Bit set and clear instructions: BSET: Set all bits in a memory byte that correspond to 1 in the mask Eg, EX1 BSET LIGHTS,$10 Two address modes are used simultaneously: Addressing mode for the mask: immediate # sign is not necessary 32

33 Addressing mode for memory: direct indexed BCLR: Clear all bits in a memory byte that correspond to 1s in the mask Bit testing and branching: BRSET: Branch if all the bits in a memory byte that correspond to 1s in the mask are set BRCLR: Branch if all the bits in a memory byte that correspond to 1s in the mask are clear Three addressing modes are used simultaneously: for the memory byte: direct or indexed for the mask: immediate for the relative addressed branch operation: relative EX2 BRCLR 1,Y,MASK1,NEXT Lecture 11 Announcement: Group must be formed me when it is formed so that you can get the kit Example ******************************************** ** SYMBOL DEFINITION 33

34 ******************************************** SW1 EQU % SWITCH 1 MASK SW2 EQU % SWITCH 2 MASK LT1 EQU % LIGHT 1 MASK ******************************************** ** DATA SECTION ******************************************** ORG $D000 IOAREA RMB 1 RMB 1 IN1 RMB 1 IN2 RMB 1 OUT RMB 1 ********************************************* ** MAIN PROGRAM ********************************************* ORG $C100 * CONTROL LIGHT CONTINUOUSLY START LDX #IOAREA POINT X AT IOAREA BRSET IN1-IOAREA,X,SW1,TSTSCND BCLR OUT-IOAREA,X,LT1 BRA NEXT TSTSCND BRSET IN2-IOAREA,X,SW2,LTON BCLR OUT-IOAREA,X,LT1 BRA NEXT LTON BSET OUT-IOAREA,X,LT1 NEXT BRA START END 34

35 Arithmetic operations Multiplication Fast multiplications are needed in real-time control system MUL: D = A * B multiply the accumulator A by the accumulator B and put the product to accumulator D original numbers in all the accumulators are lost! MUL works with unsigned numbers only bit 7 of D is put into the carry bit C No carry for the product itself This is useful for rounding If C=1, should round the most significant bit to the next number; otherwise, stay the same for signed: Converting negative numbers to positive ones Adjust the result for the sign Shifting: when the multiplier has a single A B A:B [ A ][ B ] 35

36 shift shift right left by 2 by A B A:B [ A ][ B ] shift shift right left by 5 by 3 Thus, one can perform multiple shift in one operation Division for unsigned numbers only IDIV: integer divide of two 16-bit numbers, expecting the quotient to be 1 or higher perform: D / X result: X=quotient, D=reminder C bit is set if divide by zero X = FFFF if divide by zero or quotient too big IDIV D/X Before After D X X D 000A B A

37 FFFF 0005 FFFF 0001 FFFF Lecture 12 FDIV: fractional divide of two 16-bit numbers, expecting the quotient to be smaller than 1 Fractional binary numbers: = perform: D / X result: X=quotient, D=reminder = (1) if the quotient is bigger than FFFF, X will be set to FFFF C bit is set if divide by zero V bit is set if denominator is lower than or the same as the numerator FDIV D/X Before After D X X D A 0005 FFFF A ? 37

38 E ? 0001 FFFF ? ? ( 5 9 : q q q q 4 ) r E = = = = = = E = = 7E E = = = 1B B = = = = 8E Thus, q 1 = 8, q 2 = E, q 3 = 3, q 4 = 8, and r = 0008 shifting when the divider has a single 1 It is faster and more convenient to use MUL to do multiple shift BCD operations DAA: Decimal adjust the A accumulator immediately following only an ADDA, ADDB, ADCA, ADCB, ABA Affects C bit Correct digits out of range by adding one of 00, 06, 60, 66 38

39 Lecture 13 Stack a stack is a region of memory Why do we need stack? Reuse memory space with less complications Last-in-first-out (LIFO) stack point register the content is a 16-bit address always point to the next available element in the stack Stack Instructions INS, DES : Increment or decrement the stack pointer LDS, STS : Load or store the stack pointer register PSHA, PSHB : Push the A or B accumulator onto the stack then decrement the stack pointer by 1 PSHX, PSHY : Push two bytes from the X or Y index register onto the stack then decrement the stack pointer by 2 PULA, PULB : Pull a byte from the stack and load it into the A or B accumulator 1 increment the stack pointer by one 2 load the number pointed by the pointer to A or B 39

40 PULX, PULY : Pull two bytes from the stack and load them into the X or Y index register 1 increment the stack pointer by 2 2 load 2 bytes to the index register TSX, TSY : Transfer stack pointer plus one to X or Y index register To overcome the automatic adjustment TXS, TYS : Transfer X or Y index register minus one to the stack pointer ORG $C100 * Initialize stack START LDS #$CFFF stack for Motorola trainer * Create data values for demonstration LDAA #$22 LDAB #$33 * Store data in stack PSHA PSHB * Retrieve data from stack in reverse order PULA PULB SWI "stop" for trainer END Using the stack: After a stack is used, numbers will remain in the memory They must be considered gone in your program One should not rely on the values 40

41 One should always pull the same number of bytes that were pushed Make sure that the stack does not overwrite the program at the maximum depth of the stack Subroutines They are reusable program modules save memory space improve program organization (the major benefit) independent of calling program obtain program control when called release program control when returning Instructions JSR/BSR: Jump/branch to subroutine and save the return address in the stack RTS: Return from subroutine by retrieving the return address from the stack C100 BD <- JSR OP CODE C101 C4 C C103 C103 IS PUSHED TO STACK C18A BD C18B C4 C18C 00 <- JSR OP CODE 41

42 C18D C18D IS PUSHED TO STACK C400 SUBROUTINE C401 C <- RTS OP CODE, WILL PULL STACK ******************************* * DATA SECTION ******************************* ORG $10 VALUE FCB $46 ******************************* * MAIN PROGRAM ******************************* ORG $C100 * INITIALIZE STACK START LDS #$CFFF * DEMONSTRATE SUBROUTINE OPERATION LDAA VALUE JSR SWAPA SWI ******************************* 42

43 * SUBROUTINE SWAPA * SWAP HIGH AND LOW 4 BITS OF A * ACCUMULATOR * * AFFECTS A AND CC ******************************* * * SWAP BITS * SWAPA LSLA ADCA #0 LSLA ADCA #0 LSLA ADCA #0 LSLA ADCA #0 * * RETURN FROM SUBROUTINE * RTS END 43

44 Lecture 16 Parameter Passing Passing parameters from calling program to a subroutine Parameter: value or reference 1 ********************************************** 2 ** DEMONSTRATE BAD SUBROUTINES 3 * 4 ********************************************** 5 * 6 ********************************************** 7 ** MAIN PROGRAM 8 ********************************************** 9 ORG $C * * INITIALIZE STACK 12 * START LDS #$CFFF STACK FOR TRAINER 14 * * USE BAD SUBROUTINES 16 * * MAKE DATA IN MAIN PROGRAM 18 LDAB #$11 19 * SET UP DATA FOR SUBROUTINE 20 LDAA #$22 21 STAA NUMBER 22 * CALL SUBROUTINE TO ADD TWO 23 JSR ADDTWO 44

45 24 * USE RESULT FROM SUBROUTINE 25 LDAA NUMBER 26 STAA ANS2 27 * SET UP DATA FOR SUBROUTINE 28 LDAA #$33 29 STAA NUMBER 30 * CALL SUBROUTINE TO ADD TO POSITIVE 31 JSR BAD 32 * USE RESULT FROM SUBROUTINE 33 LDAA NUMBER 34 STAA ANS3 35 * STORE MAIN PROGRAM DATA 36 STAB ANS1 37 SWI "STOP" FOR TRAINER 38 * 39 ********************************************** 40 ** DATA SECTION 41 ********************************************** 42 NUMBER RMB 1 43 ANS1 RMB 1 44 ANS2 RMB 1 45 ANS3 RMB 1 46 * 47 ********************************************** 48 ** SUBROUTINE BAD, ADDTWO, ADDONE 49 * INCREMENT POSITIVE TWO S COMPLEMENT NUMBERS, 50 * OR ADD ONE OR TWO TO ANY NUMBER 51 ********************************************** 52 ORG $C * SUBROUTINE BAD -- POSITIVE NUMBER? 45

46 54 BAD LDAB NUMBER 55 BPL ADDONE BRANCH IF PLUS 56 * SUBROUTINE ADDTWO 57 ADDTWO INC NUMBER 58 * SUBROUTINE ADDONE 59 ADDONE INC NUMBER 60 RTS 61 END Problems: No parameter passing, instead, sharing NUMBER Subroutine has to be changed if called by other program The main program must use the NUMBER to call the subroutine Inflexible B accumulator was changed in the subroutine but no restored Multiple entries of subroutine Lecture 17 Call-by-Value: Use microprocessor registers: A, B, X, Y a total of 6 bytes 1 *************************************************** 2 ** DEMONSTRATE DELAY SUBROUTINE 3 * PASS DELAY VALUE IN A ACCUMULATOR 4 * 5 *************************************************** 46

47 6 * 7 *************************************************** 8 ** SYMBOL DEFINITION 9 *************************************************** 10 DELAY EQU $C150 LINK TO SUBROUTINE 11 * 12 *************************************************** 13 ** DATA SECTION 14 *************************************************** 15 ORG $ DELPAR RMB 1 USER SUPPLIED VALUE 17 * 18 *************************************************** 19 ** MAIN PROGRAM 20 *************************************************** 21 ORG $C * * INITIALIZE STACK POINTER 24 * START LDS #$CFFF STACK 26 * * WAIT SPECIFIED TIME 28 * * GET DELAY PARAMETER 30 LDAA DELPAR 31 * DELAY 32 JSR DELAY 33 SWI 34 END 47

48 1 *************************************************** 2 ** SUBROUTINE DELAY 3 * MODIFIES A,X,CC 4 * 5 *************************************************** 6 * 7 ORG $C150 8 * GET NUMBER OF PERIODS 9 * (ALREADY IN ACCUMULATOR A) 10 * INITIALIZE PERIOD COUNTER 11 * USE ACCUMULATOR A FOR PERIOD COUNTER 12 * ALL PERIODS DONE? 13 DELAY TSTA 14 BEQ RT BRANCH ON YES 15 * WAIT 20 MILLISECONDS 16 * INITIALIZE 20-MILLISECOND COUNTER 17 LDX #$115C USE X REGISTER FOR COUNTER 18 * DONE WITH 20 MILLISECONDS? 19 AGAIN BEQ AHEAD BRANCH ON YES 20 * ADJUST 20-MILLISECOND COUNTER 21 DEX 22 BRA AGAIN 23 * ADJUST PERIOD COUNTER 24 AHEAD DECA 25 BRA DELAY 26 * RETURN TO MAIN PROGRAM 27 RT RTS 28 END Position independent code: 48

49 A subroutine is position-independent if it can be placed anywhere in the memory without alteration and they will work correctly In 68HC11, no direct or extended addressing to reference other parts of the position independent program module is sufficient 49

50 Lecture 18 Call-by-Value in memory example 1 ********************************************** 2 ** DEMONSTRATE SUBROUTINE -- ROTATE A ACCUMULATOR LEFT 3 ** MULTIPLE POSITIONS 4 * PASS PARAMETER BY VALUE AS MEMORY CONSTANT 5 * 6 ********************************************** 7 * 8 ********************************************** 9 ** DATA SECTION 10 ********************************************** 11 ORG $10 12 VALUE FCB $06 DATA FOR DEMONSTRATION 13 * 14 ********************************************** 15 ** MAIN PROGRAM 16 ********************************************** 17 ORG $C * INITIALIZE STACK 19 START LDS #$CFFF STACK 20 * ROTATE A ACCUMULATOR LEFT 4 POSITIONS 21 LDAA VALUE 22 JSR ROTAL 23 FCB 4 CONSTANT FOR POSITIONS 24 SWI STOP 25 * 26 ********************************************** 27 ** SUBROUTINE ROTAL 50

51 28 * ROTATE ONLY A ACCUMULATOR LEFT, CONSTANT FOLLOWING 29 * JSR INSTRUCTION SPECIFIES POSITIONS -- MODIFIES A,CC 30 ********************************************** 31 * * INITIALIZE SUBROUTINE 33 * * SAVE MAIN PROGRAM REGISTERS 35 ROTAL PSHX 36 PSHB 37 * GET NUMBER OF POSITIONS 38 TSX 39 LDX 3,X 40 LDAB 0,X 41 * * ROTATE A 43 * BACK TSTB 45 BEQ AHEAD 46 DECB 47 ASLA 48 ADCA #0 49 BRA BACK 50 * * RETURN FROM SUBROUTINE 52 * * ADJUST RETURN ADDRESS 54 AHEAD TSX 55 INC 4,X 56 BNE RET 57 INC 3,X 51

52 58 * RESTORE MAIN PROGRAM REGISTERS 59 RET PULB 60 PULX 61 RTS 62 END CFFB (B) CFFC (X)hh CFFD (X)ll CFFE C CFFF Lecture 19 Serial communication interface hexmon download program through serial communication to EPROM of the miniboard Serial communication is done through PORT D, but the way it is programmed is quite different than other ports 52

53 Parallel communication is when all the bits of a value are sent to the receiver at the same time, ie, in parallel To do this you need a wire for each bit This is the way a CPU sends and receives data from memory, and disks, and things like that Parallel communication needs a lot of wires, but it can be very fast Serial communication sends each bit one at a time You only need one (data) wire in this case, so this matches well when you need to communicate over long wires, like phone or network lines All networks use serial communication, and some devices, like printers, often can use serial communication A simplex connection sends data in only one direction One data wire is needed A half-duplex connection sends data in both directions, but not at the same time One data wire is needed, and its direction is switched back and forth A full duplex connection sends data in both directions simultaneously Two data wires are needed, one in each direction Example Miniboard Our phone cord connections from the Miniboard to a PC are full duplex connections In the diagrams in your manual, one pin (wire) was labelled 53

54 RxD (Receive Data), one was TxD (Transmit Data), and the other two are tied together as GND (Ground) Having a ground wire improves the signal quality between the two endpoints, and since a regular phone cord has four wires, this connection simply uses two as ground Communication protocol Both sides must, of course, agree on a signalling protocol to be able to transmit data That is, they need to agree on what voltage levels mean what, and when and how fast the signals will change The protocol that the HC11 uses with the PC is called RS-232, and is a very commonly used protocol for serial communication between nearby devices (it doesn t work over a long distance like a modem does) Baud rate The speed at which the serial communication takes place is called the baud rate This is the same baud that is used to describe modems, because they also do serial communication (but with different protocols) Some standard baud rates for RS-232 links are 2400 bps (bits per second), 4800 bps, 9600 bps, 192 Kbps (kilo-bps), and faster We will use 9600 bps for the HC11-to-PC With the way RS-232 works, 10 bits are transmitted for every byte of data This is because the transmitter and receiver have to agree when data starts and stops Question 1: How many bytes of data can be transmitted per second using 9600bps? 54

55 Question 2: How long does it take to send one byte of data? How many HC11 cycles go bye during a one-byte transmission? In answering the above questions, you see that 9600 bps is pretty slow compared to how fast the CPU goes In this class, hopefully you are learning that everything is pretty slow compared to how fast a CPU goes The CPU has to constantly wait for things to happen outside of itself Setting up Serial I/O on the HC11 1 Specify the baud rate that you want to communicate at, by setting the BAUD register ($102B), or at least parts of it Its bits are: Bit 7: TCLR it does something, I m sure Bit 6: 0, not used Bits 5,4: SCP1 and SCP0 these bits selected a prescaler divide factor Bit 3: RCKB it does something, I m sure Bits 2-0: SCR2, SCR1, and SCR0 these bits select another (rate control) divide factor It is a bit confusing, but you have to combine the selection of the prescaler divide factor (SCP0-1) with the selection of a rate control divide factor (SCR0-2) to get a certain baud rate Furthermore, it is dependent on how fast your clock (crystal) is The two tables are shown in the book on pages 389 and 390, and in the Reference Manual on page 9-8 The 55

56 Miniboard s crystal is 8Mhz, giving a 2Mhz clock There are different ways to get 9600 baud on the Miniboard, but one is to set SCP0-1 to 11 and SCR0-2 to 000 Thus, if you load register A with % , and then store this to BAUD, you will set your HC11 to be using 9600 baud 2 The other step you need to take during initialization is to actually turn the serial communication on, just like we had to turn the analog-to-digital subsystem on This is done using the SCCR2 register ($102D) There are bits that allow you to turn on transmission and reception independently The bits in the SCCR2 are: Bit 7: TIE transmitter interrupt enable Bit 6: TCIE transmit complete interrupt enable Bit 5: RIE receiver interrupt enable Bit 4: ILIE idle line interrupt enable Bit 3: TE transmission enable this must be 1 to be able to send data from the HC11 Bit 2: RE receive enable this must be 1 to be able to receive data to the HC11 Bit 1: RWU Bit 0: SBK So, at the minimum, bits 2 and 3 of SCCR2 must be set to 1 to enable full duplex (both way) sending of data For now we will ignore bits 4-7, just make sure to leave them 0 56

57 3 When actually sending and receiving data, the register SCSR ($102E) is used Remember, serial I/O is much slower than the CPU, so we must test to see if the previous data has already been sent before we can send again The bits of SCSR are: Bit 7: TDRE transmit data register empty when this is 1, it is safe to transmit another byte Bit 6: TC transmit complete even though TDRE is ready, transmission of the previous byte is not necessarily finished this flag tells you when it is we normally won t use this Bit 5: RDRF receive data register full when this is 1, a byte is ready to be read Bit 4: IDLE if this bit is 1, the receive data line has been idle for at least a 1-byte time Bit 3: OR overrun error when this is 1, your program didn t read a byte fast enough, and the next incoming byte had no where to go, so it was lost Bit 2: NF noise flag if this is 1, some electrical noise probably ruined your incoming data Bit 1: FE framing error if this is 1, errors about when the byte ended have ocurred Bit 0: 0 always 0, not implemented So, to transmit a byte, your program just waits until TDRE is 1, then transmits it To receive a byte, your program waits until RDRF is 1, then receives 57

58 it But how do we do the actual transmit and receive? Very, very simply Just write a byte to SCDR ($102F) to transmit, and read a byte from SCDR to receive Notice that the value you read from location SCDR has no relation to the value you write to the same location It just means that the HC11 uses the same address to send and receive data (This section can be ignored We will not cover it yet) Of course, rather than waiting, we can use interrupts, which are enabled in SCCR2 With the transmit interrupt (TIE, bit 7) you have to be careful, because it will keep interrupting as long as the transmitter is not busy So you cannot just leave this interrupt enabled constantly You should only enable it when you have a long sequence of bytes to transmit, and then should disable when you are done with that sequence The receive interrupt (RIE, bit 5) is harmless to leave on, as long as your program can handle incoming characters The other interrupts in SCCR2 (TCIE and ILIE, bits 6 and 4) are not needed by us The interrupt vector (ie, the address in the interrupt table) for serial communications is FFD6,D7 This is where you put the address of your interrupt service routine, or interrupt handler But, you must note that your interrupt routine must handle five different conditions This one routine handles receive, transmit, idle, and error interrupts it s up to you to tell the dif- 58

59 ference! You do this simply by testing the flags in SCSR in other words, test TDRE and if it is 1 then transmit if you need to, test RDRF and receive a byte if it is 1, test others and do whatever you need to Lecture 20 ASCII character representation When you use hexmon and send commands to the Miniboard, like r , each character that you type is a byte that is sent to the Miniboard The question is, what byte value is r, and how did we know that? Well, an agreed-upon standard for byte values representing characters is the ASCII standard (American Standard Code for Information Interchange), and it assigns a number value to each character you can type, including punctuation (and some that you cannot type) So, for example, the character A decimal value 65 hex $41, a decimal 97 hex $61 The letters are numerically in order for upper and lower case, B is $42, b is $62, and on all the way to Z and z (question: how do you capitalize an ASCII letter?) In between Z ($5A) and a ($61) is a few punctuation characters ( [ $5B, \ $5C, ] $5D,) We started by asking what r is, but actually, the 0 s 59

60 are not numerically zero, and 5 is not numerically five Rather the character 0 that we type has an ASCII value of decimal 48, hex $30, and the characters for each of the digits is in order from 0 : 1 is $31, 2 is $32,, 9 is $39 On a Unix workstation, you can type in the command man ascii, and you will see a chart of all of the ASCII characters ASCII originally used 7-bit characters, and so only had 128 possible characters ISO extended that to 8-bit characters (different manufacturers had already used 8-bit characters, with the upper 128 values being proprietary characters (like line-drawing on MS- DOS)) But even 256 values is not nearly enough to represent, for example, Chinese characters ISO does well with basic European languages with the various accented characters, but that s about it A new standard called Unicode (ISO Universal Character Set [UCS]) has been devised that uses 16-bit characters With 16 bits ie, 65,534 different values every character of every known language (including all the many thousands of Asian language characters) can have it s own unique value One nice thing about Unicode is that values with the upper byte of $00 map directly to ISO , and thus to ASCII So 8-bit ASCII characters will be around for a while An encoding of Unicode called UTF is popular as a method to preserve back- 60

61 wards compatibility with ASCII strings On our Linux workstations, man unicode and man utf-8 will give you more information 1 ******************************************************** 2 ** TRIGGER OUTPUT MESSAGE WITH INPUT CHARACTER 3 * 4 * USE SCI SERIAL COMMUNICATIONS INTERFACE WITH 80-MHZ 5 * CRYSTAL FOR 68HC11 CLOCK 6 * 7 ******************************************************** 8 * 9 ******************************************************** 10 ** SYMBOL DEFINITIONS 11 ******************************************************** 12 * 68HC11 REGISTERS 13 REG EQU $1000 BEGINNING OF REGISTERS 14 BAUD EQU $102B BAUD RATE REGISTER 15 SCCR1 EQU $102C CONTROL REGISTER 1 16 SCCR2 EQU $102D CONTROL REGISTER 2 17 SCSR EQU $102E STATUS REGISTER 18 SCDR EQU $102F DATA REGISTER 19 * MASKS 20 BIT3 EQU % BIT5 EQU % BIT7 EQU % * 24 ******************************************************** 25 ** DATA SECTION 26 ******************************************************** 27 ORG $

62 28 CHARCNT RMB 1 NUMBER OF CHARS TRANSMITTED 29 * 30 ORG $C * MESSAGE TABLE 32 BEGMSG FCC THE INPUT CHARACTER WAS 33 INCHAR RMB 1 INPUT CHARACTER INSERTED IN 34 FCB $0D CARRIAGE RETURN 35 ENDMSG FCB $0A LINE FEED 36 * 37 ORG $FFD6 38 FDB SCIISR SCI INTERRUPT VECTOR 39 * 40 ******************************************************** 41 ** MAIN PROGRAM 42 ******************************************************** 43 ORG $C * * INITIALIZATION 46 * * INITIALIZE STACK 48 START LDS #$CFFF 49 * INITIALIZE SCI SERIAL COMMUNICATIONS INTERFACE 50 * INITIALIZE SCI MODE 51 CLR SCCR1 8-BIT CHARACTERS, NO WAKE UP 52 * INITIALIZE SCI BAUD RATE TO 1200 BAUD 53 LDAA #$33 SCP1:SCP0=11 SCR2:SCR1:SCR0= STAA BAUD 55 * ENABLE SCI RECEIVER AND ITS INTERRUPT 56 LDAA #$24 DISABLES SCI TRANSMITTER AND 57 STAA SCCR2 ITS INTERRUPT 62

63 58 * TURN ON INTERRUPT SYSTEM 59 CLI 60 * * WAIT FOR INTERRUPTS 62 * HERE BRA HERE 64 * 65 ******************************************************** 66 ** SCI INTERRUPT SERVICE ROUTINE 67 ******************************************************** 68 * * INTERRUPT POLLING CHAIN 70 * * INTERRUPT FROM SCI RECEIVER? 72 SCIISR LDX #REG 73 BRSET SCSR-REG,X,BIT5,SCIRCV 74 * INTERRUPT FROM SCI TRANSMITTER? 75 BRSET SCSR-REG,X,BIT7,SCITX 76 * ILLEGAL INTERRUPT 77 BRA RTSCI IGNORE 78 * * SERVICE SCI RECEIVER 80 * * READ INPUT CHARACTER 82 SCIRCV LDAA SCDR-REG,X FINISH CLEARING FLAG 83 * PUT INPUT CHARACTER INTO OUTPUT MESSAGE 84 STAA INCHAR 85 * INITIALIZE MESSAGE BYTE COUNT 86 CLR CHARCNT 87 * START MESSAGE - ENABLE SCI XMTR AND ITS INTERRUPT 63

64 88 BSET SCCR2-REG,X,BIT7+BIT3 SENDS IDLE CHAR 89 * RETURN TO MAIN PROGRAM 90 JMP RTSCI 91 * * SERVICE SCI TRANSMITTER 93 * * AT END OF MESSAGE 95 SCITX LDAA #ENDMSG-BEGMSG+1 MESSAGE LENGTH 96 CMPA CHARCNT 97 BHI MORE 98 * TERMINATE MESSAGE - DISABLE XMTR AND ITS INTERRUPT 99 BCLR SCCR2-REG,X,BIT7+BIT3 100 BRA RTSCI 101 * TRANSMIT NEXT CHARACTER 102 * GET CHARACTER FROM TABLE 103 * POINT TO MESSAGE TABLE 104 MORE LDX #BEGMSG 105 * ADJUST POINTER TO NEXT CHARACTER 106 LDAB CHARCNT 107 ABX 108 * GET NEXT CHARACTER ASCII CODE 109 LDAA 0,X 110 * OUTPUT NEXT CHARACTER 111 STAA SCDR FINISH CLEARING XMTR FLAG 112 * INCREMENT COUNT OF CHARACTERS SENT 113 * INC CHARCNT 114 * * RETURN FROM SCI INTERRUPT 116 * RTSCI RTI 64

65 118 END Lecture 21 Quiz 3 * SCIDEMOASM REG EQU $1000 BAUD EQU $102B SCSR EQU $102E SCDR EQU $102F SCCR1 EQU $102C SCCR2 EQU $102D BRATE EQU % TDRE EQU % TC EQU % ORG $F800 charcn EQU $0000 BEGMSG FCC WELCOME TO SCI! FCB $0D ENDMSG FCB $0A ORG $F900 start LDAA #BRATE STAA BAUD LDAA #%

66 STAA SCCR1 LDAA #$08 STAA SCCR2 CLR charcn SCITX LDAA #ENDMSG-BEGMSG+1 CMPA charcn BHI more JMP end more LDX #BEGMSG LDAB charcn ABX LDAA 0,X LDY #REG WaitTDRE BRCLR SCSR-REG,Y TDRE WaitTDRE INC STAA BRA charcn SCITX SCDR end JMP end ORG $fffe *reset jump FDB start *start at our program 66

67 Lecture 22 Call by reference Passing parameter by reference in memory 1 *************************************************** 2 ** DEMOSTRATE SUBROUTINE--COUNT ZERO BYTES IN TABLE 3 * PASS PARAMETERS BY REFERENCE EIN MEMORY 4 * USE MICROPROCESSOR REGISTERS FOR LOCAL STORAGE 5 * 6 *************************************************** 7 * 8 *************************************************** 9 ** DATA SECTION 10 *************************************************** 11 ORG $25 12 LENGTH FCB 4 DATA FOR DEMONSTRATION 13 ORG $C ANSWER RMB 1 15 ORG $C TABLE FCB $45 17 FCB $00 18 FCB $10 19 FCB $00 20 * 21 *************************************************** 22 ** MAIN PROGRAM 23 *************************************************** 24 ORG $C100 67