EE 3170 Microcontroller Applications

Transcription

1 Block Diagram of 68HC11A8 EE 3170 Microcontroller Applications Lecture 14: Advanced 68HC11 Hardware- Part II: Serial Communications Interfacing - Miller 7.10 Interrupt control Clock Mode control A/D ref. voltage COP Real-Time Interrupt ROM RAM Microprocessor Timer & Pulse Accumulator SCI SPI Port A Port B Port C Strobe Port D Based on slides for ECE3170 by Profs. Davis, Kieckhafer, Tan, and Cischke Chip power EEPROM A/D converter Port E EE3170/CC/Lecture#14-PartII 1 EE3170/CC/Lecture#14-PartII 2 68HC11A8 Components Memory RAM ROM Programmable Timer & Pulse Accumulator Port A EEPROM Parallel Input/Output Port B Port C Strobe STRA STRB SCI (SPI) Serial Communications (Peripheral) Interface Port D Analog-to-Digital Converter Port E EE3170/CC/Lecture#14-PartII 3 EE3170/CC/Lecture#14-PartII 4

2 Serial I/O Overview Parallel vs. Serial Ports Simplex vs. Duplex Communication Error Control, and Parity Signaling Standards Data Formatting Message Synchronization Message Errors Parallel I/O Ports I/O Ports so far have been parallel Xmits/Receives multiple bits at once one pin per bit one wire per bit Control = strobe signals, e.g. Data valid (ready) Data received (acknowledge) 8 EE3170/CC/Lecture#14-PartII 5 EE3170/CC/Lecture#14-PartII 6 Parallel I/O Ports Advantages maximum throughput (bits in parallel) good for short range high data rate busses e.g. disk or printer interface Disadvantages Need many wires (one per bit + strobes) Cabling gets expensive Cabling gets clumsy (e.g. ribbon cable) Some long-distance media are inherently single-line phone-lines or wireless frequencies What are the Advantages of Serial Communication? As little as one wire between xmitter and receiver cabling is cheaper and more flexible appropriate for inherently serial media Good for longer range and/or lower data rate communications e.g. remote terminal or modem EE3170/CC/Lecture#14-PartII 7 EE3170/CC/Lecture#14-PartII 8

3 What are the Disadvantages of Serial Communication? Serial I/O Format Reduced throughput relative to parallel only one bit a time Added complexity of self-synchronizing protocol Length of Bit Time Data Bits : Number of Data bits per Character Frame Parity : Even, Odd, None Stop Bits : 1, 1.5, 2 EE3170/CC/Lecture#14-PartII 9 EE3170/CC/Lecture#14-PartII 10 Serial I/O Protocol Examples 9600 N Baud : No Parity : 8 data bits : 1 Stop bit (9600 bits / second) / ( bits/frame) = 960 frames / sec = 960 Bytes / sec Efficiency = 8/(1+8+1) = E Baud : Even Parity : 7 data bits : 2 Stop bit (38400 bits / second) / ( bits/frame) = 3490 frames / sec * 7 bits / frame = 3053 Bytes / sec Efficiency = 7/( ) = 0.64 Simplex/Duplex Definitions Simplex = one direction comm. needs only one data channel e.g. keyboard-to-computer, computer-to-monitor Duplex = two direction comm. Half-Duplex = only one direction at a time needs only one data channel Xmit privilege must be time-shared Full-Duplex = both directions in parallel needs two data channels Both ends can xmit at once EE3170/CC/Lecture#14-PartII 11 EE3170/CC/Lecture#14-PartII 12

4 Collision and Error Detection Note: Half-Duplex needs collision detection Both ends could start transmitting at once. Neither message will get through. Both ends must detect the collision and back-off. Errors from noise and interference faster bit rates are more vulnerable to noise longer distances are more vulnerable to noise Receiver should detect or correct errors: EDC = Error Detection Code Most common is a single parity bit ECC = Error Correction Code Many exist. Parity EDC Count the number of ones in data bits. Add a parity bit to each word. to guarantee that whole word has either Even Parity make the total number of ones even Odd Parity make the total number of ones odd Parity is easy to calculate at transmitter P = (d N xor d N-1 xor xor d 0 ) xor (ODD/EVEN) Parity is easy to check at the receiver ERR = [P xor (d N xor d N-1 xor xor d 0 ) xor (ODD/EVEN) ] EE3170/CC/Lecture#14-PartII 13 EE3170/CC/Lecture#14-PartII 14 Bit-Serial Parity Checker Calculates parity on-the-fly running XOR useful in both xmitter and receiver Parity Example (Odd) Transmitter Forces Odd Parity Transmitter forces number of ones to be odd: [ ] parity bit = 1 xmit [ ] Receiver expects Odd parity Next bit Bit clock D Ck Clr Q Initialize If no errors en route, then receiver gets [ ] number of 1 s is odd no error Assume bit d 0 is flipped en-route, then receiver gets: [ ] number of 1 s is even error EE3170/CC/Lecture#14-PartII 15 EE3170/CC/Lecture#14-PartII 16

5 Parity Exercise Rework the preceding example for even parity. Parity Coverage Parity is Single-Error Detecting code guaranteed to detect all single-bit errors in reality will detect any odd number of bit errors Parity is not an error correcting code can t tell which bit is in error knows only an error occurred somewhere Usual response to a parity error is to request retransmission of data EE3170/CC/Lecture#14-PartII 17 EE3170/CC/Lecture#14-PartII 18 A Few Signaling Standards RS-232 (Conventional Serial I/O) Copper cable Actually does have some control lines Receiver Logic Levels: 1 = -3V -25V 0 = +3V +25 V Xmitter Logic levels typically: 1 = -12V & 0 = +12 V very robust, cheap hardware A Few Signaling Standards Telephone modem modulates outgoing signal into acoustic tone demodulates incoming tones into logic levels can get full-duplex by frequency multiplexing, e.g. One end: 1 = 1275 Hz & 0 = 1075 Hz Other end: 1 = 2225 Hz & 0 = 2025 Hz EE3170/CC/Lecture#14-PartII 19 EE3170/CC/Lecture#14-PartII 20

6 Data Formatting Xmitter and receiver must agree on Bit-clock period τ Endian ordering of the data Number of bits per word Parity Mode Framing bits to identify start of a data word start-bit = 1 stop-bit(s) = 0 Idle or quiescent state of the line Data Formatting Start Bit Resting state = 1 Need to ID start of a word to the receiver Start bit must be a 0 receiver looks for first 1 0 edge 1 0 EE3170/CC/Lecture#14-PartII 21 EE3170/CC/Lecture#14-PartII 22 Data Formatting Stop Bit(s) Must return to rest state at end guarantees receiver can re-sync on next start bit Last bit(s) of message must be a 1 receiver can looks for first 1 0 edge for next word 1 Data Formatting 1-Byte Data Ordering Low-Order bits first Last bit transmitted is the parity bit (if any) allows transmitter to generate parity on-the-fly 1 XMIT = % EE3170/CC/Lecture#14-PartII 23 EE3170/CC/Lecture#14-PartII 24

7 Message Synchronization Message Errors Xmitter and receiver internal clocks don t operate at the same frequency. Receiver must detect the start-bit (1st falling edge). Receiver samples much faster than the bit-rate. Typically 16x bit rate Allows accurate detection of the falling edge Once start-bit is detected Receiver samples middle of each bit allows for maximum skew between clock frequencies typically does > 1 sample for noise immunity Timing Error occurs if the clock frequencies are too far out of sync sample point drifts away from center of bit results in erroneous samples fortunately crystal clocks are very accurate Framing Error occurs if receiver gets confused on start of message interprets some zero data value as start bit if the expected stop bit is a zero then it recognizes the framing error EE3170/CC/Lecture#14-PartII 25 EE3170/CC/Lecture#14-PartII 26 Timing Error Framing Error occurs if the clock frequencies are too far out of sync. sample point drifts from center of bit results in erroneous samples fortunately crystal clocks are very accurate Start and stop bits do not properly frame the character. Received character doesn t end with stop bit. occurs if receiver gets confused on start of message interprets some zero data value as start bit if the expected start bit is a zero detected when receiver can t find stop bit either in this character or in following character EE3170/CC/Lecture#14-PartII 27 EE3170/CC/Lecture#14-PartII 28

8 68HC11 SCI Port Basic Transmission Operations Provides standard Serial Comm Port Removes details of operation from the software bit-by-bit output real-time bit rate management Provides a variety of interrupts Various transmit and receive conditions Allows continuous transmission and reception buffer registers serial I/O shift registers Program stores to Xmit Data Register Xmit Data Register moves data to Xmit Shift Register program can then store next word in Xmit Data Register Xmit Shift Register shifts data out through Pin PD1 at preset baud rate lsb first Data Bus Xmit Data Reg Xmit Shift Reg TxD Pin PD1 EE3170/CC/Lecture#14-PartII 29 EE3170/CC/Lecture#14-PartII 30 Basic Receive Operations Receiver Shift Register shifts data in through PD0 at preset baud rate into most significant bit getting least significant bit first Receiver Shift Register moves data to Receiver Data Register Program loads from Receiver Data Register RxD Data Bus Rcvr Data Reg Rcvr Shift Reg Pin PD0 Ports COP PULSE ACCUMULATOR MODA/ LIR MODE CONTROL TIMER SYSTEM PORT A MODB/ V STBY PERIODIC INTERRUPT PA7/PAI/OC1 PA6/OC2/OC1 PA5/OC3/OC1 PA4/OC4/OC1 PA3/OC5/OC1 PA2/IC1 PA1/IC2 PA0/IC3 XTAL EXTAL OSCILLATOR CLOCK LOGIC PORT B E BUS EXPANSION ADDRESS PB7 PB6 PB5 PB4 PB3 PB2 PB1 PB0 CPU IRQ/ XIRQ STROBE AND HANDSHAKE PARALLEL I/O SINGLE CHIP MODE INTERRUPT LOGIC ADDRESS/DATA CONTROL PORT C RESET R/W AS PC7 PC6 PC5 PC4 PC3 PC2 PC1 PC0 STRB STRA A15 A14 A13 A12 A11 A10 A9 A8 A7/D7 A6/D6 A5/D5 A4/D4 A3/D3 A2/D2 A1/D1 A0/D0 R/W AS SS SCK SPI MOSI MISO PD5/SS PD4/SCK PD3/MOSI PD2/MISO 8 KBYTES ROM 512 BYTES EEPROM 256 BYTES RAM CONTROL PORT D SCI TxD RxD PD1/TxD PD0/RxD A/D CONVERTER PORT E PE7/AN7 PE6/AN6 PE5/AN5 PE4/AN4 PE3/AN3 PE2/AN2 PE1/AN1 PE0/AN0 V DD V SS V RH V RL 1 EXPANDED MODE CIRCUITRY ENCLOSED BY DOTTED LINE IS EQUIVALENT TO MC68HC24. EE3170/CC/Lecture#14-PartII 31 EE3170/CC/Lecture#14-PartII Figure 1-1 Block Diagram 32

9 Port D Data Register Operations PD5/SS PD4/SCK PD3/MOSI PD2/MISO PD1/TxD PD0/RxD PE7/AN7 PE6/AN6 PE5/AN5 PE4/AN4 PE3/AN3 PE2/AN2 PE1/AN1 PE0/AN0 CONTROL PORT D PORT E SS SCK MOSI MISO TxD RxD SPI SCI A/D CONVERTER 256 BYTES RAM V RH V RL 512 BYTES EEPROM V DD V SS 8 KBYTES ROM Xmit Data Register and Rcvr Data Register are two physical registers that share the same address! Name = SCDR = Serial Comm. Data Reg. Address = $102F Operation: staa $102F: stores a byte from accumulator A to Xmit Data Register ldaa $102F: loads a byte from Rcvr Data Register to accumulator A EE3170/CC/Lecture#14-PartII 33 EE3170/CC/Lecture#14-PartII 34 Controlling the SCI SCI registers Must set the bit rate Need flags to show states of Data Registers and Shift Registers When outgoing data has been shifted from Xmit Data Register to Xmit Shift Register When new incoming data is available in Rcvr Data Register from Rcvr Shift Register Need flags to show state of the I/O port idle line Errors Must generate interrupts for these flags EE3170/CC/Lecture#14-PartII 35 EE3170/CC/Lecture#14-PartII 36

10 Bit Rate Control SCI hardware transfers bits at preset bit rate Programmable Frequency Dividers set bit rate Crystal sets base freq (usually 8MHz) E-Clock = Xtal freq / 4 Prescalar divides E-clock by 1, 3, 4, or 13 divisor set by bits SCP1 & SCP0 in BAUD register Rate Control Unit divides prescalar output by 1, 2, 4, 8, 16, 32, 64, or 128 divisor set by bits SCR2, SCR1, and SCR0 in BAUD register Bit Rate Control Rate Control Unit output = 16 x Bit rate This signal is used as the sampling clock A fixed divide-by-16 unit generates the final bit rate Using multiple dividers allows flexibility different crystal frequencies wide range of rates EE3170/CC/Lecture#14-PartII 37 EE3170/CC/Lecture#14-PartII 38 BAUD Register Allows the BAUD rated (bits/second) to be specified. TCLR : Clear Baud Rate Counter Bit (Test) RCKB : SCI Baud Rate Clock Check Bit (Test) 6811 Baud Rate Selection (replaced) BAUD Bit Rate (bits per second) $ $ $ $ (Read pages ) EE3170/CC/Lecture#14-PartII 40

11 SCI Flags Two Receiver Data Flags in SCSR $102E RDRF = Receiver Data Register Full set on data move from Rcvr Shift Register to Rcvr Data Register tells program that next byte has arrived IDLE = Input Line is Idle set when line = 1 for one full character time program can use IDLE for port control To clear these flags, program must load from $102E load from $102F EE3170/CC/Lecture#14-PartII 41 SCI Flags Three Receiver Error Flags in SCSR $102E OR = Overrun Flag Set when complete character is received and RDRF flag is still set Shows program hasn t loaded previous character NF = Noise Flag Rcvr takes 3 samples near center of each bit NF is set if the 3 samples do not all agree FE = framing error flag set if the character Stop bit 1 To Clear these flags (same as Rcvr Data Flags) EE3170/CC/Lecture#14-PartII 42 SCI Flags SCSR Register Two Transmitter Data Flags in SCSR $102E TDRE = Transmitter Data Register Empty Flag Set when outgoing data moved to Xmit Shift Register Program should check it before storing next outgoing byte TC = Transmission Complete Flag Set when entire byte has been transmitted I.e. when Xmit Shift Register is emptied To clear these flags, program must load from $102E store to $102F SCSR $102E EE3170/CC/Lecture#14-PartII 43 EE3170/CC/Lecture#14-PartII 44

12 SCI Interrupts Interrupt Enable Flags in SCCR2 $102D Interrupts do not map 1:1 to flags TIE = TDRF Flag interrupt enable TCIE = TC interrupt enable RIE = Receiver Interrupt Enable shared by RDRF and OR flags ILIE = IDLE flag interrupt enable SCCR2 $102D TIE TCIE RIE ILIE EE3170/CC/Lecture#14-PartII 45 SCI Interrupts NF and FE flags can t cause interrupts. Program must read the flag bits. Program must look for noise and framing errors so it can find them. SCI has only one interrupt FFD6:FFD7 One Vector means ISR must poll the Flags in SCSR Time consuming, but not a problem SCI is very slow SCI interrupt has the lowest priority interrupt of all Again, not a problem because SCI is so slow EE3170/CC/Lecture#14-PartII 46 Setting Character Length Data can be characters or numbers. ASCII = 7-bit code can use the 8th bit for parity only need an 8-bit word Numbers are multiples of 8-bits. For parity protection, we need a nine-bit word allows selecting an 8 or 9 bit SCI word. a bit for length a bit for the ninth data bit (bit 8) Setting Character Length Length data is kept in SCCR1 $102C. M bit determines word length. 0 = 8-bits, 1 = 9-bits R8 bit holds the extra bit for incoming data. T8 bit holds the extra bit for outgoing data. Program must explicitly load or store R8 or T8. SCCR1 $102C EE3170/CC/Lecture#14-PartII 47 EE3170/CC/Lecture#14-PartII 48

13 Waking Up the SCI Port Program can tell the SCI port to sleep. Sleeping port still monitors the incoming line. sets no flag and causes no interrupts. SCI port can be awakened by Receive line idle for one full character Idle character is a space between messages. allows port to ignore rest of the current message Or a 1 in the leading bit of an incoming character embedded in a message header byte Waking Up the SCI Port Port put to sleep by setting RWU bit in SCCR2 0 = stay awake, 1 = go to sleep SCCR2 $102D Wake-up Condition set by WAKE bit in SCCR1 0 = IDLE, 1 = leading-one SCCR1 $102C EE3170/CC/Lecture#14-PartII 49 EE3170/CC/Lecture#14-PartII 50 SCI : Serial I/O Example SCI : Serial I/O Example Echo characters via the 68HC11 UART UART Universal asynchronous receiver transmitter Wait for each character and echo the character back Start Initialization SCIINT Check which SCI Source? Assume 8-bit data word, no parity, 1200 Baud. NOTE : Echo does not use Serial Interface. Echo Routine RECV Copy Character to InBuf XMIT Copy Character From OutBuf N Done? Y Setup to Xmit Setup to Recv Finish RTI RTI EE3170/CC/Lecture#14-PartII 51 EE3170/CC/Lecture#14-PartII 52

14 SCI Example SCI Example Assume 8Mhz Crystal; Generate 1200 BAUD SCP[1:0] = 11 SCR[2:0] = 011 All Flags no Initialization M = 0 : 8 data bits Wake = 0 : no wake Enable Receiver and Interrupt RIE = 1; RE = 1 Transmitter Disabled TIE = 0; TCIE = 1; TE = 0 EE3170/CC/Lecture#14-PartII 53 /Definitions BAUD equ $102B SCCR1 equ $102C SCCR2 equ $102D SCSR equ $102E SCDR equ $102F org $2000 INBUF rmb 8 OUTBUF rmb 8 org fdb org fdb $FFD6 SCIISR $FFFE MAIN EE3170/CC/Lecture#14-PartII 54 SCI Example SCI Example Initialization Set Baud Set 8 bit No Wakeup Disable Xmit Enable Recv end INIT LDS $2FFF LDAA #$33 STAA BAUD CLRA STAA SCCR1 LDAA #$24 STAA SCCR2 CLI RECV Copy Character to InBuf Setup to Xmit RTI SCIINT Check which SCI Source? XMIT Copy Character From OutBuf Setup to Recv RTI SCIISR LDX #$1000 BRSET SCSR-$1000, X, BIT5, RECV BRSET SCSR-$1000, X, BIT7, TX RTI RECV LDAA SCDR STAA INBUF * Enable Xmit BSET SCSR-$1000, X, % RTI TX LDAA OUTBUF STAA SCDR * Disable Xmit BCLR SCSR-$1000, X, % RTI EE3170/CC/Lecture#14-PartII 55 EE3170/CC/Lecture#14-PartII 56

15 Conclusions Serial I/O is used when parallel is impractical due to distance or interconnect limitations. Timing is inherent in the Serial I/O protocol. Serial I/O functional unit called UART in most modern microcontrollers. Serial I/O in 68HC11 Single functional unit for transmit/receive Single SCI Interrupt must be asked which source requested the interrupt EE3170/CC/Lecture#14-PartII 57