ATMega16 AVR AVR AVR DIP. (in-circiut programming) desktop MOSI MOSIT. AVRProg. header. (toggle)

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2 ATMega16 AVR AVR ATMega16 AVR AVR AVR DIP (in-circiut programming) desktop MOSI GND SK MISO MOSIT Ω Dontronic SK MISO AVRProg AVR109 JTAGIEII STK500 AVR header AVRProg clock I/O (toggle)

3 clock GND V ATMega16 μf clock clock LED LED

4 scan pull-up D

5 ATMega16 shift PORT low D high dispbuf D (PORTD) (RAM) dispscan high void dispscan(void){ int i, j; char digsel = 0xfe; // pattern to turn on first digit for(i=0; i<4; i++){ PORTD = dispbuf[i]; // pattern for ith digit from display buffer PORT = digsel; // turn on the ith digit for(j=0; j<2000; j++); // wait for some time, for example 250μs, for 100 scans per second PORTD = 0xff; // turn off all digits digsel=(digsel<<1)+1; // point to the next digit keyscan t t char keyscan(void){ int i, j, keycode=0; char colsel = 0xfe, t; for(i=0; i<4; i++){ PORT = colsel; for(j=0; j<2; j++); // some delay to let row data become valid t = PIN; for(j=0; j<4; j++){ if(!(t & 0x80)) return(keycode);

6 keycode++; t<<=1; colsel=colsel<<=1+1; return(keycode); (look-up table) D keyto7seg char keyto7seg(char keycode){ // key code for a sample 3x4 keboard follows // key number * # nothing // key code //7segment code 0x82 0xb7 0xc1 0xa1 0xb4 0xa8 0x88 0xb3 0x80 0xa0 0xdc 0x8d 0xe9 char table[]={0x8d,0x82,0xdc,0xa0,0x80,0xb3,0x88,0xa8,0xb4,0xa1,0xc1,0xb7,0xe9; return(table[keycode]); #asm sseg_scan: ldi r19,$fe ldi YREGLOW,low(DISPBUF) ldi YREGHIGH,high(DISPBUF) nxt_7seg: ld r20,y+ out PORTD,r20 out PORT,r19 call seg_delay ser r20 out PORTD,r20 sec rol r19 brcs nxt_7seg ret seg_delay: // delay on each 7segment push r16 push r17 ldi r17,20 sdel2: ldi r16,0 sdel1: dec r16 brne sdel1 dec r17 brne sdel2 pop r17 pop r16 ret key_scan: ldi r18,0 ldi r16, $fe knxtclmn: out PORT,r16 nop nop nop

7 in r15,pind ldi r17,4 knxtrow: lsl r15 brcs nokey ret nokey: inc r18 dec r17 brne knxtrow sec rol r16 sbrs r16,4 ret rjmp knxtclmn kcode2seg: ldi YREGLOW,low(KODETAB) ldi YREGHIGH,high(KODETAB) add YREGLOW,r18 ld r18,y ret #endasm

8 RS232 0 start bit 1 stop bit parity 1 idle 1 bps D D RS232

9 0 1 start idle stop 1 framing error 0 parity error o o o USART o 55H ATMega16 level converter ATMega TXD D

10 USART USART #asm.equ PORTA = $1b.equ PINA = $19.equ PORTB = $18.equ PINB = $16.equ PORT = $15.equ PIN = $13.equ PORTD = $12.equ PIND = $10.equ DISPBUF = $800.equ KODETAB = $810 DEF EQU.def XREGLOW = r26.def XREGHIGH = r27.def YREGLOW = r28.def YREGHIGH = r29.def ZREGLOW = r30.def ZREGHIGH = r31 #endasm hbit_delay bit_delay MHz bit_delay pop hbit_delay push ( ) #asm bit_delay: push r16 //2 push r17 //2 ldi r17,1 //1 bdel2: ldi bdel1: r16,26 //1 dec r16 //1 brne bdel1 //2 on jump - 1 for next instruction // loop1 length = 3*r16-1 dec r17 //1 brne bdel2 //2 on jump - 1 for next instruction // loop2 length = (4+loop1)*r17-1 pop r17 //2 pop ret r16 //2 //4 //total delay = 13+loop2 hbit_delay: push r16 //2 push r17 //2 ldi r17,1 hbdel2: //1 ldi r16,43 //1 hbdel1:

11 dec r16 //1 brne hbdel1 //2 on jump - 1 for next instruction // loop1 length = 3*r16-1 dec r17 //1 brne hbdel2 //2 on jump - 1 for next instruction // loop2 length = (4+loop1)*r17-1 pop pop r17 r16 //2 //2 ret //4 //total delay = 13+loop2 #endasm send7 D stack Y void send7(char a){ #asm send_7bit: ldd r19,y+0 cbi PORTD,1 call bit_delay ldi r16,7 nxt_bit: in r17,portd //1 bst r19,0 //1 bld r17,1 //1 out PORTD,r17 //1 lsr r19 //1 call bit_delay //3 dec r16 //1 brne nxt_bit //2 sbi PORTD,1 call bit_delay ret #endasm D Y+0 receive7 r 30 char receive7(void){ #asm receive_7bit: ldi r18,0 till_reset: in r17,pind //1 andi r17,1 //1 brne till_reset //2-1 call hbit_delay //4 ldi r16,7 rnxt_bit: //1 clc //1 sbic PIND,0 sec //1-2 //1 ror r18 //1 call bit_delay //4 dec r16 //1 brne rnxt_bit //2 clc ror r18

12 mov #endasm r30,r18

13 0 1

14 (LED) (RS232)

15 SISO z G(z) ωs fs s G(s) Matlab fdatool FIR IIR filter coefficients ai bi n m ( ) ( ) ( ) siso z ( ) ( ) ( ) z -1 ( ) ( ( ) ( )) FIR IIR FIR a0 IIR ωs fs D AD

16 DA D d n DA D jω Direct Digital Synthesis : DDS DA ATMega DA PWM PWM MHz Top PD7:O2 DDS Hz ldi r23,3 R11 R12 R13 R14 PWM Hz 0 1 R μs μs khz DA AD a1 a2 b0 b1 b2 a1 a2 a1 a2 1/a0 gain b0 b1 b2 fdatool 1/a0 b roundoff

17 AD AVref AD V AD 80H y x r30 r31 80h PWM #include <stdio.h> #include <mega16.h> #define _a1 0x60; #define _a2 0x62; #define _b0 0x64; #define _b1 0x66; #define _b2 0x68; #define _xn 0x6a; #define _xn_1 0x6c; #define _xn_2 0x6e; #define _yn_1 0x70; #define _yn_2 0x72; #define _gain 0x74; register char register char register char register char int int int int int int

18 int int int int int #pragma savereg- #pragma warninterrupt [AD_INT] void adc_isr(void){ #asm clr r27 ;permanent zero clr r24 ;clear 24 bit result reg; msb to lsb => r31:r30:r24 clr r30 clr r31 in r20,$05 clr r21 subi r20,$80 sbc r21,r27 push r20 push r21 ;read from AD ;x(n), prepared from data input, now is in r21:r20 lds r22, _b0 ;load b0 from RAM lds r23, _b0+1 call mult_acc ; b0*x(n) lds r22, _b1 ;load b1 from RAM lds r23, _b1+1 lds r20, _xn_1 ;load x(n-1) from RAM lds r21, _xn_1+1 call mult_acc ; b1*x(n-1) lds r22, _b2 ;load b2 from RAM lds r23, _b2+1 lds r20, _xn_2 ;load x(n-2) from RAM lds r21, _xn_2+1 call mult_acc ; b2*x(n-2) lds r22, _a1 ;load -a1 from RAM lds r23, _a1+1 lds r20, _yn_1 ;load y(n-1) from RAM lds r21, _yn_1+1 call mult_acc ; -a1*y(n-1) lds r22, _a2 ;load -a2 from RAM lds r23, _a2+1 lds r20, _yn_2 ;load y(n-2) from RAM lds r21, _yn_2+1 call mult_acc ; -a2*y(n-2) ;now store newly generated data into previous ones for nest iteration lds r20, _xn_1 ;load x(n-1) from RAM lds r21, _xn_1+1 sts _xn_2, r20 ;store x(n-2) to RAM sts _xn_2+1, r21 pop r21 pop r20 ;retrieve x(n) to put in x(n-1)

19 sts _xn_1, r20 ;store x(n-1) to RAM sts _xn_1+1, r21 lds r20, _yn_1 ;load y(n-1) from RAM lds r21, _yn_1+1 sts _yn_2, r20 ;store y(n-2) to RAM sts _yn_2+1, r21 sts _yn_1, r30 ;store new output as y(n-1) to RAM sts _yn_1+1, r31 ldi r20,$80 add r20,r30 out $2a,r20 ;out to PWM timer0 dec r15 brne mm2 dec r16 brne mm2 ldi r23,$10 mov r16,r23 in r23,$16 ldi r24,$08 eor r23,r24 out $18,r23 mm2: #endasm #asm mult_acc: muls r23, r21 ; (signed)p1-high * (signed)p2-high add r31, r0 mul r22, r20 ; p1-low * p2-low add r24, r0 adc r30, r1 adc r31, r27 mulsu r23, r20 ; (signed) p1-high * p2-low add r30, r0 adc r31, r1 mulsu r21, r22 ; (signed) p2-high * p1-low add r30, r0 adc r31, r1 ret #endasm #pragma savereg+ #pragma warn+ #pragma savereg- #pragma warninterrupt [TIM2_OVF] void timer2_ovf_isr(void){ #asm dec r14 brne m2 ldi r23,3 mov r14,r23 // sinusoid has a cycle of 57 iterations mov r22,r11 mov r23,r13

20 m1: m2: muls r22,r23 lsl r0 rol r1 lsl r0 rol r1 sub r1,r12 mov r12,r11 mov r11,r1 ldi r23,$80 add r23,r1 out $23,r23 brcc m1 sbi $18,0 rjmp m2 cbi $18,0 #endasm #pragma savereg+ #pragma warn+ void main(void){ a1=455; a2=-208; b0=1; b1=3; b2=1; PORTA=0x00; DDRA=0x00; PORTB=0x00; DDRB=0x19; PORT=0x00; DDR=0x00; PORTD=0x00; DDRD=0xA0; TR0=0x0A; TNT0=0x00; OR0=0xFA; TR1A=0x81; TR1B=0x09; TNT1H=0x00; TNT1L=0x00; IR1H=0x00; IR1L=0x00; OR1AH=0x00; OR1AL=0x00; OR1BH=0x00; OR1BL=0x00; ASSR=0x00; TR2=0x69; TNT2=0x00; OR2=0x00;

21 MUR=0x00; MUSR=0x00; // Timer(s)/ounter(s) Interrupt(s) initialization TIMSK=0x42; //0x12; //0x12; //0x40; USRA=0x00; USRB=0xD8; USR=0x86; UBRRH=0x00; UBRRL=0x67; ASR=0x80; SFIOR=0x00; // AD initialization // AD lock frequency: khz // AD Voltage Reference: AREF pin // AD Auto Trigger Source: Timer0 ompare Match // Only the 8 most significant bits of // the AD conversion result are used ADMUX=0xE0; //FIRST_AD_INPUT (AD_VREF_TYPE & 0xff); ADSRA=0xAE; SFIOR&=0x1F; SFIOR =0x60; reg11=0xfb; reg12=0x06; reg13=0x7f; #asm("sei") while (1){

22 Oversampling DA Δ-Σ PM Delta Modulation (forward) ±1 Simulink DA AD (AD) AD AD (Oversampling AD)

23 dithering AD offset (offset) ATMega V V (bandgap ref voltage) ± V Vin ATMega qtzr B A (Ain1) V ± V V khz