COMP3221: Microprocessors and Embedded Systems

Size: px

Start display at page:

Download "COMP3221: Microprocessors and Embedded Systems"

Hillary Hopkins
6 years ago
Views:

1 Embedded ystems Overview Arithmetic and Logic nstructions in AR ample AR Assembly Programs Using AL instructions Lecture 7: Arithmetic and logic nstructions Lecturer: ui Wu ession 2, AR nstruction Overview General-Purpose Registers in AR Load/store architecture At most two operands in each instruction Most instructions are two bytes long ome instructions are 4 bytes long Four ategories: Arithmetic and logic instructions Program control instruction Data transfer instruction Bit and bit test instructions 32 general-purpose registers named r0, r1,, r31 in AR assembly language Broken into two parts: with 16 registers each, r0 to r15 and r16 to r31. Each register is also assigned a memory address in RAM space. Register r0 and r26 through r31 have additional functions. o r0 is used in the instruction LPM (load program memory) o Registers x (r27 : r26), y (r29 : r28) and z (r31 : r30) are used as pointer registers Most instructions that operate on the registers have direct, single cycle access to all general registers. ome instructions such as sbci, subi, cpi, andi, ori and ldi operates only on a subset of registers. 3 4

2 General-Purpose Registers in AR (ont.) Address 0x00 r0 0x01 r1 he tatus Register in AR he tatus Register (REG) contains information about the result of the most recently executed arithmetic instruction. his information can be used for altering program flow in order to perform conditional operations. 0x1A 0x1B 0x1 0x1D r26 r27 r28 r29 x register low byte x register high byte y register low byte y register high byte REG is updated after all ALU operations. REG is not automatically stored when entering an interrupt routine and restored when returning from an interrupt. his must be handled by software. 0x1E r30 z register low byte 0x1F r31 z register high byte 5 6 he tatus Register in AR (ont.) he tatus Register in AR (ont.) Bit 7 : Global nterrupt Enable Used to enable and disable interrupts. 1: enabled. 0: disabled. he -bit is cleared by hardware after an interrupt has occurred, and is set by the RE instruction to enable subsequent interrupts. Bit 6 : Bit opy torage he Bit opy instructions BLD (Bit LoaD) and B (Bit ore) use the -bit as source or destination for the operated bit. A bit from a register in the Register File can be copied into by the B instruction, and a bit in can be copied into a bit in a register in the Register File by the BLD instruction. 7 8

3 he tatus Register in AR (ont.) he tatus Register in AR (ont.) Bit 5 : alf arry Flag he alf arry Flag indicates a alf arry (carry from bit 4) in some arithmetic operations. alf arry is useful in BD arithmetic. Bit 4 : ign Bit Exclusive OR between the egative Flag and the wo s omplement Overflow Flag ( = ). Bit 3 : wo s omplement Overflow Flag he wo s omplement Overflow Flag supports two s complement arithmetic he tatus Register in AR (ont.) he tatus Register in AR (ont.) Bit 2 : egative Flag is the most significant bit of the result. Bit 1 : ero Flag indicates a zero result in an arithmetic or logic operation. 1: zero. 0: on-zero. 11 Bit 0 : arry Flag ts meaning depends on the operation. For addition X+Y, it is the carry from the most significant bit. n other words, = Rd7 Rr7 +Rr7 O(R7) + O(R7) Rd7, where Rd7 is bit 7 of x, Rr7 is bit 7 of y, R7 is bit 7 of x+y, is the logical AD and + is the logical OR. For subtraction x-y, where x and y are unsigned integer, it indicates if x<y. f x<y, the =1; otherwise, =0. n other words, = O(Rd7) Rr7+ Rr7 R7 +R7 O(Rd7). 12

4 elected Arithmetic and Logic nstructions add, adc, inc sub, sbc, dec mul, muls, mulsu and, or, eor clr, cbr, cp, cpc, cpi, tst com, neg Refer to the main textbook (Pages 63~67) and AR nstruction et for the complete list of AL instructions. yntax: add Rd, Rr Add without arry Operation: Rd Rd + Rr Encoding: rd dddd rrrr add r1, r2 ; Add r2 to r1 add r28, r28 ; Add r28 to itself Add with arry ncrement yntax: inc Rd yntax: adc Rd, Rr Operation: Rd Rd + Rr + Encoding: rd dddd rrrr Add r1 : r0 to r3 : r2 add r2, r0 ; Add low byte adc r3, r1 ; Add high byte omments: adc is used in multi-byte addition. Operation: Rd Rd+1 Flags affected:,,, Encoding: d dddd 1011 clr r22 ; clear r22 loop: inc r22 ; ncrement r22 cpi r22, $4F ; compare r22 to $4F brne loop ; Branch to loop if not equal nop ; ontinue (do nothing 15 16

5 ubtract without arry ubtract with arry yntax: sub Rd, Rr yntax: sbc Rd, Rr Operation: Rd Rd Rr Encoding: rd dddd rrrr sub r13, r12 ; ubtract r12 from r13 Operation: Rd Rd Rr Encoding: rd dddd rrrr ubtract r1:r0 from r3:r2 sub r2, r0 ; ubtract low byte sbc r3, r1 ; ubtract with carry high byte omments: sbc is used in multi-byte subtraction Decrement Multiply Unsigned yntax: dec Rd yntax: mul Rd, Rr Operation: Rd Rd 1 Encoding: d dddd 1010 ldi r17, $10 ; Load constant in r17 Operation: r1, r0 Rr*Rd (unsigned unsigned * unsigned ) Flags affected:, Encoding: rd dddd rrrr ycles: 2 mul r6, r5 ; Multiply r6 and r5 loop: add r1, r2 ; Add r2 to r1 mov r6, r1 dec r17 ; Decrement r17 mov r5, r0 ; opy result back in r6 : r5 brne loop; ; Branch to loop if r17 0 nop ; ontinue (do nothing) 19 20

6 Multiply igned Multiply igned with Unsigned yntax: muls Rd, Rr Operands: Rd, Rr {r16, r17,, r31} Operation: r1, r0 Rr*Rd (signed signed * signed ) Flags affected:, Encoding: dddd rrrr ycles: 2 mul r17, r16 ; Multiply r17 and r16 movw r17:r16, r1:r0 ; opy result back to r17 : r16 yntax: mulsu Rd, Rr Operands: Rd, Rr {r16, r17,, r23} Operation: r1, r0 Rr*Rd (signed signed * unsigned ) Flags affected:, is set if bit 15 of the result is set; cleared otherwise. Encoding: ddd 0rrr ycles: Multiply igned with Unsigned (ont.) Example: igned multiply of two 16-bit numbers stored in r23:r22 and r21:r20 with 32-bit result stored in r19:r18:r17:r16 ow to do? Let ah and al be the high byte and low byte, respectively, of the multiplicand and bh and bb the high byte and low byte, respectively, of the multiplier. ah : al * bh : bl = (ah* al) * (bh* 2 8 +bl) = ah*bh* al*bh* ah*bl*2 8 + al*bl 23 Multiply igned with Unsigned (ont.) Example: igned multiply of two 16-bit numbers stored in r23:r22 and r21:r20 with 32-bit result stored in r19:r18:r17:r16 muls16x16_32: clr r2 muls r23, r21 ; (signed) ah * (signed) bh movw r19 : r18, r1 : r0 mul r22, r20 ; (unsigned) al * (unsigned) bl movw r17 : r16, r1: r0 mulsu r23, r20 ; (signed) ah * (unsigned) bl sbc r19, r2 ; rick here (int: what does the carry mean here?) add r17, r0 adc r18, r1 adc r19, r2 mulsu r21, r22 sbc r19, r2 ; rick here add r17, r0 adc r18, r1 adc r19, r2 ret ; (signed) bh * (unsigned) al 24

7 Lower-ase to Upper-ase.include "m64def.inc".equ size =5.def counter =r17.dseg.org 0x100 ; et the starting address of data segment to 0x100 ap_string:.byte 5.cseg Low_string:.db "hello" ldi zl, low(low_string<<1) ; Get the low byte of the address of "h" ldi zh, high(low_string<<1) ; Get the high byte of the address of "h" ldi yh, high(ap_string) ldi yl, low(ap_string) clr counter ; counter=0 25 main: Lower-ase to Upper-ase (ont.) loop: nop lpm r20, z+ ; Load a letter from flash memory subi r20, 32 ; onvert it to the capital letter st y+,r20 ; tore the capital letter in RAM inc counter cpi counter, size brlt main rjmp loop 26 Bitwise AD Bitwise OR yntax: and Rd, Rr Operation: Rd Rr Rd (Bitwise AD Rr and Rd) Encoding: rd dddd rrrr ldi r2, 0b ldi r16, 1 and r2, r16 ; r2=0b yntax: or Rd, Rr Operation: Rd Rr v Rd (Bitwise OR Rr and Rd) Encoding: rd dddd rrrr ldi r15, 0b ldi r16, 0b or r15, r16 ; Do bitwise or between registers ; r15=0b

8 Bitwise Exclusive-OR lear Bits in Register yntax: eor Rd, Rr Operation: Rd Rr Rd (Bitwise exclusive OR Rr and Rd) Encoding: rd dddd rrrr eor r4, r4 ; lear r4 eor r0, r22 ; Bitwise exclusive or between r0 and r22 ; f r0=0b and r22=0b ; then r0=0b yntax: cbr Rd, k Operands: Rd {r16, r17,, r31} and 0 k 255 Operation: Rd Rd ($FF-k) (lear the bits specified by k ) Encoding: 0111 wwww dddd wwww (wwwwwwww=$ff-k) cbr r4, 11 ; lear bits 0 and 1 of r ompare ompare with arry yntax: cp Rd, Rr Operation: Rd Rr (Rd is not changed) Encoding: rd dddd rrrr cp r4, r5 brne noteq... noteq: nop ; ompare r4 with r5 ; Branch if r4 r5 ; Branch destination (do nothing) yntax: cpc Rd, Rr Operation: Rd Rr (Rd is not changed) Encoding: rd dddd rrrr ; ompare r3:r2 with r1:r0 cp r2, r0 ; ompare low byte cpc r3, r1 ; ompare high byte brne noteq ; Branch if not equal... noteq: nop ; Branch destination (do nothing) 31 32

9 ompare with mmediate est for ero or Minus yntax: cpi Rd, k Operands: Rd {r16, r17,, r31} and 0 k 255 Operation: Rd k (Rd is not changed) Encoding: 0011 kkkk dddd kkkk cp r19, 30 ; ompare r19 with 30 brne noteq ; Branch if r noteq: nop ; Branch destination (do nothing) yntax: tst Rd Operation: Rd Rd Rd Encoding: dd dddd dddd tst r0 ; est r0 breq zero ; Branch if r0=0... zero: nop ; Branch destination (do nothing) One's omplement wo's omplement yntax: com Rd Operation: Rd $FF Rd Encoding: d dddd 0000 com r4 breq zero... zero: nop ; ake one's complement of r4 ; Branch if zero ; Branch destination (do nothing) 35 yntax: neg Rd Operation: Rd $00 Rd (he value of $80 is left unchanged) : R3 + Rd3 et if there is a borrow from bit 3; cleared otherwise Encoding: d dddd 0001 sub r11,r0 ;ubtract r0 from r11 brpl positive ;Branch if result positive neg r11 ;ake two's complement of r11 positive: nop ;Branch destination (do nothing) 36

10 Reading Material 1. AR nstruction et. 37

COMP2121: Microprocessors and Interfacing

COMP2121: Microprocessors and Interfacing nterfacing Overview Arithmetic and Logic nstructions in AR ample AR Assembly Programs Using AL instructions Lecture 8: Arithmetic and logic nstructions http://www.cse.unsw.edu.au/~cs2121 Lecturer: ui Wu