Module 2: Introduction to AVR ATmega 32 Architecture

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1 Module 2: Introduction to AVR ATmega 32 Architecture Definition of computer architecture processor operation CISC vs RISC von Neumann vs Harvard architecture AVR introduction AVR architecture

2 Architecture & Organization Definition

3 Definition of Architecture & Organization What is architecture? o Architecture is how a computer system is designed and what technologies it is compatible with. o The attributes of a system are visible to a programmer. o These attributes have a direct impact on the logical execution of a program (i.e. instruction set, number of bits used for data representation, I/O mechanisms, addressing techniques). o There two type of computer architecture. o Von Neumann architecture: a computer architecture with physically single storage and signal pathways for instructions and data. o Harvard architecture: a computer architecture with physically separate storage and signal pathways for instructions and data.

Von Neumann Architecture o The computer has single storage system(memory) for storing data as well as program to be executed. o Processor needs two clock cycles to complete an instruction.

4 Von Neumann Architecture o The computer has single storage system(memory) for storing data as well as program to be executed. o Processor needs two clock cycles to complete an instruction. Pipelining the instructions is not possible with this architecture. o In the first clock cycle the processor gets the instruction from memory and decodes it. In the next clock cycle the required data is taken from memory. For each instruction this cycle repeats and hence needs two cycles to complete an instruction. o This is a relatively older architecture and was replaced by Harvard architecture.

Harvard Architecture o The computer has two separate memories for storing data and program. o Processor can complete an instruction in one cycle if appropriate pipelining strategies are implemented.

5 Harvard Architecture o The computer has two separate memories for storing data and program. o Processor can complete an instruction in one cycle if appropriate pipelining strategies are implemented. o In the first stage of pipeline the instruction to be executed can be taken from program memory. In the second stage of pipeline data is taken from the data memory using the decoded instruction or address. o Most of the modern computing architectures are based on Harvard architecture. But the number of stages in the pipeline varies from system to system.

6 Definition of Architecture & Organization What is organization? o Computer Organization is typically refers to the operational units of the system together with their interconnection how features are implemented. o It consists of hardware details that are transparent to the programmers.

7 Processor Architecture & Organization Many computer manufacturers offer a family of computer models, all with the same architecture but with differences in organization. This gives code compatibility (at least backwards) o All Intel x86 family share the same basic architecture o The IBM System/370 family share the same basic architecture An architecture may survive many years, but its organization changes with the changing technology. o E.g. the IBM Systems/370 architecture, with few enhancements, has survived to this day as the architecture of IBM's mainframe product line.

8 Processor ISA (Industry Standard Architecture): CISC vs RISC CISC RISC Emphasis on hardware Emphasis on software Include multi-clock complex instructions Include single-clock reduce instruction only Memory-to-memory: Load and Store incorporated in instructions Small code sizes, high cycles per second Transistors used for storing complex instructions RISC vs. CISC is a topic quite popular on the Net. Every time Intel (CISC) or Apple (RISC) introduces a new CPU, the topic pops up again. Most PC's use CPU based on CISC architecture. For instance Intel and AMD CPU's are based on CISC architectures. Many claim that RICS is the architecture of the future. Register-to-register: Load and Store are independent instructions Low cycles per second, large code sizes Spends more transistors on memory registers But even though RISC has been in the market since 1980, it hasn t managed to kick CISC out of the picture, some argue that if it is really the architecture of the future it should have been able to do this by now.

9 Introduction to AVR

10 Introduction to AVR The AVR architecture was designed by two students Alf-Egil Bogen and Vegard Wollan in Norway and then was bought and developed by Atmel in There are many kind of AVR microcontroller with different properties. Except for AVR32 (32-bit microcontroller), AVRs are all 8-bit microprocessors the CPU can work only 8 bits of data at a time. Data larger that 8 bits has to be broken into 8-bit pieces to be processed by the CPU. The AVR is a modified Harvard architecture machine where program and data is stored in separate physical memory systems that appear in different address spaces, but having the ability to read data items from program memory using special instructions.

11 AVR Family Overview AVRs are generally classified into four groups: o Classic AVR (AT90Sxxxx) o This is the original AVR chip o i.e. AT90S2313, AT90S4433

12 o Mega AVR (ATmegaxxxx) AVR Family Overview o These are powerful microcontrollers with more than 120 instructions o Has lots of different peripheral capabilities, which can be used in different designs. o i.e. ATmega8, ATmega32, ATmega128

13 o Tiny AVR (ATtinyxxxx) AVR Family Overview o Has less instructions and smaller packages compared to mega family. o Can design systems with low cost and power consumption using Tiny AVRs. o i.e. ATtiny13, ATtiny25

14 o Special purpose AVR AVR Family Overview o The ICs of this group can be considered as a subset of other groups. o But their special capabilities are made for designing specific applications such USB controller, CAN controller, LCD controller, Zigbee, Ethernet controller, FPGA. o i.e. AT90PWM216,AT90USB1287

15 Let s get familiar with AVR part number ATmega128 Atmel mega group ROM =128K ATtiny44 AT90S4433 Atmel Tiny group ROM =4K Atmel Classic group ROM =4K

16 ATmega32 Pin Out

Atmega32 Pin Out Port B Clears all the Provides

These execution It pins should of are be used

for clock source Port A Reference voltage Supply for

17 Atmega32 Pin Out Port B Clears all the Provides registers supply and voltage restart the to the chip. These execution It pins should of are be used connected program to connect to +5 external crystal for clock source Port A Reference voltage Supply for voltage ADC for ADC and porta. Connect it to VCC Port D Port C I

18 I/O Port Pins & Their Function o The number of ports in the AVR family varies depending on the number of pins on the chip. o 8-pin AVR has port B only. o 64-pin version has ports A through F. o 100-pin AVR has ports A through L. o 40-pin AVR (ATmega32), has four ports: PORTA, PORTB, PORTC and PORTD. o It must be programmed first before we use any of these ports as an input or output. o Each port has three I/O registers associated with it; o PORTx: Data Register for send/out data. (Write) o DDRx: Data Direction Register. (Read/Write) o PINx: Dara Register for in/receive data. (Read only)

19 I/O Port Pins & Their Function o Each of the I/O registers are 8 bits wide, and each port has a maximum of 8 pins. o Therefore each bit of the I/O registers affects one of the pins.

20 DDRx Register o Each of the ports A-D in the ATmega32 can be used for input and output. o The DDRx I/O register is used solely for the purpose of making a given port an input or output port. o To make a port an output, write 1s to the DDRx register. o Example: Make port B as output, thus write 0b into DDRB register to make all of the pins output. o To make a port an input, write 0s to the DDRx register. o Example: Make port B as output, thus write 0b into DDRB register to make all of the pins input. 0x00 0x00 0b ( )

DDRx Register o Example: Define what happen to the pins when, 0b01110101 is write into DDRA register, as instructions below: LDI R20,0x75 ;R20 =

21 DDRx Register o Example: Define what happen to the pins when, 0b is write into DDRA register, as instructions below: LDI R20,0x75 ;R20 = 0b (binary) LDI R17, 0x0F ;R17 = ob OUT DDRA,R20 ;DDRA = R20 OUT PORTA,R17 ;PORTA =??? IN R18,PINA ;R18 =??? Lets input at PINA =

22 PINx Register o PINx register is used to read the data at the pins. o In which to bring the data into CPU from pins, we read the contents of the PINx register.

23 PORTx Register o PORTx register is used to send the data out to the pins. o However, PORTx register also can demonstrate for inputting data by putting 1s to activate the pull-up resistor.

24 AVR Architecture

25 AVR Architecture o AVR uses Harvard architecture, that has separate buses for the code and data memory. o Two kind of busses in AVR; o Program Bus provide access to Program Flash ROM. o Data Bus to bring data to the CPU.

26 o Two kinds of memory space in AVR: o Code memory space where program is stored. o Data memory space stores data. o The data memory is composed of three parts: o General register. o I/O register o Internal data SRAM AVR Data Memory purpose

27 General Purpose Registers (GPRs) in AVR o AVR microcontrollers have many registers for arithmetic and logic operations. o In the CPU, registers are used to store information temporarily. o That information could be; o A byte of data to be processed o And address pointing to the data to be fetched. o The majority of AVR registers are 8-bit registers because in AVR only one data type: 8-bit. MSB LSB o With an 8-bit data type, any data larger than 8 bits must be broken into 8-bit chunks before it is processed.

28 General Purpose Registers (GPRs) in AVR o In AVR there are 32 general purpose registers. o They are R01-R31 and are located in the lowest location of memory address. o To understand of the purpose of general purpose registers, two simple instructions LDI and ADD is used as example.

29 GPRs: LDI Instruction o LDI copies 8-bit data into general purpose registers. o K is an 8-bit value that can be (decimal), or 00-FF (hex). o Rd is R16 to R31. (Note: cannot load values into registers R0-R15 using LDI, because its not valid). o Example: Loads the R20 register with a value of 0x25 (25 in hex).

30 GPRs: ADD Instruction o ADD to add the value of Rr to Rd and put the result back into Rd register. o Example: To add two numbers such as 0x25 and 0x34, one can do the following: o Executing the above line results in R16 = 0x59 (0x25 + 0x34 = 0x59).

31 I/O Memory o The I/O memory is dedicated to specific function such as status register, timers, serial communication, I/O ports, ADC and etc. o The function of each I/O memory location is fixed by the CPU designer. o The number of locations in the data memory set aside for I/O memory depends on the pin numbers and peripheral functions supported by that chip. o But, all off the AVRs have at least 64 bytes of locations called standard I/O memory. I/O memory

32 Internal Data SRAM o Internal data SRAM widely used for storing data and parameters by AVR programmers and C compilers. o Each location of the SRAM can be accessed directly by its address. o Each location is 8 bits wide and can be used to store any data we want. o The size of SRAM can be vary from chip to chip.

33 Using Instruction With Data Memory o Earlier we saw a simple example of using LDI and ADD that uses immediate (constant) value of K and the GPRs. o Meanwhile, the AVR also allows direct access to other location in the data memory. o In this section, we will learn the instructions accessing various locations of the data memory.

Data Memory: LDS instruction o LDS (LoaD direct from data Space) instruction tells CPU to load (copy) one byte from an address in the data memory to GPR.

34 Data Memory: LDS instruction o LDS (LoaD direct from data Space) instruction tells CPU to load (copy) one byte from an address in the data memory to GPR. o After the instruction is executed, the GPR will have the same values as the location in the data memory. o Example: Loads the R5 with the contents of location 0x200. o Example: Adds the contents of location 0x300 to location 0x302.

35 Data Memory: LDS instruction

Data Memory: STS instruction o STS (STore direct to data Space) instruction tells CPU to store (copy) the contents of the GPR to an address location in the data memory.

36 Data Memory: STS instruction o STS (STore direct to data Space) instruction tells CPU to store (copy) the contents of the GPR to an address location in the data memory. o After the instruction is executed, the location in the data space will have the same value as GPR. o Example: Stores the contents of R25 to location 0x230. o Example: Loads the R16 register with value 0x55, then moves this value around to I/O registers of ports B (0x38), C (0x35) and D (0x32).

37 Data Memory: IN instruction o IN (IN from I/O location) instruction tells CPU to load one byte from an I/O register to GPR. o After the instruction is executed, the GPR will have the same value as I/O register. o Each location in I/O memory has two address: o Data memory address o I/O address address of each I/O register in comparison in comparison of the beginning of the I/O memory o IN instruction, the I/O registers are referred by the I/O address. o Example: Load R19 with the contents of location 0x10 of the I/O memory.

38 Data Memory: IN instruction

39 Data Memory: IN instruction o To work with the I/O registers more easily, we can use their names instead of their I/O addresses. o Example: Load R19 with the contents of PIND.

40 Data Memory: OUT instruction o OUT (OUT to I/O location) instruction tells CPU to store GPR to the I/O register. o After the instruction is executed, the I/O register will have the same value as GPR. o OUT instruction, the I/O registers are referred by the I/O address. o Example: Copy 0xE6 to SPL register. Note: cannot copy an immediate value to an I/O register nor to an SRAM location.

41 Data Memory: OUT instruction o Example: Copies PIND to PORTA.

42 Data Memory: MOV instruction o MOV instruction is used to copy data among the GPR registers (R0-R31). o Example: Copies the contents of R20 to R10.

43 More ALU instructions involving GPRs

44 ALU Instruction: INC o INC instruction increments the contents of Rd (register) by 1. o Example: Adds 1 to the contents of R2. o Example: Increase the contents of data memory location 0x430 by 1.

45 ALU Instruction: DEC o DEC instruction decrements the contents of Rd (register) by 1. o Example: Subtracts 1 to the contents of R10. o Example: Put the value 3 into R30, then the value of R30 is decremented three times.

46 ALU Instruction: SUB o SUB instruction tells the CPU to subtract the value of Rr from Rd and put the result back into the Rd register. o Example: Subtract 0x25 from 0x34 values. o Example: Subtracts 5 from the contents of location 0x300 and stores the result in location 0x3200.

47 ALU Instruction: Others

48 ALU Instruction: Others

49 AVR Status Register

50 AVR Status Register o Like other μps, the AVR has a flag register to indicate arithmetic condition such as the carry bit. o The flag register in the AVR is called status register (SReg) o The status register is an 8-bit register that contains of C, Z, N, V, S and H that are called conditional flags (to indicate some conditions that result after an instruction is executed).

51 o C, the carry flag AVR Status Register o The flag is set whenever there is a carry out from D7 bit, in which after an 8-bit addition or subtraction. o Z, the zero flag o The flag reflects the result of an arithmetic or logic operation. o If the result is zero, then Z=1. if the result is not zero, then Z=0. o N, the negative flag o Binary representation of signed numbers uses D7 as the sign bit. o The flag reflects the result of an arithmetic operation. o If the D7 bit is zero, then N=0 and the result is positive. But, if the D7 bit is one, then N=1 and the result is negative. o V, the overflow flag o The flag is set whenever the result of a signed number operation is too large, causing the high-order bit to overflow in the sign bit.

52 o S, the Sign flag AVR Status Register o The flag is the result of Exclusive-Oring of N and V flags. o H, Half carry flag o If there is a carry from D3 to D4 during and ADD or SUB operation, this bit is set, otherwise, it is cleared.

53 AVR Status Register: Example

54 AVR Status Register: Example D7 D4 D3 D0 1

55 AVR Status Register: Example D7 D4 D3 D0 1 1

56 AVR Status Register: Example D7 D4 D3 D0 1

AVR Status Register: Example SREG: I T H S V N Z C Interrupt ALU Temporary Sign Negative Half carry N+V Example: Show the status of the C, H, and Z flags after the addition subtraction of 0x9C 0x38

57 AVR Status Register: Example SREG: I T H S V N Z C Interrupt ALU Temporary Sign Negative Half carry N+V Example: Show the status of the C, H, and Z flags after the addition subtraction of 0x9C 0x38 of 0x23 0x9C 0x73 and 0x64 0x2F from in 0xA5 0x9C 0x52 the following the following instructions: instructions: LDI R16, LDI 0x38 R20, R0 0xA5 0x9C 0x52 ;R16 = 0x38 R1 LDI R17, LDI 0x2F R21, 0x64 0x23 0x9C 0x73 ;R17 = 0x2F R2 ADD ADD R16, SUB R17 R20, R21 ;add R17 ;add ;subtract to R16 R21 to R21 R20 from R20 SREG: I T H S V N C Solution: Solution: CPU Solution: 1 R15 R16 R17 PC Z overflow 1 because R21 is bigger than R20 and there is a borrow from D8 bit. C = 1 0 because there R21 is is not a carry bigger R30beyond than R20 the D7 and bit. there is no borrow from D8 bit. Instruction C 0 because decoder there R20 is no has carry a value beyond other the than D7 zero bit. after the subtraction. Z = 1 because there R20 is has is carry zero carry R31 value from after other D3 subtraction. than to the 0 after D4 bit. the subtraction. because there is a borrow from from the D4 D3 to D3. the D4 bit. Instruction Z H = 1 0 because Register the there R20 is (the no borrow result) has from a D4 value to D3. 0 in it after the addition. = 0 because the R16 (the result) has value other than 0 after the addition. registers Zero Carry $A5 $9C $ $ $64 $23 $9C $ $2F $DF $100 $67 $82 $ R20 R20 = 00 R16 R20 = $DF 0x67 $82 $00

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