Designing an Instruction Set

Transcription

1 Designing an Instruction Set Nerd Chef at work. move flour,bowl add milk,bowl add egg,bowl move bowl,mixer rotate mixer... WARD & HALSTEAD NERD KIT Handouts: Lecture Slides, β docs L12 Instruction Set 1

2 Let s build a simple computer Data path for computing N*(N-1) 1 N A SEL 0 1 B SEL 0 1 A LE L.E. A B LE L.E. B * -1 ANSWER L.E. = load enable. Register only loads new value when LE=1 L12 Instruction Set 2

3 A programmable control system Computing N*(N-1) with this data path is a multi-step process. We can control the processing at each step with a FSM. If we allow different control sequences to be loaded into the control FSM, then we allow the machine to be programmed. A 1 B N A A * B Control FSM A SEL B SEL A LE B LE B B - 1 A A * B L12 Instruction Set 3

4 A first program A 1 A A * B B B - 1 A A * B B N S0 S1 S2 S3 S4 Once more,writing a control program is nothing more than filling in a table S N S N+1 A sel B sel A le B le L12 Instruction Set 4

5 An optimized program A 1 B N S0 Some parts of the program can be computed simultaneously. A A * B B B - 1 A A * B S1 S2 S3 S N S N+1 A sel B sel A le B le L12 Instruction Set 5

6 Computing Factorial The advantage of a programmable control system is that we can reconfigure it to compute new functions. In order to compute N! we will need to add some new logic and an input to our control FSM. A SEL A L.E. LE 0 1 A * 1 N B SEL B L.E. LE 0 1 B -1 ANSWER =0? Control FSM A sel B sel A le B le L12 Instruction Set 6

7 Program for Factorial B N A 1 A A * B B B - 1 DONE Z=1 S0 Z=0 S1 S2 Programmability allows us to reuse data paths to solve new problems. What we need is a general purpose data path, which can be used to efficiently solve most problems as well as a easier way to control it. Z S N S N+1 A sel B sel A le B le L12 Instruction Set 7

8 Factorial Engine A LE A SEL L.E. 0 1 A 1 N B SEL B LE 0 1 L.E. B The same data paths could compute N*(N-1), Factorial,... only difference: information in control ROM. ANSWER * Control FSM A SEL B SEL A LE B LE Z S S Asel Bsel Ale Ble A=1, B=N A=A*B, B=B done -1 =0? Today s big idea: general purpose computer architecture One set of UNIVERSAL Data paths ENCODED sequence of operational steps dictate specific function to be performed... New Issue: the PROGRAM! HOW to encode the Program? L12 Instruction Set 8

9 Anatomy of an Interpreter Internal storage Data Paths control status Control Unit address data MEMORY address instructions dest +1 PC R1 R2+R3 INSTRUCTIONS coded as binary data asel bsel PROGRAM COUNTER or PC: Address of next instruction to be executed fn ALU Cc s logic to translate instructions into control signals for data path L12 Instruction Set 9

10 Questions to be answered: Data path questions: how much internal storage? what are the ALU functions? provision for constant operands? how does data get to/from memory? width (in bits) of the registers/alu? Control unit questions: how should instructions be encoded? low-level (eg, ctl signals for data path) high-level (eg, fill polygon ) next Huffman encoded (so commonly-used insts are short) etc., etc., etc. fn dest asel bsel L12 Instruction Set 10

11 β Model of Computation Processor State Main Memory PC 00 r0 r1 r2 r31 32 bits always 0 MSB bits (4 bytes) next instr MSB = most significant bit LSB = least significant bit 0 LSB Fetch/Execute loop: loop: fetch Mem[PC] PC PC = PC PC + 4 execute fetched instruction (may change PC!) PC!) repeat! Even though each memory word is 32-bits wide, for historical reasons the β uses byte memory addresses. Since each word contains four 8-bit bytes, addresses of consecutive words differ by 4. L12 Instruction Set 11

12 β Main Memory Instructions and data are initially stored in main memory (so called in order to distinguish it from other, smaller, special-purpose memories we ll learn about later). memories consist of many locations (aka words), each of which has some number of bits. In the β each memory location has 32 bits. memories have one or more access ports (multiport memories can access more than one location at a time) each port includes an address that specifies a location a data bus that supplies write data or receives read data (or both!) control signals indicating when the memory should perform an access PC VDD MADDR MOE MWE CLK A A Dual-port 32-bit Main memory ADDR OE ADDR OE WE CLK DOUT DATA INST ADDR = selects one of 2 A locations OE = output enable for READ data WE = write enable for WRITE data CLK = data written on rising edge MDATA L12 Instruction Set 12

13 β ALU Operations What the machine sees: 32-bit instruction word OP 6 r c 5 r a 5 r b 5 unused 6-bit operation field can specify one of 64 operations: arithmetic: ADD, SUB, MUL, DIV compare: CMPEQ, CMPLT, CMPLE boolean: AND, OR, XOR shift: SHL, SHR, SAR 5-bit register fields can name one of 32 registers: Ra and Rb are the operands, Rc is the destination. R31 reads as 0, unchanged by writes What we prefer to see: symbolic ASSEMBLY LANGUAGE ADD(ra, rb, rc) If rc is 31, the result is discarded and the instruction does nothing ( NOP ) Reg[rc] = Reg[ra] + Reg[rb] Add the contents of ra to the contents of rb; store the result in rc L12 Instruction Set 13

14 β ALU Operations w/ constant Alternative instruction format w/ built-in constant: OP 6 r c 5 r a 5 16 signed constant arithmetic: ADDC, SUBC, MULC, DIVC compare: CMPEQC, CMPLTC, CMPLEC boolean: ANDC, ORC, XORC shift: SHLC, SHRC, SARC ADDC(ra, const, rc) Wait! Do we really need this extra complication? Two s complement 16-bit constant for numbers from to 32767; signextended to 32 bits before use. Reg[rc] = Reg[ra] + sxt(const) Add the contents of ra to const; store the result in rc L12 Instruction Set 14

15 Do we need built-in constants? From Hennessy & Patterson Percentage of the operations that use a constant operand One One way way to to answer architectural questions is is to to evaluate the the consequences of of different choices using carefully chosen representative benchmarks (programs and/or code code sequences). Make choices that that are are best according to to some metric (cost, performance, ). ). L12 Instruction Set 15

16 β Loads & Stores OP 6 r c 5 r a 5 signed constant 16 LD(ra, const, rc) ST(rc, const, ra) Reg[rc] = Mem[Reg[ra] + sxt(const)] Fetch into rc the contents of the memory location whose address is C plus the contents of ra Abbreviation: LD(C, rc) for LD(R31, C, rc) Mem[Reg[ra] + sxt(const)] = Reg[rc] Store the contents of rc into the memory location whose address is C plus the contents of ra Abbreviation: ST(rc,C) for ST(rc, C, R31) BYTE ADDRESSES, but but only only 32-bit word word accesses to to word-aligned addresses are are supported. Low Low two two address bits bits are are ignored! L12 Instruction Set 16

17 Variables live in memory Operations done on registers Registers hold Temporary values 1000: 1004: 1008: 100C: 1010: Storage Conventions Addr assigned at compile time int x, y; y = x * 37; n r x y translates to or, more humanely, to Compilation approach: LOAD, COMPUTE, STORE LD(r31, 0x1008, r0) MULC(r0, 37, r0) ST(r0, 0x100C, r31) x=0x1008 y=0x100c LD(x, r0) MULC(r0, 37, r0) ST(r0, y) Ra defaults to R31 (0) L12 Instruction Set 17

18 Alternative Addressing Modes Absolute: (constant) Value = Mem[constant] Use: accessing static data Indirect (aka Register deferred): (Rx) Value = Mem[Reg[x]] Use: pointer accesses Displacement: constant(rx) Value = Mem[Reg[x] + constant] Use: access to local variables Indexed: (Rx + Ry) β can do these with appropriate choices for Ra and const Value = Mem[Reg[x] + Reg[y]] Use: array accesses (base+index) Memory Value = Mem[Mem[Reg[x]]] Use: access thru pointer in mem Autoincrement: (Rx)+ Value = Mem[Reg[x]]; Reg[x]++ Use: sequential pointer accesses Autodecrement: -(Rx) Value = Reg[X]--; Mem[Reg[x]] Use: stack operations Scaled: constant(rx)[ry] Argh! Need a cost/benefit analysis! Value = Mem[Reg[x] + c + d*reg[y]] Use: array accesses (base+index) L12 Instruction Set 18

19 Memory Operands: usage From Hennessy & Patterson Usage of different memory operand modes L12 Instruction Set 19

20 Translation of an Expression int x, y; y = (x-3)*(y ) x: long(0) y: long(0) c: long(123456)... LD(x, r1) SUBC(r1,3,r1) LD(y, r2) LD(C, r3) ADD(r2,r3,r2) MUL(r2,r1,r1) ST(r1,y) VARIABLES are are allocated storage in in main main memory VARIABLE references translate to to LD LD or or ST ST OPERATORS translate to to ALU ALU instructions SMALL CONSTANTS translate to to ALU ALU instructions w/ w/ built-in constant LARGE CONSTANTS translate to to initialized variables L12 Instruction Set 20

21 Summary Instructions and data are stored in 32-bit wide main memory PC contains address of next instruction to be executed normally incremented (by 4) after each instruction fetch BR/JMP instructions save PC and then modify it BR s use PC-relative addressing with a word displacement Instructions are decoded by control unit 6-bit opcode, 5-bit register fields 3-reg format: Reg[rc] = Reg[ra] op Reg[rb] 2-reg + constant format: Reg[rc] = Reg[ra] op sxt(const) LD/ST: address is Reg[ra] + sxt(const) BR: const is used as pc-relative word displacement Compilation strategy load operands from memory into regs compute using reg operands (+ small consts), reg destination store result into memory ISA design requires tradeoffs, usually based on benchmark results L12 Instruction Set 21