Allegro SPB V16 Advance
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1 Allegro SPB V16 Advance
2 Allegro SPB 16.2 Advance Import Logic Back Annotate Netlist Compare Advanced Placement Constraint Management Differential Pair
3 Import Logic Other Cadence
4 Import Logic Other 利用 Other 的方式轉出或者導入 netlist 的方式 Orcad Orcad Capture Capture Orcad Orcad Capture Capture CIS CIS Schematic Create netlist (Other allegro.dll) Back Annotate Device Device.txt.txt file + file Allegro Allegro Netlist Netlist.net.net file file Capture Capture Back Back Annotation Annotation.swp.swp file file Import Logic (Other) Export Logic (Other) Cadence Cadence Allegro Allegro PCB layout 優點 : 在 Capture 中定義可以相對簡單缺點 : 導入 netlist 和回編線路圖對複雜, 導入時需要 Device file, 回編時需要提供 Swp file
5 Import Logic Other 利用 Other 的方式轉出或者導入 netlist 的方式 1.Create netlist from Capture Tools > Create Netlist > Other 注意 : 在 9.2 版後, 程式中已經沒有含 allegro.dll 必須在 9.2 之前的版本中 allegro.dll 複製到新的版本中放置的路徑 home:\cadence\spb15.7\capture\netforms) Netlist 格式 : Device Value Part Reference nets {PCB Footprint}! {PCB Footprint}
6 Import Logic Other 2. Import netlist to Allegro Other Import > Logic > Other Allegro Netlist 格式 : ( 其中 [] 的內容可以省略 ) [PCB Footprint]! Device! [Value]! [ Tolerance];Reference Syntax check only 只做語法 check Supersede all logical data 取代現有的 Logic Append device file log 將所有使用到的 device 加到 netin log Allow etch removal during ECO 當 netlist 有所變動時則會將相關的走線刪除 Ignore FIXED property 忽略 Fixed 設定
7 Import Logic Cadence 針對 Cadence 直接導入方式, 簡稱新轉法 Create netlist (Capture Allegro) Orcad Orcad Capture Capture Orcad Orcad Capture Capture CIS CIS Create update Allegro board Back Annotate (Allegro) Schematic Import Logic (Cadence Capture) Netlist Netlist file file directory directory Pst*.dat Pst*.dat files files.brd Cadence Cadence Allegro Allegro PCB layout 優點 : Capture 可以順利跟 Allegro 做雙向的溝通缺點 : 有條件規範 Capture 與 Allegro 的 Lib
8 Import Logic Cadence 利用 Allegro 的方式轉出或者導入 netlist 的方式 1.Create netlist from Capture Tools > Create Netlist > Allegro 直接開啟 Allegro( 參考 Import Board File 將新資料寫入 Output Board File 中 ) 輸出 netlist 路徑
9 Import Logic Cadence 2. Import netlist to Allegro Allegro Import > Logic > Allegro
10 Back annotation(cadence) Property Changes Ref-des Changes Pin an Gate Swaps
11 Back annotation(other) Property Changes Ref-des Changes Pin an Gate Swaps
12 Design Compare Tools\Design Compare
13 Advanced Placement Placement in Areas ALT_SYMBOL Assign RdfDes Automatic Swapping of Functions and Pins
14 Placement in Areas 1. 針對 symbols 2. 針對 board 當你轉 netlist 的方式是用 Capture to Allegro 1. Shape Polygon 2. Class Board Geometry Subclass Top_Room 3. Edit property Room_Type 當你轉 netlist 的方式是用 Other Allegro.dll
15 ALT_Symbol 設定 1. 當你是用 Netlist Allegro 轉 Netlist 2. 當你是用 Other Allegro 轉 Netlist 在 capture 中對 part 設定 property 在 Device File 中加入參數 定義零件外型替換可在各零件的 device 檔中宣告可替換的零件外型語法為 PACKAGEPROP ALT_SYMBOLS '(Subclass:Symbol,...;Subclass:Symbol,...)' Subclass 可為 TOP 或 T 指正面零件, BOTTOM 或 B 指正面零件. 若沒指定則視為正面. 例如 C0603 可換成 C0805 或 C1206(DEVICE FILE: C0603) PACKAGE C0603 PACKAGEPROP ALT_SYMBOLS '(C0805,C1206)' PINCOUNT 2 END
16 ALT_Symbol 用法 Place Manually 選擇滑鼠右鍵 Edit move 兩者的差別在於 Place 有一個下拉式的選項讓你做選擇 Move 漸進式的替換
17 Assign RdfDes Logic Assign RefDes 先在 Options 中寫入要替換的 RefDes 在點選 Board 上遇替換的 Symbol 注意 : 替換的零件必須存在於 Database 中其腳 Pin, 電氣特性需要一致才可以互換
18 Swapping of Functions and Pins Place Swap Pins Place Swap Functions Place Swap Components
19 Swapping Pins 當你是用 Netlist Allegro 轉 Netlist 當你是用 Other Allegro 轉 Netlist 定義零件邏輯互換以 DDR184 為例宣告接點可互換為 PINSWAP. 宣告邏輯閘可互換則為各 FUNCTION Gate (Device file for 7400) PACKAGE DIP14Package name (PCB Footprint) CLASS IC Placement class PINCOUNT 14 Total number of pins in device PINORDER 7400 I0 I1 O Defines pin names for a section PINUSE 7400 IN IN OUT Specifies pin functions (relates to PINORDER) PINSWAP 7400 I0 I1 Specifies swappable pins FUNCTION G Defines a section (relates to PINORDER) FUNCTION G Ditto FUNCTION G Ditto FUNCTION G Ditto POWER VCC ; 14 Specifies power pins GROUND GND ; 7 Ditto END
20 Swapping Functions Place Swap Components 需注意的事項 Pin 腳的數量 電器的特性 相同的包裝 定義零件邏輯互換以 7400 為例宣告接點可互換為 PINSWAP. 宣告邏輯閘可互換則為各 FUNCTION Gate (Device file for 7400) PACKAGE DIP14 Package name (PCB Footprint) CLASS IC Placement class PINCOUNT 14 Total number of pins in device PINORDER 7400 I0 I1 O Defines pin names for a section PINUSE 7400 IN IN OUTSpecifies pin functions (relates to PINORDER) PINSWAP 7400 I0 I1 Specifies swappable pins FUNCTION G Defines a section (relates to PINORDER) FUNCTION G Ditto FUNCTION G Ditto FUNCTION G Ditto POWER VCC ; 14 Specifies power pins GROUND GND ; 7 Ditto END
21 Constraint Management Constraint Management UI Hierarchical Rule Management
22 Constraint Management A High-Speed Design Flow Exploration Design Capture Design Realization Topology Editor Allegro DesignEntry Allegro PCB SI Constraint Manager Allegro PCB Editor Topology Editor Topology Editor Topology Electrical Templates CSets Schematic DB Schematic Schematic Constraint View Database View Netrev Packager genfeed Front-to-back Flow Board file CM Board data sigfile models
23 Constraint Management INHERITANCE System Design Bus Diff Pair XNet Net Match Group Pin Pair Hierarchical Rule Management Multi-PCB Configuration Single PCB Named collection of Diff Pairs, XNets, or Nets Pair of XNets or Nets to be routed differentially extended Net comprised of Nets connected through resistors or connectors Basic connectivity as defined in schematic Named collection of Pin Pairs for match delay requirements Pair of Pins implying a connection that must be on the same XNet or Net OVERRIDES Highest object is the System. Goal is to assign constraints at the highest possible level. Special cases can be handled by overrides at a lower level.
24 Constraint Management Hierarchical Rule Management
25 Constraint Management Invoking the Constraint Manager Schematic Entry: Tools > Constraints > Edit Physical Layout: Setup > Constraints > Electrical Icon: Standalone: consmgr Worksheet selector Worksheet display
26 Constraint Management Selecting a Worksheet Workbook Worksheet Tree widgets are used to access worksheets. The top-most categories are ECSets and Nets. Under each category, constraints and properties are divided by discipline. These can be opened for access to entire workbook. Bottom-most expansion will open specific tab in workbook.
27 Constraint Management The User Interface for Managing Constraints Object column ECSet reference Constraint values
28 Constraint Management Design Objects The first column in every spreadsheet: Displays the objects in a hierarchical fashion Is collapsible Allows for setting constraints at the highest level and applying overrides at lower levels as necessary
29 Constraint Management Electrical Constraint Set References The second column for Net spreadsheets: Contains the ECSet that is applied to that object, which can be a Bus, Diff Pair, XNet, or Net Is usually in collapsed form to appear as a check box Can be expanded to display actual ECSet name
30 Constraint Management Viewing Constraint Values Columns define a constraint: For ECSets the columns contain constraint values. For Nets additional columns contain result information.
31 Constraint Management Controlling Colors Use View > Options to change cell color coding. Cells are color coded to indicate inheritance for constraints and status for results.
32 Constraint Management Status Indicators Placing cursor over object will result in message below Located in lower left-hand corner of user interface window Provides information on specific items in the display Progress Meter for simulations Brief descriptions of commands Reasons why items are inactive out
33 Constraint Management Basic Operations of Constraint Management Usage can be divided into three basic functions: 1. Creating Electrical Constraint Sets 2. Making associations between ECSets and design objects 3. Analyzing to see if constraints are met
34 Constraint Management Creating an Electrical Constraint Set Similar set of options is available with RMB pick in Objects column. An ECSet can be created from scratch. Prompt will appear for name. Result is empty ECSet.
35 Constraint Management Copying Electrical Constraint Sets ECSets can be copied from existing ECSets.
36 Constraint Management Referencing Electrical Constraint Sets ECSet references can be driven from ECSet or Net objects.
37 Constraint Management Analyzing Constraints Analyze > Analysis Modes Analyze > Settings
38 Constraint Management Constraint Management Summary Create ECSet Create an empty ECSet to edit later either in worksheet or Topology Editor (PCB SI) Import (*.top on disk) (PCB SI) Copy from another ECSet Create from Net object Extract Net Object into Topology Editor then Update Constraint Manager icon or File > Update (PCB SI) Associate ECSets and Net Objects Reference from ECSet Reference from Net Object Analyze Constraints DRC system based Simulation (PCB SI)
39 Differential Pair agenda Differential Pair Overhaul Logic >Assign Differential Pair Constraints > Spacing rule set Route > Connect Line Spacing Cornering Via Patterns Single Trace Mode provide the best service
40 Differential Pair proper noun 先認識一下新增的專有名詞 a.calculator 可由 User 設定的 Impedance 計算線寬, 線距.., 存在於 setup > constints> ecsets > diff pair values 中 a.primary Gap 兩條線主要的間距 b.line Width 兩條線主要的線寬 c.neck Gap/Width 兩條線次要的線寬與線距 d. Coupled Tolerance +/- -- 兩條線的線距誤差值 e.min Line Spacing 兩條線的最小間距 f.max Uncoupled Length 兩條對線無法走在一起時, 可允許的線長 g.phase Tolerance 兩條線可允許的誤差值 h.pseudo Segment Uncoupled Length 的線段用該層的 DRC 顏色表示出來, 如下圖 :
41 Differential Pair Generate Logic Assign Differential Pair 可分成自動與手動兩種 : 自動 Auto Generate 找出對線的 +- 字元舉例 Usb0+;Usb0- 手動 Diff Pair information 可用手動的方式自行尋找對線的名稱與編輯
42 Differential Pair Setup Rule
43 Differential Pair Setup Rule 點選 Assign 進行 Rule 的配對
44 Differential Pair Router Add connect with RMB options (vias( vias,, necking) 在 Property 或 ECSET 中 Neck mode 有設定此功能才有作用
45 Differential Pair Router Single trace mode 雖然 SPB16.X 新的走線方法是兩條線一起走, 不習慣的使用者也可以將他恢復單條線走線的模式, Route > Connect 中按滑鼠右鍵, 點選 Single trace mode 結果如下圖 : 若要恢復兩條線一起走, 只要再點選一次 Single trace mode 即可
46 Differential Pair Router Slide of DP object, group slide of several pairs 在 Slide 的功能裡, 對 Diff Pair Slide 可以兩條線一起做, 如下圖 : Slide 按右鍵選擇 Cut
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